This is a 64-bit Arm CPU with pipelining developed in Verilog. The instruction set of the CPU is listed below:
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ADDI Rd, Rn, Imm12: Reg[Rd] = Reg[Rn] + ZeroExtend(Imm12).
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ADDS Rd, Rn, Rm: Reg[Rd] = Reg[Rn] + Reg[Rm]. Set flags.
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B Imm26: PC = PC + SignExtend(Imm26 << 2).
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B.LT Imm19: If (flags.negative != flags.overflow) PC = PC + SignExtend(Imm19<<2).
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BL Imm26: X30 = PC + 4 (instruction after this one), PC = PC + SignExtend(Imm26<<2).
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BR Rd: PC = Reg[Rd].
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CBZ Rt, Imm19: If (Reg[Rt] == 0) PC = PC + SignExtend(Imm19<<2).
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LDUR Rt, [Rn, #Imm9]: Reg[Rt] = Mem[Reg[Rn] + SignExtend(Imm9)].
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STUR Rt, [Rn, #Imm9]: Mem[Reg[Rn] + SignExtend(Imm9)] = Reg[Rt].
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SUBS Rd, Rn, Rm: Reg[Rd] = Reg[Rn] - Reg[Rm]. Set flags.