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<h1>PDP-11/45: RK11 II</h1>
Mon 20 February 2017
by <a class="url fn" href="https://fritzm.github.io/author/fritz-mueller.html">Fritz Mueller</a>
</div>
<div><p>Okay, moving on with the RK11-C debug, the following bit of test code is modeled after that part of the
ZRKJE0 diagnotic that is trapping out:</p>
<table class="highlighttable"><tr><td class="linenos"><div class="linenodiv"><pre> 1
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24</pre></div></td><td class="code"><div class="highlight"><pre><span></span> <span class="nt">177404</span> <span class="nt">RKCS</span><span class="o">=</span><span class="nt">177404</span>
<span class="nt">000000</span> <span class="p">.</span><span class="nc">ASECT</span>
<span class="nt">001000</span> <span class="o">.=</span><span class="nt">1000</span>
<span class="nt">001000</span> <span class="nt">012706</span> <span class="nt">000770</span> <span class="nt">START</span><span class="o">:</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">770</span><span class="o">,</span><span class="nt">SP</span> <span class="o">;</span><span class="nt">INIT</span> <span class="nt">STACK</span> <span class="nt">POINTER</span>
<span class="nt">001004</span> <span class="nt">005000</span> <span class="nt">CLR</span> <span class="nt">R0</span> <span class="o">;</span><span class="nt">INIT</span> <span class="nt">TRAP</span> <span class="nt">BASE</span>
<span class="nt">001006</span> <span class="nt">012701</span> <span class="nt">000002</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">2</span><span class="o">,</span><span class="nt">R1</span> <span class="o">;</span><span class="nt">INIT</span> <span class="nt">TRAP</span> <span class="nt">DEST</span>
<span class="nt">001012</span> <span class="nt">010120</span> <span class="nt">L1</span><span class="o">:</span> <span class="nt">MOV</span> <span class="nt">R1</span><span class="o">,(</span><span class="nt">R0</span><span class="o">)+</span> <span class="o">;</span><span class="nt">STORE</span> <span class="nt">TRAP</span> <span class="nt">DEST</span>
<span class="nt">001014</span> <span class="nt">005020</span> <span class="nt">CLR</span> <span class="o">(</span><span class="nt">R0</span><span class="o">)+</span> <span class="o">;</span><span class="nt">AND</span> <span class="nt">STORE</span> <span class="nt">HALT</span> <span class="nt">AT</span> <span class="nt">TRAP</span> <span class="nt">DEST</span>
<span class="nt">001016</span> <span class="nt">062701</span> <span class="nt">000004</span> <span class="nt">ADD</span> <span class="p">#</span><span class="nn">4</span><span class="o">,</span><span class="nt">R1</span> <span class="o">;</span><span class="nt">UPDATE</span> <span class="nt">TRAP</span> <span class="nt">DEST</span>
<span class="nt">001022</span> <span class="nt">020600</span> <span class="nt">CMP</span> <span class="nt">SP</span><span class="o">,</span><span class="nt">R0</span> <span class="o">;</span><span class="nt">ALL</span> <span class="nt">TRAPS</span> <span class="nt">INITD</span><span class="o">?</span>
<span class="nt">001024</span> <span class="nt">001372</span> <span class="nt">BNE</span> <span class="nt">L1</span> <span class="o">;</span><span class="nt">IF</span> <span class="nt">NOT</span><span class="o">,</span> <span class="nt">KEEP</span> <span class="nt">GOING</span>
<span class="nt">001026</span> <span class="nt">005002</span> <span class="nt">CLR</span> <span class="nt">R2</span> <span class="o">;</span><span class="nt">INIT</span> <span class="nt">MAIN</span> <span class="nt">ITERATION</span> <span class="nt">COUNT</span>
<span class="nt">001030</span> <span class="nt">005202</span> <span class="nt">L2</span><span class="o">:</span> <span class="nt">INC</span> <span class="nt">R2</span> <span class="o">;</span><span class="nt">INC</span> <span class="nt">MAIN</span> <span class="nt">ITERATION</span> <span class="nt">COUNT</span>
<span class="nt">001032</span> <span class="nt">010237</span> <span class="nt">177570</span> <span class="nt">MOV</span> <span class="nt">R2</span><span class="o">,@</span><span class="p">#</span><span class="nn">177570</span> <span class="o">;</span><span class="nt">UPDATE</span> <span class="nt">DISPLAY</span> <span class="nt">REG</span>
<span class="nt">001036</span> <span class="nt">012700</span> <span class="nt">177404</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">RKCS</span><span class="o">,</span><span class="nt">R0</span> <span class="o">;</span><span class="nt">GET</span> <span class="nt">RKCS</span> <span class="nt">ADDRESS</span>
<span class="nt">001042</span> <span class="nt">012710</span> <span class="nt">007560</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">7560</span><span class="o">,</span><span class="p">@</span><span class="k">R0</span> <span class="p">;</span><span class="nt">SET</span> <span class="nt">RESET</span> <span class="nt">CTRLR</span> <span class="nt">CMD</span>
<span class="nt">001046</span> <span class="nt">005210</span> <span class="nt">INC</span> <span class="p">@</span><span class="k">R0</span> <span class="p">;</span><span class="nt">SET</span> <span class="nt">GO</span> <span class="nt">BIT</span>
<span class="nt">001050</span> <span class="nt">005005</span> <span class="nt">CLR</span> <span class="nt">R5</span> <span class="o">;</span><span class="nt">INIT</span> <span class="nt">CHECK</span> <span class="nt">COUNT</span>
<span class="nt">001052</span> <span class="nt">105710</span> <span class="nt">L3</span><span class="o">:</span> <span class="nt">TSTB</span> <span class="p">@</span><span class="k">R0</span> <span class="p">;</span><span class="nt">CHECK</span> <span class="nt">DONE</span> <span class="nt">BIT</span>
<span class="nt">001054</span> <span class="nt">100765</span> <span class="nt">BMI</span> <span class="nt">L2</span> <span class="o">;</span><span class="nt">IF</span> <span class="nt">SET</span><span class="o">,</span> <span class="nt">NEXT</span> <span class="nt">MAIN</span> <span class="nt">LOOP</span>
<span class="nt">001056</span> <span class="nt">005205</span> <span class="nt">INC</span> <span class="nt">R5</span> <span class="o">;</span><span class="nt">OTHERWISE</span> <span class="nt">INC</span> <span class="nt">CHECK</span> <span class="nt">COUNT</span>
<span class="nt">001060</span> <span class="nt">001374</span> <span class="nt">BNE</span> <span class="nt">L3</span> <span class="o">;</span><span class="nt">IF</span> <span class="nt">NOT</span> <span class="nt">EXPIRED</span> <span class="nt">GO</span> <span class="nt">CHECK</span> <span class="nt">AGAIN</span>
<span class="nt">001062</span> <span class="nt">000000</span> <span class="nt">HALT</span> <span class="o">;</span><span class="nt">OTHERWISE</span><span class="o">,</span> <span class="nt">HALT</span> <span class="nt">HERE</span>
<span class="nt">001000</span> <span class="p">.</span><span class="nc">END</span> <span class="nt">START</span>
</pre></div>
</td></tr></table>
<p>Running this code, the error is easily reproduced -- the machine traps on a bus timeout and halts after
anywhere from a few dozen to a few hundred iterations. Put the logic analyzer on MSYN and SSYN at the
back M105 address decode module on the RK11-C backplane and set up a trigger for long bus cycles, but
surprisingly this was not triggering even though the processor was taking a trap 4. Verified that the
trigger itself was working fine by accessing a non-existent memory location from the front panel. Hmmm...</p>
<p>Next step then was to move back to the CPU, and throw the UBC card out on extenders to get more visibility
into the trap. A further surprise here -- the problem went away when the UBC was on the extender! I was
able to run the test code above for hundreds of thousands of iterations without timeouts, and the original
ZRKJE0 diagnostic ran for over half an hour this way.</p>
<p>Took the UBC back off the extender, and the problem re-occurred, so apparently not just a bad seat. Hooked
the logic analyzer up to BUS A MSYN L, BUS A SSYN L, and UBCB TIMEOUT (1) H on the 11/45 backplane. With
this, I was able to capture lots of traces of the failure mode, which looks like this:</p>
<p><img src='/images/pdp11/timeout-trace.jpg'/></p>
<p>Here a glitch on the timeout signal is clearly visible, even though the MSYN/SSYN interval is well under
the bus timeout. The interesting thing is that bus cycles that result in a glitch all have a MSYN/SSYN
interval of 568 nanosceconds, to within a nanosecond. Cycles with a slightly different interval do not
timeout. This jibes with what I saw with the card extender also. As a further verification, replaced
the M920 bus jumper I'd been using with a 2-foot BC11, and the problem disappeared again.</p>
<p>At this point, Don over on the VCFED forum pointed out that the M920 I had been using was discontinued early
on due to negative effects on bus signal integrity, and was replaced with the M9202 (which itself contains 2
feet of BC11). The issue with the M920 is apprently that it provides so little separation that the connected
loads appear to the bus overall as a single lumped load. The M9202 separates the loads on the bus to smear
out reflections and ringing and avoid false triggers. I have tracked down an M9202 on eBay, and have also
put an inexpensive digital storage scope on order so I can start to investigate signal integrity issues like
this that are not apparent on a logic analyzer.</p></div>
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