From 92afcc76442d5a9cc1ecb833b34fe6fb9d96ad85 Mon Sep 17 00:00:00 2001 From: cscott111 Date: Tue, 21 Jun 2022 16:07:37 -0300 Subject: [PATCH] added default nettype wire to pass compiler check --- rtl/verilog/i2c_master_bit_ctrl.v | 1 + rtl/verilog/i2c_master_byte_ctrl.v | 1 + rtl/verilog/i2c_master_top.v | 1 + 3 files changed, 3 insertions(+) diff --git a/rtl/verilog/i2c_master_bit_ctrl.v b/rtl/verilog/i2c_master_bit_ctrl.v index a6a79c1..ca7d6c1 100644 --- a/rtl/verilog/i2c_master_bit_ctrl.v +++ b/rtl/verilog/i2c_master_bit_ctrl.v @@ -135,6 +135,7 @@ // `include "i2c_master_defines.v" +`default_nettype wire //do not allow undeclared wires module i2c_master_bit_ctrl ( input clk, // system clock diff --git a/rtl/verilog/i2c_master_byte_ctrl.v b/rtl/verilog/i2c_master_byte_ctrl.v index 58ca2ff..c3d95c1 100644 --- a/rtl/verilog/i2c_master_byte_ctrl.v +++ b/rtl/verilog/i2c_master_byte_ctrl.v @@ -67,6 +67,7 @@ // `include "i2c_master_defines.v" +`default_nettype wire //do not allow undeclared wires module i2c_master_byte_ctrl ( diff --git a/rtl/verilog/i2c_master_top.v b/rtl/verilog/i2c_master_top.v index ddd2811..886f2a4 100644 --- a/rtl/verilog/i2c_master_top.v +++ b/rtl/verilog/i2c_master_top.v @@ -70,6 +70,7 @@ // `include "i2c_master_defines.v" +`default_nettype wire //do not allow undeclared wires module i2c_master_top (