From 053145fd0ff208a1baddc82692a946eea7c314cb Mon Sep 17 00:00:00 2001
From: Wei Dai <daiweix@meta.com>
Date: Fri, 6 Dec 2024 09:19:02 -0800
Subject: [PATCH] fix broken AgentVoqSwitchTest after enabling noAclForTrap

Summary: ACL based rx reason traps are now disabled on DNX starting from 12.0 brcm-sai, see D65280288. These traps are replaced by explicit FBOSS ACL config instead.

Reviewed By: shri-khare

Differential Revision: D66846592

fbshipit-source-id: 7edafa7ff97d325606d09c156d4db3cc947c05b8
---
 .../agent_hw_tests/AgentVoqSwitchTests.cpp    | 48 ++-----------------
 1 file changed, 3 insertions(+), 45 deletions(-)

diff --git a/fboss/agent/test/agent_hw_tests/AgentVoqSwitchTests.cpp b/fboss/agent/test/agent_hw_tests/AgentVoqSwitchTests.cpp
index 3425413e6cf15..ee439cab5a300 100644
--- a/fboss/agent/test/agent_hw_tests/AgentVoqSwitchTests.cpp
+++ b/fboss/agent/test/agent_hw_tests/AgentVoqSwitchTests.cpp
@@ -39,28 +39,14 @@ class AgentVoqSwitchTest : public AgentHwTest {
       const AgentEnsemble& ensemble) const override {
     // Increase the query timeout to be 5sec
     FLAGS_hwswitch_query_timeout = 5000;
-    // Before m-mpu agent test, use first Asic for initialization.
-    auto switchIds = ensemble.getSw()->getHwAsicTable()->getSwitchIDs();
-    CHECK_GE(switchIds.size(), 1);
-    auto asic =
-        ensemble.getSw()->getHwAsicTable()->getHwAsic(*switchIds.cbegin());
     auto config = utility::onePortPerInterfaceConfig(
         ensemble.getSw(),
         ensemble.masterLogicalPortIds(),
         true /*interfaceHasSubnet*/);
-    const auto& cpuStreamTypes =
-        asic->getQueueStreamTypes(cfg::PortType::CPU_PORT);
-    for (const auto& cpuStreamType : cpuStreamTypes) {
-      if (asic->getDefaultNumPortQueues(
-              cpuStreamType, cfg::PortType::CPU_PORT)) {
-        // cpu queues supported
-        auto l3Asics = ensemble.getSw()->getHwAsicTable()->getL3Asics();
-        addCpuTrafficPolicy(config, l3Asics);
-        utility::addCpuQueueConfig(config, l3Asics, ensemble.isSai());
-        break;
-      }
-    }
     utility::addNetworkAIQosMaps(config, ensemble.getL3Asics());
+    utility::setDefaultCpuTrafficPolicyConfig(
+        config, ensemble.getL3Asics(), ensemble.isSai());
+    utility::addCpuQueueConfig(config, ensemble.getL3Asics(), ensemble.isSai());
     return config;
   }
 
@@ -343,34 +329,6 @@ class AgentVoqSwitchTest : public AgentHwTest {
     });
     return portDescs;
   }
-
- private:
-  void addCpuTrafficPolicy(
-      cfg::SwitchConfig& cfg,
-      std::vector<const HwAsic*>& l3Asics) const {
-    cfg::CPUTrafficPolicyConfig cpuConfig;
-    std::vector<cfg::PacketRxReasonToQueue> rxReasonToQueues;
-    std::vector<std::pair<cfg::PacketRxReason, uint16_t>>
-        rxReasonToQueueMappings = {
-            std::pair(
-                cfg::PacketRxReason::BGP,
-                utility::getCoppHighPriQueueId(l3Asics)),
-            std::pair(
-                cfg::PacketRxReason::BGPV6,
-                utility::getCoppHighPriQueueId(l3Asics)),
-            std::pair(
-                cfg::PacketRxReason::CPU_IS_NHOP,
-                utility::getCoppMidPriQueueId(l3Asics)),
-        };
-    for (auto rxEntry : rxReasonToQueueMappings) {
-      auto rxReasonToQueue = cfg::PacketRxReasonToQueue();
-      rxReasonToQueue.rxReason() = rxEntry.first;
-      rxReasonToQueue.queueId() = rxEntry.second;
-      rxReasonToQueues.push_back(rxReasonToQueue);
-    }
-    cpuConfig.rxReasonToQueueOrderedList() = rxReasonToQueues;
-    cfg.cpuTrafficPolicy() = cpuConfig;
-  }
 };
 
 class AgentVoqSwitchLineRateTest : public AgentVoqSwitchTest {