diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py
index 18780e187e..47f0f5aee6 100755
--- a/litex/soc/cores/cpu/vexriscv_smp/core.py
+++ b/litex/soc/cores/cpu/vexriscv_smp/core.py
@@ -337,7 +337,7 @@ def __init__(self, platform, variant):
 
         # DMA.
         if VexRiscvSMP.coherent_dma:
-            self.dma_bus = dma_bus = wishbone.Interface(data_width=VexRiscvSMP.dcache_width)
+            self.dma_bus = dma_bus = wishbone.Interface(data_width=VexRiscvSMP.dcache_width, address_width=32)
             dma_bus_stall   = Signal()
             dma_bus_inhibit = Signal()
             self.cpu_params.update(
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 72ae9acb4f..2ed96f46b2 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1113,8 +1113,8 @@ def add_cpu(self, name="vexriscv", variant="standard", reset_address=None, cfu=N
                 self.irq.enable()
                 if hasattr(self.cpu, "reserved_interrupts"):
                     self.cpu.interrupts.update(self.cpu.reserved_interrupts)
-                for name, loc in self.cpu.interrupts.items():
-                    self.irq.add(name, loc)
+                for irq_name, loc in self.cpu.interrupts.items():
+                    self.irq.add(irq_name, loc)
                 self.add_config("CPU_HAS_INTERRUPT")
 
             # Create optional DMA Bus (for Cache Coherence).