CVA6 + Nexys4 DDR - RAM access issues

[juanschroeder]

Hi there,

I'm trying to test the CVA6 in my Nexys4 DDR board. Unfortunately I don't have a Genesys2 board.

Basic simulation seems to work without issues, but running on the FPGA board gives errors startup: 'Memory initialization failed'.

Console seems to work fine, but again, both 'sdram_test' and 'mem_test' command seems to fail ('KO' results)
I've built the bitstream for 75MHz (default), 50MHz, 25MHz and 15MHz and the issue still happens.
Vivado says 'Timing requirements' are met for 25MHz and 15MHz builds (and not for the other two).

When running for 'smaller' sizes, mem_test seems to work well most of the time when run consecutively (except always from the first time):

`litex> mem_test 0x40000000 0x1000

Memtest at 0x40000000 (4.0KiB)...

Write: 0x40000000-0x40001000 4.0KiB

Read: 0x40000000-0x40001000 4.0KiB

Memtest OK
`

There is some kind of issue with console buffering too:

`
litex> mem_test 0x40000000000
Memtest at 0x40000000 (64.0KiB)...
Write: 0x40000000-0x40010000 64.0KiB
Read: 0x400-0x40010000 64.0
us es: 56
addr errors: 0/8192
data errors: 10712/1638emteO

`

Can you suggest a good way to debug this issue? Is there something I can check in simulation?
Can I easily add features to the 'bios' running to get more info?

Thanks!