Implementing reset comming from the CPU jtag

[Dolu1990]

Hi,

I didn't found a clean way for the CPU core.py to provide a reset (comming from its jtag debug module) to the SoC

Here is what i mean as a idea reset tree topology :

- power on reset / external async reset
  -> Debug module
  -> Soc reset

- Debug module reset from JTAG (NDM_RESET)   this guy is the subject of this issue.
  -> Soc reset

- Soc reset
  -> CPU / Interconnect / Peripherals 

So far, it has been handled in a hacky way which assumes how the board target is implemented :

litex/litex/soc/cores/cpu/vexiiriscv/core.py

Line 522 in 59fc1ca

if hasattr(soc.crg.pll, "locked") and isinstance(self.platform.toolchain, EfinityToolchain):

For Rocket, they keept their NDM_RESET floating (non-functional)

Is there any other way ?