From 773fb340792067d2850be100dec7642904d82af8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Fri, 18 Oct 2024 07:58:44 +0200 Subject: [PATCH] vexiiriscv: have opensbi behind a option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit this way opensbi things are only activated, when a linux variant is used. Signed-off-by: Fin Maaß --- litex/soc/cores/cpu/vexiiriscv/core.py | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py index dd398a918c..780198a4ac 100755 --- a/litex/soc/cores/cpu/vexiiriscv/core.py +++ b/litex/soc/cores/cpu/vexiiriscv/core.py @@ -57,6 +57,7 @@ class VexiiRiscv(CPU): with_rva = False with_dma = False with_axi3 = False + with_opensbi = False jtag_tap = False jtag_instruction = False with_cpu_clk = False @@ -163,6 +164,7 @@ def args_read(args): VexiiRiscv.vexii_args += " --relaxed-branch" if args.cpu_variant in ["linux", "debian"]: + VexiiRiscv.with_opensbi = True VexiiRiscv.vexii_args += " --with-rva --with-supervisor" VexiiRiscv.vexii_args += " --fetch-l1-ways=4 --fetch-l1-mem-data-width-min=64" VexiiRiscv.vexii_args += " --lsu-l1-ways=4 --lsu-l1-mem-data-width-min=64" @@ -366,6 +368,7 @@ def generate_netlist_name(): md5_hash.update(str(VexiiRiscv.memory_regions).encode('utf-8')) md5_hash.update(str(VexiiRiscv.vexii_args).encode('utf-8')) md5_hash.update(str(VexiiRiscv.vexii_video).encode('utf-8')) + md5_hash.update(str(VexiiRiscv.with_opensbi).encode('utf-8')) # md5_hash.update(str(VexiiRiscv.internal_bus_width).encode('utf-8')) @@ -442,12 +445,13 @@ def add_soc_components(self, soc): # Set Human-name. self.human_name = f"{self.human_name} {self.xlen}-bit" - # Set UART/Timer0 CSRs to the ones used by OpenSBI. - soc.csr.add("uart", n=2) - soc.csr.add("timer0", n=3) + if VexiiRiscv.with_opensbi: + # Set UART/Timer0 CSRs to the ones used by OpenSBI. + soc.csr.add("uart", n=2) + soc.csr.add("timer0", n=3) - # Add OpenSBI region. - soc.bus.add_region("opensbi", SoCRegion(origin=self.mem_map["main_ram"] + 0x00f0_0000, size=0x8_0000, cached=True, linker=True)) + # Add OpenSBI region. + soc.bus.add_region("opensbi", SoCRegion(origin=self.mem_map["main_ram"] + 0x00f0_0000, size=0x8_0000, cached=True, linker=True)) # Define ISA. soc.add_config("CPU_COUNT", VexiiRiscv.cpu_count)