Precheck pin check

[d-m-bailey]

Currently, the XOR check verifies that the user area - framework is consistent with expectations.

However, it does not check pin names/shapes.

It's possible for a user to relabel the pins (possibly swapping vss* and vdd*), pass LVS on the user area and submit the design.

However, when this design with modified pin names is integrated, the connections will not be as intended.

A check of the pin names and shapes against the golden version may be needed.

[d-m-bailey]

Related to this, some users totally flatten the user_analog_project_wrapper to avoid the Consistency error due to unmatched cells. This can leave many hierarchical text in the layout that interfere with the abstract extraction of the cell.

Maybe flag text that does not match the port list as a Consistency error (in addition to the pins).