Skip to content

Issues: efabless/caravel_mgmt_soc_litex

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

25 Open 28 Closed
25 Open 28 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

Constructs unsupported for synthesis error Something isn't working RTL Changes to verilog source
#136 opened Jan 3, 2024 by mo-hosni
1
Please Review: SPI DO OENb signal source error Something isn't working
#132 opened Aug 26, 2023 by dlmiles
@mo-hosni
3
The CPU is slow question Further information is requested
#129 opened Jun 22, 2023 by mo-hosni
21
Simulation with VexRISC is so slow
#124 opened Mar 8, 2023 by M0stafaRady
10
sim: ELF file is deleted after compiling
#121 opened Dec 25, 2022 by xobs
management gpio pull up and down doesn't work
#119 opened Nov 27, 2022 by M0stafaRady
@RTimothyEdwards @jeffdi
10
Linker script contain different memory size than generated regions.ld invalid This doesn't seem right
#107 opened Oct 22, 2022 by M0stafaRady
@RTimothyEdwards @jeffdi
1
Documentation on how to use io.def for pin configuration documentation Improvements or additions to documentation
#94 opened Oct 15, 2022 by marwaneltoukhy
@jeffdi
Unused directory ./lvs PnR Changes to Place & Route files
#81 opened Oct 12, 2022 by marwaneltoukhy
@RTimothyEdwards @marwaneltoukhy
SRAM second port has "no connect" inputs error Something isn't working RTL Changes to verilog source wontfix This will not be worked on
#51 opened Oct 4, 2022 by RTimothyEdwards
@jeffdi
2
add gf180mcuC variant enhancement New feature or request
#44 opened Sep 21, 2022 by proppy
1
Resource not found: serial:None while building with picorv32 error Something isn't working
#42 opened Sep 19, 2022 by rhit-painteza
'make verify' does not work error Something isn't working simulation Verilog testbenches and simulation
#40 opened Sep 15, 2022 by RTimothyEdwards
@marwaneltoukhy @M0stafaRady
1
VexRISCV core missing WFI error Something isn't working
#36 opened Apr 20, 2022 by tbialas-riverlane
[Litex] "make setup" generates the signal list twice error Something isn't working RTL Changes to verilog source
#34 opened Apr 4, 2022 by suppamax
@jeffdi
add instructions to README.md on how to run tests documentation Improvements or additions to documentation
#32 opened Mar 23, 2022 by mattvenn
@jeffdi
2
env.makefile should use MCW_ROOT to refer to caravel_mgmt_soc_litex flow Changes to Makefile and process flow
#30 opened Mar 17, 2022 by proppy
cleanup hardcoded path in makefiles flow Changes to Makefile and process flow
#29 opened Mar 17, 2022 by proppy
@jeffdi
1
ImportError: cannot import name 'SpiFlash' from 'litex.soc.cores.spi_flash' error Something isn't working flow Changes to Makefile and process flow
#26 opened Mar 11, 2022 by suppamax
add wishbone test simulation Verilog testbenches and simulation
#24 opened Mar 10, 2022 by mattvenn
@marwaneltoukhy @M0stafaRady
3
add IRQ info to docs documentation Improvements or additions to documentation
#23 opened Mar 10, 2022 by mattvenn
@jeffdi
1
add link to readthedocs on the README.md documentation Improvements or additions to documentation
#16 opened Feb 9, 2022 by mattvenn
repo is huge flow Changes to Makefile and process flow
#15 opened Feb 9, 2022 by mattvenn
mgmt_core/user_irq input_delay missing? SDC Timing files
#11 opened Jan 4, 2022 by mbalestrini
@passant5
2
Make sure design is able to boot on a Digilent Arty A7 board enhancement New feature or request
#1 opened Oct 30, 2021 by mithro
4
ProTip! Adding no:label will show everything without a label.