From 8c3c08f10826c4d5332a6d8e2fdf014b793a456a Mon Sep 17 00:00:00 2001 From: Yuxin Zhou Date: Tue, 26 Jul 2022 02:04:40 +0000 Subject: [PATCH] Release 6.1.12 --- CMakeLists.txt | 13 +- README.md | 2 +- common/CMakeLists.txt | 1 + common/inc/tx_api.h | 7 +- common/src/tx_trace_object_register.c | 15 +- .../utilities/module_binary_to_c_array.c | 139 + .../utilities/module_to_binary.c | 332 ++ .../utilities/module_to_c_array.c | 392 +++ common_smp/inc/tx_api.h | 7 +- common_smp/src/tx_trace_object_register.c | 15 +- ports/cortex_a12/ac6/inc/tx_port.h | 13 +- ports/cortex_a12/gnu/inc/tx_port.h | 13 +- ports/cortex_a15/ac6/inc/tx_port.h | 13 +- ports/cortex_a15/gnu/inc/tx_port.h | 13 +- ports/cortex_a17/ac6/inc/tx_port.h | 13 +- ports/cortex_a17/gnu/inc/tx_port.h | 13 +- ports/cortex_a5/ac6/inc/tx_port.h | 13 +- ports/cortex_a5/gnu/inc/tx_port.h | 13 +- ports/cortex_a7/ac6/inc/tx_port.h | 13 +- ports/cortex_a7/gnu/inc/tx_port.h | 13 +- ports/cortex_a8/ac6/inc/tx_port.h | 13 +- ports/cortex_a8/gnu/inc/tx_port.h | 13 +- ports/cortex_a9/ac6/inc/tx_port.h | 13 +- ports/cortex_a9/gnu/inc/tx_port.h | 13 +- .../gnu/example_build/build_threadx.bat | 5 +- .../example_build/build_threadx_sample.bat | 6 +- .../gnu/example_build/cortexm0_crt0.S} | 8 - .../gnu/example_build/cortexm0_vectors.S} | 15 +- .../gnu/example_build/sample_threadx.ld | 303 +- ports/cortex_m0/iar/CMakeLists.txt | 21 + .../keil/example_build/sample_threadx.uvoptx | 281 -- .../keil/example_build/sample_threadx.uvprojx | 433 --- ports/cortex_m0/keil/example_build/tx.uvoptx | 2672 ----------------- ports/cortex_m0/keil/example_build/tx.uvprojx | 1453 --------- ports/cortex_m23/ac6/inc/tx_port.h | 10 +- ports/cortex_m23/ac6/src/tx_misra.S | 724 +++++ .../ac6/src/tx_thread_secure_stack.c | 221 +- .../src/tx_thread_secure_stack_initialize.S | 8 +- ports/cortex_m23/gnu/inc/tx_port.h | 10 +- ports/cortex_m23/gnu/src/tx_misra.S | 724 +++++ .../gnu/src/tx_thread_secure_stack.c | 217 +- .../src/tx_thread_secure_stack_initialize.S | 8 +- ports/cortex_m23/iar/inc/tx_port.h | 10 +- ports/cortex_m23/iar/src/tx_misra.s | 658 ++-- .../iar/src/tx_thread_secure_stack.c | 225 +- .../src/tx_thread_secure_stack_initialize.s | 8 +- ports/cortex_m3/ac5/inc/tx_port.h | 13 +- ports/cortex_m3/ac6/inc/tx_port.h | 13 +- ports/cortex_m3/ac6/src/tx_misra.S | 504 +--- .../gnu/example_build/build_threadx.bat | 5 +- .../example_build/build_threadx_sample.bat | 6 +- .../gnu/example_build/cortexm3_crt0.S} | 42 +- ...simulator_startup.s => cortexm3_vectors.S} | 15 +- .../gnu/example_build/sample_threadx.ld | 303 +- .../example_build/tx_initialize_low_level.S | 303 +- ports/cortex_m3/gnu/inc/tx_port.h | 13 +- ports/cortex_m3/gnu/src/tx_misra.S | 504 +--- ports/cortex_m3/iar/CMakeLists.txt | 21 + ports/cortex_m3/iar/inc/tx_port.h | 13 +- ports/cortex_m3/iar/src/tx_misra.s | 560 +--- .../keil/example_build/ThreadX_Demo.uvopt | 2 +- .../keil/example_build/ThreadX_Demo.uvproj | 15 - .../keil/example_build/ThreadX_Library.uvopt | 2 +- .../keil/example_build/ThreadX_Library.uvproj | 15 - ports/cortex_m3/keil/inc/tx_port.h | 13 +- .../ac6/CMakeLists.txt} | 0 ports/cortex_m33/ac6/inc/tx_port.h | 23 +- .../ac6/src/tx_initialize_low_level.S | 278 ++ ports/cortex_m33/ac6/src/tx_misra.S | 719 +++++ .../ac6/src/tx_thread_secure_stack.c | 3 +- .../src/tx_thread_secure_stack_initialize.S | 8 +- .../gnu/CMakeLists.txt} | 0 ports/cortex_m33/gnu/inc/tx_port.h | 23 +- ports/cortex_m33/gnu/src/tx_misra.S | 719 +++++ .../gnu/src/tx_thread_secure_stack.c | 6 +- .../src/tx_thread_secure_stack_initialize.S | 8 +- ports/cortex_m33/iar/inc/tx_port.h | 23 +- ports/cortex_m33/iar/src/tx_misra.s | 563 +--- .../iar/src/tx_thread_secure_stack.c | 12 +- .../src/tx_thread_secure_stack_initialize.s | 8 +- ports/cortex_m4/ac5/inc/tx_port.h | 13 +- ports/cortex_m4/ac6/inc/tx_port.h | 13 +- ports/cortex_m4/ac6/src/tx_misra.S | 504 +--- .../gnu/example_build/build_threadx.bat | 387 ++- .../example_build/build_threadx_sample.bat | 12 +- .../gnu/example_build/cortexm4_crt0.S} | 8 - .../gnu/example_build/cortexm4_vectors.S} | 15 +- .../gnu/example_build/sample_threadx.ld | 303 +- ports/cortex_m4/gnu/inc/tx_port.h | 13 +- ports/cortex_m4/gnu/src/tx_misra.S | 504 +--- ports/cortex_m4/iar/CMakeLists.txt | 21 + ports/cortex_m4/iar/inc/tx_port.h | 13 +- ports/cortex_m4/iar/src/tx_misra.s | 560 +--- ports/cortex_m4/keil/inc/tx_port.h | 13 +- ports/cortex_m55/ac6/CMakeLists.txt | 21 + ports/cortex_m55/ac6/inc/tx_port.h | 21 +- .../src/tx_thread_secure_stack_initialize.S | 8 +- ports/cortex_m55/gnu/inc/tx_port.h | 21 +- .../src/tx_thread_secure_stack_initialize.S | 8 +- ports/cortex_m55/iar/inc/tx_port.h | 21 +- .../src/tx_thread_secure_stack_initialize.s | 8 +- ports/cortex_m7/ac5/inc/tx_port.h | 13 +- ports/cortex_m7/ac6/inc/tx_port.h | 13 +- ports/cortex_m7/ac6/src/tx_misra.S | 504 +--- .../gnu/example_build/build_threadx.bat | 387 ++- .../example_build/build_threadx_sample.bat | 12 +- .../gnu/example_build/cortexm7_crt0.S | 91 + .../gnu/example_build/cortexm7_vectors.S} | 33 +- .../gnu/example_build/sample_threadx.ld | 303 +- .../example_build/tx_initialize_low_level.S | 303 +- ports/cortex_m7/gnu/inc/tx_port.h | 13 +- ports/cortex_m7/gnu/src/tx_misra.S | 504 +--- ports/cortex_m7/iar/CMakeLists.txt | 21 + ports/cortex_m7/iar/inc/tx_port.h | 13 +- ports/cortex_m7/iar/src/tx_misra.s | 560 +--- ports/cortex_m85/ac6/CMakeLists.txt | 21 + ports/cortex_m85/ac6/inc/tx_port.h | 21 +- .../src/tx_thread_secure_stack_initialize.S | 8 +- ports/cortex_m85/gnu/inc/tx_port.h | 21 +- .../src/tx_thread_secure_stack_initialize.S | 8 +- ports/cortex_m85/iar/inc/tx_port.h | 21 +- .../src/tx_thread_secure_stack_initialize.s | 8 +- ports/cortex_r4/gnu/inc/tx_port.h | 11 +- ports/cortex_r5/ac6/inc/tx_port.h | 11 +- ports/cortex_r5/gnu/inc/tx_port.h | 11 +- .../ac5/example_build/build_threadx_demo.bat | 3 + .../module_manager/src/tx_thread_schedule.S | 16 +- .../module_manager/src/tx_thread_schedule.S | 16 +- .../module_manager/src/tx_thread_schedule.S | 16 +- ports_module/cortex_m23/ac6/inc/tx_port.h | 10 +- .../cortex_m23/ac6/inc/txm_module_port.h | 2 +- .../src/txm_module_thread_shell_entry.c | 2 +- .../module_manager/src/tx_thread_schedule.S | 14 +- .../src/tx_thread_secure_stack.c | 225 +- .../src/tx_thread_secure_stack_initialize.S | 10 +- .../src/tx_thread_stack_error_handler.c | 93 - ports_module/cortex_m23/gnu/inc/tx_port.h | 10 +- .../module_manager/src/tx_thread_schedule.S | 14 +- .../src/tx_thread_secure_stack.c | 221 +- .../src/tx_thread_secure_stack_initialize.S} | 75 +- .../src/tx_thread_stack_error_handler.c | 93 - ports_module/cortex_m23/iar/inc/tx_port.h | 10 +- .../module_manager/src/tx_thread_schedule.s | 14 +- .../src/tx_thread_secure_stack.c | 229 +- .../src/tx_thread_secure_stack_initialize.s} | 72 +- .../src/tx_thread_stack_error_handler.c | 93 - .../cortex_m3/ac5/inc/txm_module_port.h | 59 +- .../module_manager/src/tx_thread_schedule.s | 51 +- .../txm_module_manager_mm_register_setup.c | 71 +- .../cortex_m3/ac6/inc/txm_module_port.h | 61 +- .../src/txm_module_thread_shell_entry.c | 2 +- .../module_manager/src/tx_thread_schedule.S | 36 +- .../txm_module_manager_mm_register_setup.c | 71 +- .../example_build/build_threadx_sample.bat | 4 + .../cortex_m3/gnu/inc/txm_module_port.h | 61 +- .../module_manager/src/tx_thread_schedule.S | 52 +- .../txm_module_manager_mm_register_setup.c | 71 +- .../cortex_m3/iar/inc/txm_module_port.h | 61 +- .../module_manager/src/tx_thread_schedule.s | 53 +- .../txm_module_manager_mm_register_setup.c | 71 +- ports_module/cortex_m33/ac6/inc/tx_port.h | 19 +- .../src/txm_module_thread_shell_entry.c | 2 +- .../module_manager/src/tx_thread_schedule.S | 12 +- .../src/tx_thread_secure_stack.c | 218 +- .../src/tx_thread_secure_stack_initialize.S | 10 +- .../src/tx_thread_stack_error_handler.c | 93 - .../src/tx_thread_stack_error_notify.c | 96 - ports_module/cortex_m33/gnu/inc/tx_port.h | 19 +- .../module_manager/src/tx_thread_schedule.S | 12 +- .../src/tx_thread_secure_stack.c | 221 +- .../src/tx_thread_secure_stack_initialize.S | 8 +- .../src/tx_thread_stack_error_handler.c | 93 - .../src/tx_thread_stack_error_notify.c | 96 - ports_module/cortex_m33/iar/inc/tx_port.h | 19 +- .../module_manager/src/tx_thread_schedule.s | 12 +- .../src/tx_thread_secure_stack.c | 224 +- .../src/tx_thread_secure_stack_initialize.s} | 72 +- .../src/tx_thread_stack_error_handler.c | 93 - .../src/tx_thread_stack_error_notify.c | 96 - .../cortex_m4/ac5/inc/txm_module_port.h | 59 +- .../module_manager/src/tx_thread_schedule.s | 51 +- .../txm_module_manager_mm_register_setup.c | 71 +- .../cortex_m4/ac6/inc/txm_module_port.h | 61 +- .../src/txm_module_thread_shell_entry.c | 2 +- .../module_manager/src/tx_thread_schedule.S | 36 +- .../txm_module_manager_mm_register_setup.c | 71 +- .../example_build/build_threadx_sample.bat | 5 + .../gnu/example_build/cortexm_crt0.S | 0 .../gnu/example_build/cortexm_vectors.S | 77 + .../cortex_m4/gnu/inc/txm_module_port.h | 61 +- .../module_manager/src/tx_thread_schedule.S | 52 +- .../txm_module_manager_mm_register_setup.c | 71 +- .../cortex_m4/iar/inc/txm_module_port.h | 61 +- .../module_manager/src/tx_thread_schedule.s | 53 +- .../txm_module_manager_mm_register_setup.c | 71 +- .../cortex_m7/ac5/inc/txm_module_port.h | 59 +- .../module_manager/src/tx_thread_schedule.s | 51 +- .../txm_module_manager_mm_register_setup.c | 71 +- .../cortex_m7/ac6/inc/txm_module_port.h | 61 +- .../src/txm_module_thread_shell_entry.c | 2 +- .../module_manager/src/tx_thread_schedule.S | 36 +- .../txm_module_manager_mm_register_setup.c | 71 +- .../cortex_m7/gnu/inc/txm_module_port.h | 61 +- .../module_manager/src/tx_thread_schedule.S | 52 +- .../txm_module_manager_mm_register_setup.c | 71 +- .../cortex_m7/iar/inc/txm_module_port.h | 61 +- .../module_manager/src/tx_thread_schedule.s | 53 +- .../txm_module_manager_mm_register_setup.c | 71 +- .../example_build/sample_threadx/.cproject | 170 ++ .../ac6/example_build/sample_threadx/.project | 26 + .../sample_threadx/sample_threadx.c | 374 +++ .../sample_threadx/tx_cortex_r4.launch | 469 +++ .../gnu/src/tx_thread_smp_protect.S | 10 +- .../smp_version/tx_execution_profile.c | 1278 ++++++++ .../smp_version/tx_execution_profile.h | 93 + utility/low_power/low_power.md | 258 +- .../FreeRTOS/tx_freertos.c | 33 +- 217 files changed, 13427 insertions(+), 13461 deletions(-) create mode 100644 common_modules/module_manager/utilities/module_binary_to_c_array.c create mode 100644 common_modules/module_manager/utilities/module_to_binary.c create mode 100644 common_modules/module_manager/utilities/module_to_c_array.c rename ports/{cortex_m3/gnu/example_build/cortexm3_crt0.s => cortex_m0/gnu/example_build/cortexm0_crt0.S} (99%) rename ports/{cortex_m4/gnu/example_build/tx_simulator_startup.s => cortex_m0/gnu/example_build/cortexm0_vectors.S} (90%) create mode 100644 ports/cortex_m0/iar/CMakeLists.txt delete mode 100644 ports/cortex_m0/keil/example_build/sample_threadx.uvoptx delete mode 100644 ports/cortex_m0/keil/example_build/sample_threadx.uvprojx delete mode 100644 ports/cortex_m0/keil/example_build/tx.uvoptx delete mode 100644 ports/cortex_m0/keil/example_build/tx.uvprojx create mode 100644 ports/cortex_m23/ac6/src/tx_misra.S create mode 100644 ports/cortex_m23/gnu/src/tx_misra.S rename ports/{cortex_m4/gnu/example_build/cortexm4_crt0.s => cortex_m3/gnu/example_build/cortexm3_crt0.S} (72%) rename ports/cortex_m3/gnu/example_build/{tx_simulator_startup.s => cortexm3_vectors.S} (90%) create mode 100644 ports/cortex_m3/iar/CMakeLists.txt rename ports/{cortex_m55/ac6/CmakeLists.txt => cortex_m33/ac6/CMakeLists.txt} (100%) create mode 100644 ports/cortex_m33/ac6/src/tx_initialize_low_level.S create mode 100644 ports/cortex_m33/ac6/src/tx_misra.S rename ports/{cortex_m85/ac6/CmakeLists.txt => cortex_m33/gnu/CMakeLists.txt} (100%) create mode 100644 ports/cortex_m33/gnu/src/tx_misra.S rename ports/{cortex_m7/gnu/example_build/cortexm7_crt0.s => cortex_m4/gnu/example_build/cortexm4_crt0.S} (99%) rename ports/{cortex_m7/gnu/example_build/tx_simulator_startup.s => cortex_m4/gnu/example_build/cortexm4_vectors.S} (90%) create mode 100644 ports/cortex_m4/iar/CMakeLists.txt create mode 100644 ports/cortex_m55/ac6/CMakeLists.txt create mode 100644 ports/cortex_m7/gnu/example_build/cortexm7_crt0.S rename ports/{cortex_m0/gnu/example_build/tx_vectors.s => cortex_m7/gnu/example_build/cortexm7_vectors.S} (78%) create mode 100644 ports/cortex_m7/iar/CMakeLists.txt create mode 100644 ports/cortex_m85/ac6/CMakeLists.txt create mode 100644 ports_module/cortex_a7/ac5/example_build/build_threadx_demo.bat delete mode 100644 ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_handler.c rename ports_module/cortex_m23/{iar/module_manager/src/tx_thread_stack_error_notify.c => gnu/module_manager/src/tx_thread_secure_stack_initialize.S} (71%) delete mode 100644 ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_handler.c rename ports_module/cortex_m23/{gnu/module_manager/src/tx_thread_stack_error_notify.c => iar/module_manager/src/tx_thread_secure_stack_initialize.s} (71%) delete mode 100644 ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_handler.c create mode 100644 ports_module/cortex_m3/gnu/example_build/build_threadx_sample.bat delete mode 100644 ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_handler.c delete mode 100644 ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_notify.c delete mode 100644 ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_error_handler.c delete mode 100644 ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_error_notify.c rename ports_module/{cortex_m23/ac6/module_manager/src/tx_thread_stack_error_notify.c => cortex_m33/iar/module_manager/src/tx_thread_secure_stack_initialize.s} (71%) delete mode 100644 ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_handler.c delete mode 100644 ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_notify.c create mode 100644 ports_module/cortex_m4/gnu/example_build/build_threadx_sample.bat rename ports/cortex_m0/gnu/example_build/cortexm0_crt0.s => ports_module/cortex_m4/gnu/example_build/cortexm_crt0.S (100%) create mode 100644 ports_module/cortex_m4/gnu/example_build/cortexm_vectors.S create mode 100644 ports_module/cortex_r4/ac6/example_build/sample_threadx/.cproject create mode 100644 ports_module/cortex_r4/ac6/example_build/sample_threadx/.project create mode 100644 ports_module/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c create mode 100644 ports_module/cortex_r4/ac6/example_build/sample_threadx/tx_cortex_r4.launch create mode 100644 utility/execution_profile_kit/smp_version/tx_execution_profile.c create mode 100644 utility/execution_profile_kit/smp_version/tx_execution_profile.h diff --git a/CMakeLists.txt b/CMakeLists.txt index f931f6d43..05baf6c7b 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -31,8 +31,17 @@ endif() # Pick up the common stuff add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/common) - - +# Define the FreeRTOS adaptation layer +add_library(freertos-threadx EXCLUDE_FROM_ALL) +target_include_directories(freertos-threadx + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/utility/rtos_compatibility_layers/FreeRTOS +) +target_sources(freertos-threadx + PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/utility/rtos_compatibility_layers/FreeRTOS/tx_freertos.c +) +target_link_libraries(freertos-threadx PUBLIC threadx) # If the user provided an override, copy it to the custom directory if (NOT TX_USER_FILE) diff --git a/README.md b/README.md index c62d0af65..69dd035fa 100644 --- a/README.md +++ b/README.md @@ -87,7 +87,7 @@ Azure RTOS provides OEMs with components to secure communication and to create c # Adaptation layer for ThreadX -Azure RTOS ThreadX is an advanced real-time operating system (RTOS) designed specifically for deeply embedded applications. To help ease application migration to Auzre RTOS, ThreadX provides [adaption layers](https://github.com/azure-rtos/threadx/tree/master/utility/rtos_compatibility_layers) for various legacy RTOS APIs (FreeRTOS, POSIX, OSEK, etc.). +Azure RTOS ThreadX is an advanced real-time operating system (RTOS) designed specifically for deeply embedded applications. To help ease application migration to Azure RTOS, ThreadX provides [adaption layers](https://github.com/azure-rtos/threadx/tree/master/utility/rtos_compatibility_layers) for various legacy RTOS APIs (FreeRTOS, POSIX, OSEK, etc.). # Licensing diff --git a/common/CMakeLists.txt b/common/CMakeLists.txt index 635dd3ab9..715e64c75 100644 --- a/common/CMakeLists.txt +++ b/common/CMakeLists.txt @@ -202,6 +202,7 @@ target_sources(${PROJECT_NAME} # Add the Common/inc directory to the project include list target_include_directories(${PROJECT_NAME} + SYSTEM PUBLIC ${CMAKE_CURRENT_LIST_DIR}/inc ) diff --git a/common/inc/tx_api.h b/common/inc/tx_api.h index af3846629..d4d8e5006 100644 --- a/common/inc/tx_api.h +++ b/common/inc/tx_api.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* tx_api.h PORTABLE C */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -86,6 +86,9 @@ /* optimized the definition of */ /* TX_TIMER_TICKS_PER_SECOND, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comment(s), */ +/* update patch number, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -122,7 +125,7 @@ extern "C" { #define AZURE_RTOS_THREADX #define THREADX_MAJOR_VERSION 6 #define THREADX_MINOR_VERSION 1 -#define THREADX_PATCH_VERSION 11 +#define THREADX_PATCH_VERSION 12 /* Define the following symbol for backward compatibility */ #define EL_PRODUCT_THREADX diff --git a/common/src/tx_trace_object_register.c b/common/src/tx_trace_object_register.c index da2dafcff..f76de2f4a 100644 --- a/common/src/tx_trace_object_register.c +++ b/common/src/tx_trace_object_register.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_object_register PORTABLE C */ -/* 6.1 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,9 +69,12 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ /* resulting in version 6.1 */ +/* 07-29-2022 Scott Larson Modified comment(s), */ +/* check for null name, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ VOID _tx_trace_object_register(UCHAR object_type, VOID *object_ptr, CHAR *object_name, ULONG parameter_1, ULONG parameter_2) @@ -223,6 +226,12 @@ TX_TRACE_OBJECT_ENTRY *entry_ptr; work_ptr = TX_CHAR_TO_UCHAR_POINTER_CONVERT(object_name); work_ptr = TX_UCHAR_POINTER_ADD(work_ptr, i); + /* Determine if object_name (work_ptr) is null. */ + if (work_ptr == TX_NULL) + { + break; + } + /* Copy a character of the name. */ entry_ptr -> tx_trace_object_entry_name[i] = (UCHAR) *work_ptr; diff --git a/common_modules/module_manager/utilities/module_binary_to_c_array.c b/common_modules/module_manager/utilities/module_binary_to_c_array.c new file mode 100644 index 000000000..b02fde6eb --- /dev/null +++ b/common_modules/module_manager/utilities/module_binary_to_c_array.c @@ -0,0 +1,139 @@ +#include +#include +#include + + +/* Define the file handles. */ + +FILE *source_file; +FILE *array_file; + + +int main(int argc, char* argv[]) +{ + +int alpha; +int alpha1; +int alpha2; +int alpha3; +unsigned long address; +unsigned long column; + + + /* Determine if the proper number of files are provided. */ + if (argc != 3) + { + + /* Print an error message out and wait for user key hit. */ + printf("module_binary_to_c_array.exe - Copyright (c) Microsoft Corporation v5.8\n"); + printf("**** Error: invalid input parameter for module_binary_to_c_array.exe **** \n"); + printf(" Command Line Should be:\n\n"); + printf(" > module_binary_to_c_array source_binary_file c_array_file \n\n"); + return(1); + } + + /* Attempt to open the source file for reading. */ + source_file = fopen(argv[1], "rb"); + + /* Determine if the source file was opened properly. */ + if (source_file == NULL) + { + + /* Print an error message out and wait for user key hit. */ + printf("**** Error: open failed on binary source file **** \n"); + printf(" File: %s ", argv[1]); + return(2); + } + + /* Determine if the binary file is a valid ThreadX module. */ + alpha = fgetc(source_file); + alpha1 = fgetc(source_file); + alpha2 = fgetc(source_file); + alpha3 = fgetc(source_file); + + if ((alpha != 0x4D && alpha != 0x55) || (alpha1 != 0x4F && alpha1 != 0x44) || (alpha2 != 0x44 && alpha2 != 0x4F) || (alpha3 != 0x55 && alpha3 != 0x4D)) + { + + /* Print an error message out and wait for user key hit. */ + printf("**** Error: invalid format of binary input file **** \n"); + printf(" File: %s ", argv[1]); + return(3); + } + + /* Attempt to open the dump file for writing. */ + array_file = fopen(argv[2], "w"); + + /* Determine if the dump file was opened properly. */ + if (array_file == NULL) + { + + /* Print an error message out and wait for user key hit. */ + printf("**** Error: open failed on C array file **** \n"); + printf(" File: %s ", argv[2]); + return(4); + } + + fprintf(array_file, "/**************************** Module-Binary-to-C-array Utility **********************************/\n"); + fprintf(array_file, "/* */\n"); + fprintf(array_file, "/* Copyright (c) Microsoft Corporation Version 5.4, build date: 03-01-2018 */\n"); + fprintf(array_file, "/* */\n"); + fprintf(array_file, "/************************************************************************************************/\n\n"); + fprintf(array_file, "/* \n"); + fprintf(array_file, " Input Binary file: %30s\n", argv[1]); + fprintf(array_file, " Output C Array file: %30s\n", argv[2]); + fprintf(array_file, "*/\n\n"); + + /* Now print out the sections in a C array. */ + fprintf(array_file, "unsigned char module_code[] = {\n\n"); + fprintf(array_file, "/* Address Contents */\n\n"); + + /* Seek to the beginning of the source file. */ + fseek(source_file, 0, SEEK_SET); + + /* Initialize the variables. */ + address = 0; + column = 0; + + do + { + + /* Get character from the input file. */ + alpha = fgetc(source_file); + + /* Have we reached EOF? */ + if (alpha == EOF) + break; + + /* Print out character with a leading comma, except on the first character. */ + if (column == 0) + { + if (address != 0) + fprintf(array_file, ",\n"); + fprintf(array_file, "/* 0x%08X */ 0x%02X", address, (unsigned int) alpha); + } + else + fprintf(array_file, ", 0x%02X", (unsigned int) alpha); + + /* Move column forward. */ + column++; + + /* Are we at the end of the column? */ + if (column >= 16) + { + + column = 0; + } + + /* Move address forward. */ + address++; + } while (alpha != EOF); + + /* Finally, finish the C array containing the module code. */ + fprintf(array_file, "};\n\n"); + + /* Close files. */ + fclose(source_file); + fclose(array_file); + + return 0; +} diff --git a/common_modules/module_manager/utilities/module_to_binary.c b/common_modules/module_manager/utilities/module_to_binary.c new file mode 100644 index 000000000..77517e0d2 --- /dev/null +++ b/common_modules/module_manager/utilities/module_to_binary.c @@ -0,0 +1,332 @@ +#include +#include +#include + + +/* Define the file handles. */ + +FILE *source_file; +FILE *binary_file; + + +#define ELF_ID_STRING_SIZE 16 +#define ELF_ARM_MACHINE_TYPE 40 +#define ELF_EXECUTABLE 2 + + +typedef struct ELF_HEADER_STRUCT +{ + unsigned char elf_header_id_string[ELF_ID_STRING_SIZE]; + unsigned short elf_header_file_type; + unsigned short elf_header_machinge_type; + unsigned long elf_header_version; + unsigned long elf_header_entry_address; + unsigned long elf_header_program_header_offset; + unsigned long elf_header_section_header_offset; + unsigned long elf_header_processor_flags; + unsigned short elf_header_size; + unsigned short elf_header_program_header_size; + unsigned short elf_header_program_header_entries; + unsigned short elf_header_section_header_size; + unsigned short elf_header_section_header_entries; + unsigned short elf_header_section_string_index; +} ELF_HEADER; + + +typedef struct ELF_PROGRAM_HEADER_STRUCT +{ + unsigned long elf_program_header_type; + unsigned long elf_program_header_offset; + unsigned long elf_program_header_virtual_address; + unsigned long elf_program_header_physical_address; + unsigned long elf_program_header_file_size; + unsigned long elf_program_header_memory_size; + unsigned long elf_program_header_flags; + unsigned long elf_program_header_alignment; +} ELF_PROGRAM_HEADER; + + +typedef struct ELF_SECTION_HEADER_STRUCT +{ + unsigned long elf_section_header_name; + unsigned long elf_section_header_type; + unsigned long elf_section_header_flags; + unsigned long elf_section_header_address; + unsigned long elf_section_header_offset; + unsigned long elf_section_header_size; + unsigned long elf_section_header_link; + unsigned long elf_section_header_info; + unsigned long elf_section_header_alignment; + unsigned long elf_section_header_entry_size; +} ELF_SECTION_HEADER; + + +typedef struct ELF_SYMBOL_TABLE_ENTRY_STRUCT +{ + unsigned long elf_symbol_table_entry_name; + unsigned long elf_symbol_table_entry_address; + unsigned long elf_symbol_table_entry_size; + unsigned char elf_symbol_table_entry_info; + unsigned char elf_symbol_table_entry_other; + unsigned short elf_symbol_table_entry_shndx; + +} ELF_SYMBOL_TABLE_ENTRY; + + +typedef struct CODE_SECTION_ENTRY_STRUCT +{ + unsigned long code_section_index; + unsigned long code_section_address; + unsigned long code_section_size; +} CODE_SECTION_ENTRY; + + +/* Define global variables. */ + +ELF_HEADER header; +ELF_PROGRAM_HEADER *program_header; +ELF_SECTION_HEADER *section_header; +unsigned char *section_string_table; +unsigned char *main_string_table; +unsigned long total_symbols; +ELF_SYMBOL_TABLE_ENTRY *symbol_table; +unsigned long total_functions; +ELF_SYMBOL_TABLE_ENTRY *function_table; +CODE_SECTION_ENTRY *code_section_array; + + +/* Define helper functions. */ + +int elf_object_read(unsigned long offset, void *object_address, int object_size) +{ + +int i; +int alpha; +unsigned char *buffer; + + /* Setup the buffer pointer. */ + buffer = (unsigned char *) object_address; + + /* Seek to the proper position in the file. */ + fseek(source_file, offset, SEEK_SET); + + /* Read the ELF object. */ + for (i = 0; i < object_size; i++) + { + alpha = fgetc(source_file); + + if (alpha == EOF) + return(1); + + buffer[i] = (unsigned char) alpha; + } + + /* Return success. */ + return(0); +} + + +int main(int argc, char* argv[]) +{ + +unsigned long i, j; +unsigned long current_total; +unsigned long address; +unsigned long size; +unsigned char *code_buffer; +unsigned long code_section_index; +CODE_SECTION_ENTRY code_section_temp; +unsigned char zero_value; + + + /* Determine if the proper number of files are provided. */ + if (argc != 3) + { + + /* Print an error message out and wait for user key hit. */ + printf("module_to_binary.exe - Copyright (c) Microsoft Corporation v5.8\n"); + printf("**** Error: invalid input parameter for module_to_binary.exe **** \n"); + printf(" Command Line Should be:\n\n"); + printf(" > module_to_binary source_elf_file c_binary_file \n\n"); + return(1); + } + + /* Attempt to open the source file for reading. */ + source_file = fopen(argv[1], "rb"); + + /* Determine if the source file was opened properly. */ + if (source_file == NULL) + { + + /* Print an error message out. */ + printf("**** Error: open failed on source elf file **** \n"); + printf(" File: %s ", argv[1]); + return(2); + } + + /* Attempt to open the binary file for writing. */ + binary_file = fopen(argv[2], "wb"); + + /* Determine if the binary file was opened properly. */ + if (binary_file == NULL) + { + + /* Print an error message out and wait for user key hit. */ + printf("**** Error: open failed on binary output file **** \n"); + printf(" File: %s ", argv[2]); + return(3); + } + + /* Read the ELF header. */ + elf_object_read(0, &header, sizeof(header)); + + /* Allocate memory for the program header(s). */ + program_header = malloc(sizeof(ELF_PROGRAM_HEADER)*header.elf_header_program_header_entries); + + /* Read the program header(s). */ + elf_object_read(header.elf_header_program_header_offset, program_header, (sizeof(ELF_PROGRAM_HEADER)*header.elf_header_program_header_entries)); + + /* Allocate memory for the section header(s). */ + section_header = malloc(sizeof(ELF_SECTION_HEADER)*header.elf_header_section_header_entries); + + /* Read the section header(s). */ + elf_object_read(header.elf_header_section_header_offset, section_header, (sizeof(ELF_SECTION_HEADER)*header.elf_header_section_header_entries)); + + + /* Alocate memory for the section string table. */ + section_string_table = malloc(section_header[header.elf_header_section_string_index].elf_section_header_size); + + /* Read the section string table. */ + elf_object_read(section_header[header.elf_header_section_string_index].elf_section_header_offset, section_string_table, section_header[header.elf_header_section_string_index].elf_section_header_size); + + /* Allocate memory for the code section array. */ + code_section_array = malloc(sizeof(CODE_SECTION_ENTRY)*header.elf_header_section_header_entries); + code_section_index = 0; + + /* Print out the section header(s). */ + for (i = 0; i < header.elf_header_section_header_entries; i++) + { + + /* Determine if this section is a code section and there is a size. */ + if ((section_header[i].elf_section_header_type == 1) && (section_header[i].elf_section_header_size)) + { + + /* Check for an-instruction area. */ + if ((section_header[i].elf_section_header_flags & 0x4) || (section_header[i].elf_section_header_flags & 0x2)) + { + + /* Determine if this new section overlaps with an existing section. */ + for (j = 0; j < code_section_index; j++) + { + /* Is there an overlap? */ + if ((section_header[i].elf_section_header_address >= code_section_array[j].code_section_address) && + ((section_header[i].elf_section_header_address+section_header[i].elf_section_header_size + section_header[i].elf_section_header_offset) < (code_section_array[j].code_section_address+code_section_array[j].code_section_size))) + { + /* New section is within a current section, just disregard it. */ + break; + } + } + + /* Determine if we have an overlap. */ + if (j == code_section_index) + { + + /* Yes, we have a code section... save it! */ + code_section_array[code_section_index].code_section_index = i; + code_section_array[code_section_index].code_section_address = section_header[i].elf_section_header_address; + code_section_array[code_section_index].code_section_size = section_header[i].elf_section_header_size; + + /* Move to next code section. */ + code_section_index++; + } + } + } + } + + /* Check for no code sections. */ + if (code_section_index == 0) + { + + /* Close files. */ + fclose(source_file); + fclose(binary_file); + + return(4); + } + + /* One or more code sections have been found... let's put them in the correct order by address. */ + i = 0; + while (i+1 < code_section_index) + { + + /* Make the "ith" entry the lowest address. */ + j = i + 1; + do + { + /* Is there a new lowest address? */ + if (code_section_array[j].code_section_address < code_section_array[i].code_section_address) + { + /* Yes, swap them! */ + code_section_temp = code_section_array[i]; + code_section_array[i] = code_section_array[j]; + code_section_array[j] = code_section_temp; + } + + /* Move the inner index. */ + j++; + } while (j < code_section_index); + + /* Move top index. */ + i++; + } + + address = code_section_array[0].code_section_address; + zero_value = 0; + for (i = 0; i < code_section_index; i++) + { + + /* Determine if there is any fill characters between sections. */ + while (address < code_section_array[i].code_section_address) + { + + /* Write a zero value. */ + fwrite(&zero_value, 1, 1, binary_file); + + /* Move address forward. */ + address++; + } + + /* Now allocate memory for the code section. */ + code_buffer = malloc(code_section_array[i].code_section_size); + + /* Read in the code area. */ + j = code_section_array[i].code_section_index; + elf_object_read(section_header[j].elf_section_header_offset, code_buffer, code_section_array[i].code_section_size); + + /* Write out the contents of this program area. */ + size = code_section_array[i].code_section_size; + + j = 0; + while (size) + { + + /* Print out a byte. */ + fwrite(&code_buffer[j], 1, 1, binary_file); + + /* Move address forward. */ + address++; + + /* Decrement size. */ + size--; + + /* Move index into buffer. */ + j++; + } + } + + /* Close files. */ + fclose(source_file); + fclose(binary_file); + + return 0; +} diff --git a/common_modules/module_manager/utilities/module_to_c_array.c b/common_modules/module_manager/utilities/module_to_c_array.c new file mode 100644 index 000000000..fc72092c9 --- /dev/null +++ b/common_modules/module_manager/utilities/module_to_c_array.c @@ -0,0 +1,392 @@ +#include +#include +#include + + +/* Define the file handles. */ + +FILE *source_file; +FILE *array_file; + + +#define ELF_ID_STRING_SIZE 16 +#define ELF_ARM_MACHINE_TYPE 40 +#define ELF_EXECUTABLE 2 + + +typedef struct ELF_HEADER_STRUCT +{ + unsigned char elf_header_id_string[ELF_ID_STRING_SIZE]; + unsigned short elf_header_file_type; + unsigned short elf_header_machinge_type; + unsigned long elf_header_version; + unsigned long elf_header_entry_address; + unsigned long elf_header_program_header_offset; + unsigned long elf_header_section_header_offset; + unsigned long elf_header_processor_flags; + unsigned short elf_header_size; + unsigned short elf_header_program_header_size; + unsigned short elf_header_program_header_entries; + unsigned short elf_header_section_header_size; + unsigned short elf_header_section_header_entries; + unsigned short elf_header_section_string_index; +} ELF_HEADER; + + +typedef struct ELF_PROGRAM_HEADER_STRUCT +{ + unsigned long elf_program_header_type; + unsigned long elf_program_header_offset; + unsigned long elf_program_header_virtual_address; + unsigned long elf_program_header_physical_address; + unsigned long elf_program_header_file_size; + unsigned long elf_program_header_memory_size; + unsigned long elf_program_header_flags; + unsigned long elf_program_header_alignment; +} ELF_PROGRAM_HEADER; + + +typedef struct ELF_SECTION_HEADER_STRUCT +{ + unsigned long elf_section_header_name; + unsigned long elf_section_header_type; + unsigned long elf_section_header_flags; + unsigned long elf_section_header_address; + unsigned long elf_section_header_offset; + unsigned long elf_section_header_size; + unsigned long elf_section_header_link; + unsigned long elf_section_header_info; + unsigned long elf_section_header_alignment; + unsigned long elf_section_header_entry_size; +} ELF_SECTION_HEADER; + + +typedef struct ELF_SYMBOL_TABLE_ENTRY_STRUCT +{ + unsigned long elf_symbol_table_entry_name; + unsigned long elf_symbol_table_entry_address; + unsigned long elf_symbol_table_entry_size; + unsigned char elf_symbol_table_entry_info; + unsigned char elf_symbol_table_entry_other; + unsigned short elf_symbol_table_entry_shndx; + +} ELF_SYMBOL_TABLE_ENTRY; + + +typedef struct CODE_SECTION_ENTRY_STRUCT +{ + unsigned long code_section_index; + unsigned long code_section_address; + unsigned long code_section_size; +} CODE_SECTION_ENTRY; + + +/* Define global variables. */ + +ELF_HEADER header; +ELF_PROGRAM_HEADER *program_header; +ELF_SECTION_HEADER *section_header; +unsigned char *section_string_table; +unsigned char *main_string_table; +unsigned long total_symbols; +ELF_SYMBOL_TABLE_ENTRY *symbol_table; +unsigned long total_functions; +ELF_SYMBOL_TABLE_ENTRY *function_table; +CODE_SECTION_ENTRY *code_section_array; + + +/* Define helper functions. */ + +int elf_object_read(unsigned long offset, void *object_address, int object_size) +{ + +int i; +int alpha; +unsigned char *buffer; + + /* Setup the buffer pointer. */ + buffer = (unsigned char *) object_address; + + /* Seek to the proper position in the file. */ + fseek(source_file, offset, SEEK_SET); + + /* Read the ELF object. */ + for (i = 0; i < object_size; i++) + { + alpha = fgetc(source_file); + + if (alpha == EOF) + return(1); + + buffer[i] = (unsigned char) alpha; + } + + /* Return success. */ + return(0); +} + + +int main(int argc, char* argv[]) +{ + +unsigned long i, j, k; +unsigned long current_total; +unsigned long address; +unsigned long size; +unsigned long column; +unsigned char *code_buffer; +unsigned long code_section_index; +CODE_SECTION_ENTRY code_section_temp; + + + /* Determine if the proper number of files are provided. */ + if (argc != 3) + { + + /* Print an error message out and wait for user key hit. */ + printf("module_to_c_array.exe - Copyright (c) Microsoft Corporation v5.8\n"); + printf("**** Error: invalid input parameter for module_to_c_array.exe **** \n"); + printf(" Command Line Should be:\n\n"); + printf(" > module_to_c_array source_elf_file c_array_file \n\n"); + return(1); + } + + /* Attempt to open the source file for reading. */ + source_file = fopen(argv[1], "rb"); + + /* Determine if the source file was opened properly. */ + if (source_file == NULL) + { + + /* Print an error message out and wait for user key hit. */ + printf("**** Error: open failed on source elf file **** \n"); + printf(" File: %s ", argv[1]); + return(2); + } + + /* Attempt to open the dump file for writing. */ + array_file = fopen(argv[2], "w"); + + /* Determine if the dump file was opened properly. */ + if (array_file == NULL) + { + + /* Print an error message out and wait for user key hit. */ + printf("**** Error: open failed on C array file **** \n"); + printf(" File: %s ", argv[2]); + return(3); + } + + /* Read the ELF header. */ + elf_object_read(0, &header, sizeof(header)); + + fprintf(array_file, "/**************************** Module-to-C-array Utility *****************************************/\n"); + fprintf(array_file, "/* */\n"); + fprintf(array_file, "/* Copyright (c) Microsoft Corporation Version 5.8, build date: 03-01-2018 */\n"); + fprintf(array_file, "/* */\n"); + fprintf(array_file, "/************************************************************************************************/\n\n"); + fprintf(array_file, "/* \n"); + fprintf(array_file, " Input ELF file: %30s\n", argv[1]); + fprintf(array_file, " Output C Array file: %30s\n", argv[2]); + fprintf(array_file, "*/\n\n"); + + /* Allocate memory for the program header(s). */ + program_header = malloc(sizeof(ELF_PROGRAM_HEADER)*header.elf_header_program_header_entries); + + /* Read the program header(s). */ + elf_object_read(header.elf_header_program_header_offset, program_header, (sizeof(ELF_PROGRAM_HEADER)*header.elf_header_program_header_entries)); + + /* Allocate memory for the section header(s). */ + section_header = malloc(sizeof(ELF_SECTION_HEADER)*header.elf_header_section_header_entries); + + /* Read the section header(s). */ + elf_object_read(header.elf_header_section_header_offset, section_header, (sizeof(ELF_SECTION_HEADER)*header.elf_header_section_header_entries)); + + + /* Alocate memory for the section string table. */ + section_string_table = malloc(section_header[header.elf_header_section_string_index].elf_section_header_size); + + /* Read the section string table. */ + elf_object_read(section_header[header.elf_header_section_string_index].elf_section_header_offset, section_string_table, section_header[header.elf_header_section_string_index].elf_section_header_size); + + /* Allocate memory for the code section array. */ + code_section_array = malloc(sizeof(CODE_SECTION_ENTRY)*header.elf_header_section_header_entries); + code_section_index = 0; + + /* Print out the section header(s). */ + for (i = 0; i < header.elf_header_section_header_entries; i++) + { + + /* Determine if this section is a code section and there is a size. */ + if ((section_header[i].elf_section_header_type == 1) && (section_header[i].elf_section_header_size)) + { + + /* Check for an-instruction area. */ + if ((section_header[i].elf_section_header_flags & 0x4) || (section_header[i].elf_section_header_flags & 0x2)) + { + /* Determine if this new section overlaps with an existing section. */ + for (j = 0; j < code_section_index; j++) + { + /* Is there an overlap? */ + if ((section_header[i].elf_section_header_address >= code_section_array[j].code_section_address) && + ((section_header[i].elf_section_header_address+section_header[i].elf_section_header_size + section_header[i].elf_section_header_offset) < (code_section_array[j].code_section_address+code_section_array[j].code_section_size))) + { + /* New section is within a current section, just disregard it. */ + break; + } + } + + /* Determine if we have an overlap. */ + if (j == code_section_index) + { + + /* Yes, we have a code section... save it! */ + code_section_array[code_section_index].code_section_index = i; + code_section_array[code_section_index].code_section_address = section_header[i].elf_section_header_address; + code_section_array[code_section_index].code_section_size = section_header[i].elf_section_header_size; + + /* Move to next code section. */ + code_section_index++; + } + } + } + } + + /* Check for no code sections. */ + if (code_section_index == 0) + { + + /* Print an error message out. */ + printf("**** Error: No code sections found! **** \n"); + + fprintf(array_file, "unsigned char module_code[] = {0x00};\n\n"); + + /* Close files. */ + fclose(source_file); + fclose(array_file); + + return(4); + } + + /* One or more code sections have been found... let's put them in the correct order by address. */ + i = 0; + while (i+1 < code_section_index) + { + + /* Make the "ith" entry the lowest address. */ + j = i + 1; + do + { + /* Is there a new lowest address? */ + if (code_section_array[j].code_section_address < code_section_array[i].code_section_address) + { + /* Yes, swap them! */ + code_section_temp = code_section_array[i]; + code_section_array[i] = code_section_array[j]; + code_section_array[j] = code_section_temp; + } + + /* Move the inner index. */ + j++; + } while (j < code_section_index); + + /* Move top index. */ + i++; + } + + /* Now print out the sections in a C array. */ + fprintf(array_file, "unsigned char module_code[] = {\n\n"); + fprintf(array_file, "/* Address Contents */\n\n"); + + address = code_section_array[0].code_section_address; + column = 0; + + for (i = 0; i < code_section_index; i++) + { + + /* Determine if there is any fill characters between sections. */ + while (address < code_section_array[i].code_section_address) + { + + /* Print out a character with a leading comma, except on the first character. */ + if (column == 0) + fprintf(array_file, "/* 0x%08X */ 0x00", address); + else + fprintf(array_file, ", 0x00"); + + /* Move column forward. */ + column++; + + /* Are we at the end of the column? */ + if (column >= 16) + { + fprintf(array_file, ",\n"); + column = 0; + } + + /* Move address forward. */ + address++; + } + + /* Now allocate memory for the code section. */ + code_buffer = malloc(code_section_array[i].code_section_size); + + /* Read in the code area. */ + j = code_section_array[i].code_section_index; + elf_object_read(section_header[j].elf_section_header_offset, code_buffer, code_section_array[i].code_section_size); + + /* Write out the contents of this program area. */ + size = code_section_array[i].code_section_size; + + j = 0; + k = 0; + while (size) + { + + /* Print out a character with a leading comma, except on the first character. */ + if (column == 0) + fprintf(array_file, "/* 0x%08X */ 0x%02X", address, (unsigned int) code_buffer[j]); + else + fprintf(array_file, ", 0x%02X", (unsigned int) code_buffer[j]); + + /* Move column forward. */ + column++; + + /* Are we at the end of the column? */ + if (column >= 16) + { + + /* Is this the last byte of the image? */ + if ((size != 1) || (i+1 != code_section_index)) + { + if (k == 0) + { + k = code_section_array[i].code_section_index; + fprintf(array_file, ", /* SECTION: %s */\n", §ion_string_table[section_header[k].elf_section_header_name]); + } + else + fprintf(array_file, ",\n"); + } + column = 0; + } + + /* Move address forward. */ + address++; + + /* Decrement size. */ + size--; + + /* Move index into buffer. */ + j++; + } + } + + /* Finally, finish the C array containing the module code. */ + fprintf(array_file, "};\n\n"); + + /* Close files. */ + fclose(source_file); + fclose(array_file); + + return 0; +} diff --git a/common_smp/inc/tx_api.h b/common_smp/inc/tx_api.h index e17e0ff34..5bd9bd7ab 100644 --- a/common_smp/inc/tx_api.h +++ b/common_smp/inc/tx_api.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* tx_api.h PORTABLE SMP */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,6 +75,9 @@ /* optimized the definition of */ /* TX_TIMER_TICKS_PER_SECOND, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comment(s), */ +/* update patch number, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -127,7 +130,7 @@ extern "C" { #define AZURE_RTOS_THREADX #define THREADX_MAJOR_VERSION 6 #define THREADX_MINOR_VERSION 1 -#define THREADX_PATCH_VERSION 11 +#define THREADX_PATCH_VERSION 12 /* Define the following symbol for backward compatibility */ #define EL_PRODUCT_THREADX diff --git a/common_smp/src/tx_trace_object_register.c b/common_smp/src/tx_trace_object_register.c index da2dafcff..f76de2f4a 100644 --- a/common_smp/src/tx_trace_object_register.c +++ b/common_smp/src/tx_trace_object_register.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_object_register PORTABLE C */ -/* 6.1 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,9 +69,12 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ /* resulting in version 6.1 */ +/* 07-29-2022 Scott Larson Modified comment(s), */ +/* check for null name, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ VOID _tx_trace_object_register(UCHAR object_type, VOID *object_ptr, CHAR *object_name, ULONG parameter_1, ULONG parameter_2) @@ -223,6 +226,12 @@ TX_TRACE_OBJECT_ENTRY *entry_ptr; work_ptr = TX_CHAR_TO_UCHAR_POINTER_CONVERT(object_name); work_ptr = TX_UCHAR_POINTER_ADD(work_ptr, i); + /* Determine if object_name (work_ptr) is null. */ + if (work_ptr == TX_NULL) + { + break; + } + /* Copy a character of the name. */ entry_ptr -> tx_trace_object_entry_name[i] = (UCHAR) *work_ptr; diff --git a/ports/cortex_a12/ac6/inc/tx_port.h b/ports/cortex_a12/ac6/inc/tx_port.h index 19463de15..2155a2f62 100644 --- a/ports/cortex_a12/ac6/inc/tx_port.h +++ b/ports/cortex_a12/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARMv7-A */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -47,12 +47,15 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ /* macro definition, */ /* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ +/* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Updated comments, removed */ +/* unneeded temp variable, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -284,7 +287,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #else -#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); diff --git a/ports/cortex_a12/gnu/inc/tx_port.h b/ports/cortex_a12/gnu/inc/tx_port.h index 19463de15..2155a2f62 100644 --- a/ports/cortex_a12/gnu/inc/tx_port.h +++ b/ports/cortex_a12/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARMv7-A */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -47,12 +47,15 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ /* macro definition, */ /* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ +/* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Updated comments, removed */ +/* unneeded temp variable, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -284,7 +287,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #else -#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); diff --git a/ports/cortex_a15/ac6/inc/tx_port.h b/ports/cortex_a15/ac6/inc/tx_port.h index 19463de15..2155a2f62 100644 --- a/ports/cortex_a15/ac6/inc/tx_port.h +++ b/ports/cortex_a15/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARMv7-A */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -47,12 +47,15 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ /* macro definition, */ /* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ +/* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Updated comments, removed */ +/* unneeded temp variable, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -284,7 +287,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #else -#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); diff --git a/ports/cortex_a15/gnu/inc/tx_port.h b/ports/cortex_a15/gnu/inc/tx_port.h index 19463de15..2155a2f62 100644 --- a/ports/cortex_a15/gnu/inc/tx_port.h +++ b/ports/cortex_a15/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARMv7-A */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -47,12 +47,15 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ /* macro definition, */ /* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ +/* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Updated comments, removed */ +/* unneeded temp variable, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -284,7 +287,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #else -#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); diff --git a/ports/cortex_a17/ac6/inc/tx_port.h b/ports/cortex_a17/ac6/inc/tx_port.h index 19463de15..2155a2f62 100644 --- a/ports/cortex_a17/ac6/inc/tx_port.h +++ b/ports/cortex_a17/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARMv7-A */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -47,12 +47,15 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ /* macro definition, */ /* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ +/* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Updated comments, removed */ +/* unneeded temp variable, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -284,7 +287,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #else -#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); diff --git a/ports/cortex_a17/gnu/inc/tx_port.h b/ports/cortex_a17/gnu/inc/tx_port.h index 19463de15..2155a2f62 100644 --- a/ports/cortex_a17/gnu/inc/tx_port.h +++ b/ports/cortex_a17/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARMv7-A */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -47,12 +47,15 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ /* macro definition, */ /* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ +/* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Updated comments, removed */ +/* unneeded temp variable, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -284,7 +287,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #else -#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); diff --git a/ports/cortex_a5/ac6/inc/tx_port.h b/ports/cortex_a5/ac6/inc/tx_port.h index 19463de15..2155a2f62 100644 --- a/ports/cortex_a5/ac6/inc/tx_port.h +++ b/ports/cortex_a5/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARMv7-A */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -47,12 +47,15 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ /* macro definition, */ /* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ +/* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Updated comments, removed */ +/* unneeded temp variable, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -284,7 +287,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #else -#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); diff --git a/ports/cortex_a5/gnu/inc/tx_port.h b/ports/cortex_a5/gnu/inc/tx_port.h index 19463de15..2155a2f62 100644 --- a/ports/cortex_a5/gnu/inc/tx_port.h +++ b/ports/cortex_a5/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARMv7-A */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -47,12 +47,15 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ /* macro definition, */ /* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ +/* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Updated comments, removed */ +/* unneeded temp variable, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -284,7 +287,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #else -#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); diff --git a/ports/cortex_a7/ac6/inc/tx_port.h b/ports/cortex_a7/ac6/inc/tx_port.h index 19463de15..2155a2f62 100644 --- a/ports/cortex_a7/ac6/inc/tx_port.h +++ b/ports/cortex_a7/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARMv7-A */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -47,12 +47,15 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ /* macro definition, */ /* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ +/* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Updated comments, removed */ +/* unneeded temp variable, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -284,7 +287,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #else -#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); diff --git a/ports/cortex_a7/gnu/inc/tx_port.h b/ports/cortex_a7/gnu/inc/tx_port.h index 19463de15..2155a2f62 100644 --- a/ports/cortex_a7/gnu/inc/tx_port.h +++ b/ports/cortex_a7/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARMv7-A */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -47,12 +47,15 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ /* macro definition, */ /* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ +/* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Updated comments, removed */ +/* unneeded temp variable, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -284,7 +287,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #else -#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); diff --git a/ports/cortex_a8/ac6/inc/tx_port.h b/ports/cortex_a8/ac6/inc/tx_port.h index 19463de15..2155a2f62 100644 --- a/ports/cortex_a8/ac6/inc/tx_port.h +++ b/ports/cortex_a8/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARMv7-A */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -47,12 +47,15 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ /* macro definition, */ /* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ +/* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Updated comments, removed */ +/* unneeded temp variable, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -284,7 +287,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #else -#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); diff --git a/ports/cortex_a8/gnu/inc/tx_port.h b/ports/cortex_a8/gnu/inc/tx_port.h index 19463de15..2155a2f62 100644 --- a/ports/cortex_a8/gnu/inc/tx_port.h +++ b/ports/cortex_a8/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARMv7-A */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -47,12 +47,15 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ /* macro definition, */ /* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ +/* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Updated comments, removed */ +/* unneeded temp variable, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -284,7 +287,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #else -#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); diff --git a/ports/cortex_a9/ac6/inc/tx_port.h b/ports/cortex_a9/ac6/inc/tx_port.h index 19463de15..2155a2f62 100644 --- a/ports/cortex_a9/ac6/inc/tx_port.h +++ b/ports/cortex_a9/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARMv7-A */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -47,12 +47,15 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ /* macro definition, */ /* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ +/* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Updated comments, removed */ +/* unneeded temp variable, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -284,7 +287,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #else -#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); diff --git a/ports/cortex_a9/gnu/inc/tx_port.h b/ports/cortex_a9/gnu/inc/tx_port.h index 19463de15..2155a2f62 100644 --- a/ports/cortex_a9/gnu/inc/tx_port.h +++ b/ports/cortex_a9/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARMv7-A */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -47,12 +47,15 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ /* macro definition, */ /* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ +/* 04-25-2022 Zhen Kong Updated comments, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Updated comments, removed */ +/* unneeded temp variable, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -284,7 +287,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #else -#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); diff --git a/ports/cortex_m0/gnu/example_build/build_threadx.bat b/ports/cortex_m0/gnu/example_build/build_threadx.bat index c74b194e6..dbcac3a56 100644 --- a/ports/cortex_m0/gnu/example_build/build_threadx.bat +++ b/ports/cortex_m0/gnu/example_build/build_threadx.bat @@ -1,5 +1,4 @@ del tx.a -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb tx_initialize_low_level.S arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_stack_build.S arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_schedule.S arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_system_return.S @@ -7,7 +6,7 @@ arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_context_save.S arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_context_restore.S arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_interrupt_control.S arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_timer_interrupt.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_interrupt_control.S + arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c @@ -192,8 +191,8 @@ arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../in arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c + arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o -arm-none-eabi-ar -r tx.a tx_thread_interrupt_control.o arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o diff --git a/ports/cortex_m0/gnu/example_build/build_threadx_sample.bat b/ports/cortex_m0/gnu/example_build/build_threadx_sample.bat index 96c754d58..e0c7b374b 100644 --- a/ports/cortex_m0/gnu/example_build/build_threadx_sample.bat +++ b/ports/cortex_m0/gnu/example_build/build_threadx_sample.bat @@ -1,7 +1,5 @@ -arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb tx_vectors.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb cortexm0_vectors.S arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb cortexm0_crt0.S arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb tx_initialize_low_level.S arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc sample_threadx.c -arm-none-eabi-ld -A cortex-m0 -ereset_handler -T sample_threadx.ld tx_vectors.o cortexm0_crt0.o tx_initialize_low_level.o sample_threadx.o tx.a libgcc.a -o sample_threadx.out -M > sample_threadx.map - - +arm-none-eabi-gcc -g -mcpu=cortex-m0 -mthumb -T sample_threadx.ld -ereset_handler -nostartfiles -o sample_threadx.out -Wl,-Map=sample_threadx.map cortexm0_vectors.o cortexm0_crt0.o tx_initialize_low_level.o sample_threadx.o tx.a diff --git a/ports/cortex_m3/gnu/example_build/cortexm3_crt0.s b/ports/cortex_m0/gnu/example_build/cortexm0_crt0.S similarity index 99% rename from ports/cortex_m3/gnu/example_build/cortexm3_crt0.s rename to ports/cortex_m0/gnu/example_build/cortexm0_crt0.S index d4cb16360..bb530ac5a 100644 --- a/ports/cortex_m3/gnu/example_build/cortexm3_crt0.s +++ b/ports/cortex_m0/gnu/example_build/cortexm0_crt0.S @@ -13,7 +13,6 @@ _start: ldr r1, =__stack_end__ mov sp, r1 - /* Copy initialised sections into RAM if required. */ ldr r0, =__data_load_start__ ldr r1, =__data_start__ @@ -47,7 +46,6 @@ _start: mov r2, #0 bl crt0_memory_set - /* Setup heap - not recommended for Threadx but here for compatibility reasons */ ldr r0, = __heap_start__ ldr r1, = __heap_end__ @@ -57,7 +55,6 @@ _start: add r0, r0, #4 str r1, [r0] - /* constructors in case of using C++ */ ldr r0, =__ctors_start__ ldr r1, =__ctors_end__ @@ -72,13 +69,11 @@ crt0_ctor_loop: b crt0_ctor_loop crt0_ctor_end: - /* Setup call frame for main() */ mov r0, #0 mov lr, r0 mov r12, sp - start: /* Jump to main() */ mov r0, #0 @@ -93,7 +88,6 @@ crt0_exit_loop: /* Startup helper functions. */ - crt0_memory_copy: cmp r0, r1 beq memory_copy_done @@ -109,7 +103,6 @@ memory_copy_loop: memory_copy_done: bx lr - crt0_memory_set: cmp r0, r1 beq memory_set_done @@ -119,7 +112,6 @@ crt0_memory_set: memory_set_done: bx lr - /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */ .section .stack, "wa", %nobits .section .stack_process, "wa", %nobits diff --git a/ports/cortex_m4/gnu/example_build/tx_simulator_startup.s b/ports/cortex_m0/gnu/example_build/cortexm0_vectors.S similarity index 90% rename from ports/cortex_m4/gnu/example_build/tx_simulator_startup.s rename to ports/cortex_m0/gnu/example_build/cortexm0_vectors.S index cf0db9742..6ae558e4d 100644 --- a/ports/cortex_m4/gnu/example_build/tx_simulator_startup.s +++ b/ports/cortex_m0/gnu/example_build/cortexm0_vectors.S @@ -1,5 +1,3 @@ - - .global reset_handler .global __tx_NMIHandler @@ -10,7 +8,6 @@ .global __tx_SysTickHandler .global __tx_BadHandler - .syntax unified .section .vectors, "ax" .code 16 @@ -29,7 +26,7 @@ _vectors: .word 0 // Reserved .word 0 // Reserved .word 0 // Reserved - .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // + .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved .word __tx_PendSVHandler @@ -70,14 +67,10 @@ _vectors: .word __tx_BadHandler .word __tx_BadHandler - - - .section .init, "ax" - .thumb_func + .section .init, "ax" + .thumb_func reset_handler: - -// low level hardware config, such as PLL setup goes here - + // low level hardware config, such as PLL setup goes here b _start diff --git a/ports/cortex_m0/gnu/example_build/sample_threadx.ld b/ports/cortex_m0/gnu/example_build/sample_threadx.ld index 28f203fdf..c65a13464 100644 --- a/ports/cortex_m0/gnu/example_build/sample_threadx.ld +++ b/ports/cortex_m0/gnu/example_build/sample_threadx.ld @@ -1,206 +1,125 @@ MEMORY { - UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0 - CM3_System_Control_Space (wx) : ORIGIN = 0xe000e000, LENGTH = 0x00001000 - AHB_Peripherals (wx) : ORIGIN = 0x50000000, LENGTH = 0x00200000 - APB1_Peripherals (wx) : ORIGIN = 0x40080000, LENGTH = 0x00080000 - APB0_Peripherals (wx) : ORIGIN = 0x40000000, LENGTH = 0x00080000 - GPIO (wx) : ORIGIN = 0x2009c000, LENGTH = 0x00004000 - AHBSRAM1 (wx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 - AHBSRAM0 (wx) : ORIGIN = 0x2007c000, LENGTH = 0x00004000 - RAM (wx) : ORIGIN = 0x10000000, LENGTH = 0x00008000 - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + RAM (wx) : ORIGIN = 0x20000000, LENGTH = 0x00800000 + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00400000 } +__STACKSIZE__ = 1024; +__STACKSIZE_PROCESS__ = 0; +__HEAPSIZE__ = 128; SECTIONS { - __CM3_System_Control_Space_segment_start__ = 0xe000e000; - __CM3_System_Control_Space_segment_end__ = 0xe000f000; - __AHB_Peripherals_segment_start__ = 0x50000000; - __AHB_Peripherals_segment_end__ = 0x50200000; - __APB1_Peripherals_segment_start__ = 0x40080000; - __APB1_Peripherals_segment_end__ = 0x40100000; - __APB0_Peripherals_segment_start__ = 0x40000000; - __APB0_Peripherals_segment_end__ = 0x40080000; - __GPIO_segment_start__ = 0x2009c000; - __GPIO_segment_end__ = 0x200a0000; - __AHBSRAM1_segment_start__ = 0x20080000; - __AHBSRAM1_segment_end__ = 0x20084000; - __AHBSRAM0_segment_start__ = 0x2007c000; - __AHBSRAM0_segment_end__ = 0x20080000; - __RAM_segment_start__ = 0x10000000; - __RAM_segment_end__ = 0x10008000; - __FLASH_segment_start__ = 0x00000000; - __FLASH_segment_end__ = 0x00080000; - - __STACKSIZE__ = 1024; - __STACKSIZE_PROCESS__ = 0; - __STACKSIZE_IRQ__ = 0; - __STACKSIZE_FIQ__ = 0; - __STACKSIZE_SVC__ = 0; - __STACKSIZE_ABT__ = 0; - __STACKSIZE_UND__ = 0; - __HEAPSIZE__ = 128; - - __vectors_load_start__ = __FLASH_segment_start__; - .vectors __FLASH_segment_start__ : AT(__FLASH_segment_start__) + .vectors : { - __vectors_start__ = .; - *(.vectors .vectors.*) - } - __vectors_end__ = __vectors_start__ + SIZEOF(.vectors); - - . = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .vectors is too large to fit in FLASH memory segment"); - - __init_load_start__ = ALIGN(__vectors_end__ , 4); - .init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4)) - { - __init_start__ = .; - *(.init .init.*) - } - __init_end__ = __init_start__ + SIZEOF(.init); - - . = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .init is too large to fit in FLASH memory segment"); - - __text_load_start__ = ALIGN(__init_end__ , 4); - .text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4)) - { - __text_start__ = .; - *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table) - } - __text_end__ = __text_start__ + SIZEOF(.text); - - . = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .text is too large to fit in FLASH memory segment"); - - __dtors_load_start__ = ALIGN(__text_end__ , 4); - .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4)) - { - __dtors_start__ = .; - KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) - } - __dtors_end__ = __dtors_start__ + SIZEOF(.dtors); - - . = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .dtors is too large to fit in FLASH memory segment"); - - __ctors_load_start__ = ALIGN(__dtors_end__ , 4); - .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4)) - { - __ctors_start__ = .; - KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) - } - __ctors_end__ = __ctors_start__ + SIZEOF(.ctors); - - . = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .ctors is too large to fit in FLASH memory segment"); - - __rodata_load_start__ = ALIGN(__ctors_end__ , 4); - .rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4)) - { - __rodata_start__ = .; - *(.rodata .rodata.* .gnu.linkonce.r.*) - } - __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - - . = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .rodata is too large to fit in FLASH memory segment"); - - __fast_load_start__ = ALIGN(__rodata_end__ , 4); - .fast ALIGN(__RAM_segment_start__ , 4) : AT(ALIGN(__rodata_end__ , 4)) - { - __fast_start__ = .; - *(.fast .fast.*) - } - __fast_end__ = __fast_start__ + SIZEOF(.fast); - - __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast); - - . = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00080000) , "error: .fast is too large to fit in FLASH memory segment"); - - .fast_run ALIGN(__RAM_segment_start__ , 4) (NOLOAD) : - { - __fast_run_start__ = .; - . = MAX(__fast_run_start__ + SIZEOF(.fast), .); - } - __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run); - - . = ASSERT(__fast_run_end__ >= __RAM_segment_start__ && __fast_run_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .fast_run is too large to fit in RAM memory segment"); - - __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4); - .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4)) - { - __data_start__ = .; - *(.data .data.* .gnu.linkonce.d.*) - } - __data_end__ = __data_start__ + SIZEOF(.data); - - __data_load_end__ = __data_load_start__ + SIZEOF(.data); - - __FLASH_segment_used_end__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4) + SIZEOF(.data); - - . = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00080000) , "error: .data is too large to fit in FLASH memory segment"); - - .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) : - { - __data_run_start__ = .; - . = MAX(__data_run_start__ + SIZEOF(.data), .); - } - __data_run_end__ = __data_run_start__ + SIZEOF(.data_run); - - . = ASSERT(__data_run_end__ >= __RAM_segment_start__ && __data_run_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .data_run is too large to fit in RAM memory segment"); - - __bss_load_start__ = ALIGN(__data_run_end__ , 4); - .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4)) - { - __bss_start__ = .; - *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) - } - __bss_end__ = __bss_start__ + SIZEOF(.bss); - - . = ASSERT(__bss_end__ >= __RAM_segment_start__ && __bss_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .bss is too large to fit in RAM memory segment"); - - __non_init_load_start__ = ALIGN(__bss_end__ , 4); - .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4)) - { - __non_init_start__ = .; - *(.non_init .non_init.*) - } - __non_init_end__ = __non_init_start__ + SIZEOF(.non_init); - - . = ASSERT(__non_init_end__ >= __RAM_segment_start__ && __non_init_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .non_init is too large to fit in RAM memory segment"); - - __heap_load_start__ = ALIGN(__non_init_end__ , 4); - .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4)) - { - __heap_start__ = .; + KEEP(*(.vectors .vectors.*)) + } > FLASH + + .text : + { + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + __ctors_start__ = ALIGN(4); + *(SORT(.ctors.*)) + *(.ctors) + __ctors_end__ = ALIGN(4); + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + __dtors_start__ = ALIGN(4); + *(SORT(.dtors.*)) + *(.dtors) + __dtors_end__ = ALIGN(4); + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __data_load_start__ = ALIGN (4); + + .data : AT (__data_load_start__) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + + } > RAM + + .heap (COPY): + { + __heap_start__ = ALIGN(4); *(.heap) - . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4); - } - __heap_end__ = __heap_start__ + SIZEOF(.heap); - - . = ASSERT(__heap_end__ >= __RAM_segment_start__ && __heap_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .heap is too large to fit in RAM memory segment"); + . = ALIGN(. + __HEAPSIZE__, 4); + __heap_end__ = ALIGN(4); + } > RAM - __stack_load_start__ = ALIGN(__heap_end__ , 4); - .stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4)) + .stack ALIGN(4) (NOLOAD) : { - __stack_start__ = .; + __stack_start__ = ALIGN(4); *(.stack) - . = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4); - } - __stack_end__ = __stack_start__ + SIZEOF(.stack); - - . = ASSERT(__stack_end__ >= __RAM_segment_start__ && __stack_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .stack is too large to fit in RAM memory segment"); - - __stack_process_load_start__ = ALIGN(__stack_end__ , 4); - .stack_process ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4)) - { - __stack_process_start__ = .; - *(.stack_process) - . = ALIGN(MAX(__stack_process_start__ + __STACKSIZE_PROCESS__ , .), 4); - } - __stack_process_end__ = __stack_process_start__ + SIZEOF(.stack_process); - - __RAM_segment_used_end__ = ALIGN(__stack_end__ , 4) + SIZEOF(.stack_process); - - . = ASSERT(__stack_process_end__ >= __RAM_segment_start__ && __stack_process_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .stack_process is too large to fit in RAM memory segment"); + . = ALIGN(. + __STACKSIZE__, 4); + __stack_end__ = ALIGN(4); + } > RAM + __RAM_segment_used_end__ = .; } - diff --git a/ports/cortex_m0/iar/CMakeLists.txt b/ports/cortex_m0/iar/CMakeLists.txt new file mode 100644 index 000000000..a524d79f0 --- /dev/null +++ b/ports/cortex_m0/iar/CMakeLists.txt @@ -0,0 +1,21 @@ + +target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} + ${CMAKE_CURRENT_LIST_DIR}/src/tx_iar.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_disable.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S + # {{END_TARGET_SOURCES}} +) + +target_include_directories(${PROJECT_NAME} + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/inc +) diff --git a/ports/cortex_m0/keil/example_build/sample_threadx.uvoptx b/ports/cortex_m0/keil/example_build/sample_threadx.uvoptx deleted file mode 100644 index 6ff0dbc9e..000000000 --- a/ports/cortex_m0/keil/example_build/sample_threadx.uvoptx +++ /dev/null @@ -1,281 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - sample_threadx - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\Listings\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 7 - - 1 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 5 - - - - - - - - - - - BIN\DbgFM.DLL - - - - 0 - ARMRTXEVENTFLAGS - -L70 -Z18 -C0 -M0 -T1 - - - 0 - DLGDARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) - - - 0 - ARMDBGFLAGS - -T0 - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) - - - - - - 0 - 1 - thread_0_counter - - - 1 - 1 - thread_1_counter - - - 2 - 1 - thread_2_counter - - - 3 - 1 - thread_3_counter - - - 4 - 1 - thread_4_counter - - - 5 - 1 - thread_5_counter - - - 6 - 1 - thread_6_counter - - - 7 - 1 - thread_7_counter - - - - 0 - - - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - src - 1 - 0 - 0 - 0 - - 1 - 1 - 1 - 0 - 0 - 0 - .\sample_threadx.c - sample_threadx.c - 0 - 0 - - - 1 - 2 - 2 - 0 - 0 - 0 - .\tx_initialize_low_level.s - tx_initialize_low_level.s - 0 - 0 - - - - - lib - 1 - 0 - 0 - 0 - - 2 - 3 - 4 - 0 - 0 - 0 - .\Objects\tx.lib - tx.lib - 0 - 0 - - - - diff --git a/ports/cortex_m0/keil/example_build/sample_threadx.uvprojx b/ports/cortex_m0/keil/example_build/sample_threadx.uvprojx deleted file mode 100644 index a0e27af8e..000000000 --- a/ports/cortex_m0/keil/example_build/sample_threadx.uvprojx +++ /dev/null @@ -1,433 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - sample_threadx - 0x4 - ARM-ADS - 5060750::V5.06 update 6 (build 750)::.\ARMCC - 0 - - - ARMCM0 - ARM - ARM.CMSIS.5.7.0 - http://www.keil.com/pack/ - IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) - 0 - $$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\Objects\ - sample_threadx - 1 - 0 - 0 - 1 - 1 - .\Listings\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DARMCM1.DLL - -pCM0 - SARMCM3.DLL - - TARMCM1.DLL - -pCM0 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 0 - -1 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M0" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 1 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x0 - 0x40000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x40000 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 0 - 0 - 0 - 3 - 3 - 1 - 1 - 0 - 0 - 0 - - - - - ..\inc;..\..\..\..\common\inc - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - - - - - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 0x00000000 - 0x20000000 - - - - - --first __tx_vectors --entry=__main - - - - - - - - src - - - sample_threadx.c - 1 - .\sample_threadx.c - - - tx_initialize_low_level.s - 2 - .\tx_initialize_low_level.s - - - - - lib - - - tx.lib - 4 - .\Objects\tx.lib - - - - - - - - - - - - - - - - - <Project Info> - - - - - - 0 - 1 - - - - - diff --git a/ports/cortex_m0/keil/example_build/tx.uvoptx b/ports/cortex_m0/keil/example_build/tx.uvoptx deleted file mode 100644 index d481141d2..000000000 --- a/ports/cortex_m0/keil/example_build/tx.uvoptx +++ /dev/null @@ -1,2672 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - tx - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\Listings\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 7 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - - - - - - - - - - - BIN\UL2CM3.DLL - - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) - - - - - 0 - - - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - inc - 0 - 0 - 0 - 0 - - 1 - 1 - 5 - 0 - 0 - 0 - ..\inc\tx_port.h - tx_port.h - 0 - 0 - - - 1 - 2 - 5 - 0 - 0 - 0 - ..\..\..\..\common\inc\tx_api.h - tx_api.h - 0 - 0 - - - 1 - 3 - 5 - 0 - 0 - 0 - ..\..\..\..\common\inc\tx_block_pool.h - tx_block_pool.h - 0 - 0 - - - 1 - 4 - 5 - 0 - 0 - 0 - ..\..\..\..\common\inc\tx_byte_pool.h - tx_byte_pool.h - 0 - 0 - - - 1 - 5 - 5 - 0 - 0 - 0 - ..\..\..\..\common\inc\tx_event_flags.h - tx_event_flags.h - 0 - 0 - - - 1 - 6 - 5 - 0 - 0 - 0 - ..\..\..\..\common\inc\tx_initialize.h - tx_initialize.h - 0 - 0 - - - 1 - 7 - 5 - 0 - 0 - 0 - ..\..\..\..\common\inc\tx_mutex.h - tx_mutex.h - 0 - 0 - - - 1 - 8 - 5 - 0 - 0 - 0 - ..\..\..\..\common\inc\tx_queue.h - tx_queue.h - 0 - 0 - - - 1 - 9 - 5 - 0 - 0 - 0 - ..\..\..\..\common\inc\tx_semaphore.h - tx_semaphore.h - 0 - 0 - - - 1 - 10 - 5 - 0 - 0 - 0 - ..\..\..\..\common\inc\tx_thread.h - tx_thread.h - 0 - 0 - - - 1 - 11 - 5 - 0 - 0 - 0 - ..\..\..\..\common\inc\tx_timer.h - tx_timer.h - 0 - 0 - - - 1 - 12 - 5 - 0 - 0 - 0 - ..\..\..\..\common\inc\tx_trace.h - tx_trace.h - 0 - 0 - - - 1 - 13 - 5 - 0 - 0 - 0 - ..\..\..\..\common\inc\tx_user_sample.h - tx_user_sample.h - 0 - 0 - - - - - src - 0 - 0 - 0 - 0 - - 2 - 14 - 2 - 0 - 0 - 0 - ..\src\tx_thread_context_restore.s - tx_thread_context_restore.s - 0 - 0 - - - 2 - 15 - 2 - 0 - 0 - 0 - ..\src\tx_thread_context_save.s - tx_thread_context_save.s - 0 - 0 - - - 2 - 16 - 2 - 0 - 0 - 0 - ..\src\tx_thread_interrupt_control.s - tx_thread_interrupt_control.s - 0 - 0 - - - 2 - 17 - 2 - 0 - 0 - 0 - ..\src\tx_thread_interrupt_disable.s - tx_thread_interrupt_disable.s - 0 - 0 - - - 2 - 18 - 2 - 0 - 0 - 0 - ..\src\tx_thread_interrupt_restore.s - tx_thread_interrupt_restore.s - 0 - 0 - - - 2 - 19 - 2 - 0 - 0 - 0 - ..\src\tx_thread_schedule.s - tx_thread_schedule.s - 0 - 0 - - - 2 - 20 - 2 - 0 - 0 - 0 - ..\src\tx_thread_stack_build.s - tx_thread_stack_build.s - 0 - 0 - - - 2 - 21 - 2 - 0 - 0 - 0 - ..\src\tx_thread_system_return.s - tx_thread_system_return.s - 0 - 0 - - - 2 - 22 - 2 - 0 - 0 - 0 - ..\src\tx_timer_interrupt.s - tx_timer_interrupt.s - 0 - 0 - - - 2 - 23 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_block_allocate.c - tx_block_allocate.c - 0 - 0 - - - 2 - 24 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_block_pool_cleanup.c - tx_block_pool_cleanup.c - 0 - 0 - - - 2 - 25 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_block_pool_create.c - tx_block_pool_create.c - 0 - 0 - - - 2 - 26 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_block_pool_delete.c - tx_block_pool_delete.c - 0 - 0 - - - 2 - 27 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_block_pool_info_get.c - tx_block_pool_info_get.c - 0 - 0 - - - 2 - 28 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_block_pool_initialize.c - tx_block_pool_initialize.c - 0 - 0 - - - 2 - 29 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_block_pool_performance_info_get.c - tx_block_pool_performance_info_get.c - 0 - 0 - - - 2 - 30 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c - tx_block_pool_performance_system_info_get.c - 0 - 0 - - - 2 - 31 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_block_pool_prioritize.c - tx_block_pool_prioritize.c - 0 - 0 - - - 2 - 32 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_block_release.c - tx_block_release.c - 0 - 0 - - - 2 - 33 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_byte_allocate.c - tx_byte_allocate.c - 0 - 0 - - - 2 - 34 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_byte_pool_cleanup.c - tx_byte_pool_cleanup.c - 0 - 0 - - - 2 - 35 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_byte_pool_create.c - tx_byte_pool_create.c - 0 - 0 - - - 2 - 36 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_byte_pool_delete.c - tx_byte_pool_delete.c - 0 - 0 - - - 2 - 37 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_byte_pool_info_get.c - tx_byte_pool_info_get.c - 0 - 0 - - - 2 - 38 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_byte_pool_initialize.c - tx_byte_pool_initialize.c - 0 - 0 - - - 2 - 39 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_byte_pool_performance_info_get.c - tx_byte_pool_performance_info_get.c - 0 - 0 - - - 2 - 40 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c - tx_byte_pool_performance_system_info_get.c - 0 - 0 - - - 2 - 41 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_byte_pool_prioritize.c - tx_byte_pool_prioritize.c - 0 - 0 - - - 2 - 42 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_byte_pool_search.c - tx_byte_pool_search.c - 0 - 0 - - - 2 - 43 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_byte_release.c - tx_byte_release.c - 0 - 0 - - - 2 - 44 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_event_flags_cleanup.c - tx_event_flags_cleanup.c - 0 - 0 - - - 2 - 45 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_event_flags_create.c - tx_event_flags_create.c - 0 - 0 - - - 2 - 46 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_event_flags_delete.c - tx_event_flags_delete.c - 0 - 0 - - - 2 - 47 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_event_flags_get.c - tx_event_flags_get.c - 0 - 0 - - - 2 - 48 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_event_flags_info_get.c - tx_event_flags_info_get.c - 0 - 0 - - - 2 - 49 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_event_flags_initialize.c - tx_event_flags_initialize.c - 0 - 0 - - - 2 - 50 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_event_flags_performance_info_get.c - tx_event_flags_performance_info_get.c - 0 - 0 - - - 2 - 51 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c - tx_event_flags_performance_system_info_get.c - 0 - 0 - - - 2 - 52 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_event_flags_set.c - tx_event_flags_set.c - 0 - 0 - - - 2 - 53 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_event_flags_set_notify.c - tx_event_flags_set_notify.c - 0 - 0 - - - 2 - 54 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_initialize_high_level.c - tx_initialize_high_level.c - 0 - 0 - - - 2 - 55 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_initialize_kernel_enter.c - tx_initialize_kernel_enter.c - 0 - 0 - - - 2 - 56 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_initialize_kernel_setup.c - tx_initialize_kernel_setup.c - 0 - 0 - - - 2 - 57 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_misra.c - tx_misra.c - 0 - 0 - - - 2 - 58 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_mutex_cleanup.c - tx_mutex_cleanup.c - 0 - 0 - - - 2 - 59 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_mutex_create.c - tx_mutex_create.c - 0 - 0 - - - 2 - 60 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_mutex_delete.c - tx_mutex_delete.c - 0 - 0 - - - 2 - 61 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_mutex_get.c - tx_mutex_get.c - 0 - 0 - - - 2 - 62 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_mutex_info_get.c - tx_mutex_info_get.c - 0 - 0 - - - 2 - 63 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_mutex_initialize.c - tx_mutex_initialize.c - 0 - 0 - - - 2 - 64 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_mutex_performance_info_get.c - tx_mutex_performance_info_get.c - 0 - 0 - - - 2 - 65 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_mutex_performance_system_info_get.c - tx_mutex_performance_system_info_get.c - 0 - 0 - - - 2 - 66 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_mutex_prioritize.c - tx_mutex_prioritize.c - 0 - 0 - - - 2 - 67 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_mutex_priority_change.c - tx_mutex_priority_change.c - 0 - 0 - - - 2 - 68 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_mutex_put.c - tx_mutex_put.c - 0 - 0 - - - 2 - 69 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_queue_cleanup.c - tx_queue_cleanup.c - 0 - 0 - - - 2 - 70 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_queue_create.c - tx_queue_create.c - 0 - 0 - - - 2 - 71 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_queue_delete.c - tx_queue_delete.c - 0 - 0 - - - 2 - 72 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_queue_flush.c - tx_queue_flush.c - 0 - 0 - - - 2 - 73 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_queue_front_send.c - tx_queue_front_send.c - 0 - 0 - - - 2 - 74 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_queue_info_get.c - tx_queue_info_get.c - 0 - 0 - - - 2 - 75 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_queue_initialize.c - tx_queue_initialize.c - 0 - 0 - - - 2 - 76 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_queue_performance_info_get.c - tx_queue_performance_info_get.c - 0 - 0 - - - 2 - 77 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_queue_performance_system_info_get.c - tx_queue_performance_system_info_get.c - 0 - 0 - - - 2 - 78 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_queue_prioritize.c - tx_queue_prioritize.c - 0 - 0 - - - 2 - 79 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_queue_receive.c - tx_queue_receive.c - 0 - 0 - - - 2 - 80 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_queue_send.c - tx_queue_send.c - 0 - 0 - - - 2 - 81 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_queue_send_notify.c - tx_queue_send_notify.c - 0 - 0 - - - 2 - 82 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_semaphore_ceiling_put.c - tx_semaphore_ceiling_put.c - 0 - 0 - - - 2 - 83 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_semaphore_cleanup.c - tx_semaphore_cleanup.c - 0 - 0 - - - 2 - 84 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_semaphore_create.c - tx_semaphore_create.c - 0 - 0 - - - 2 - 85 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_semaphore_delete.c - tx_semaphore_delete.c - 0 - 0 - - - 2 - 86 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_semaphore_get.c - tx_semaphore_get.c - 0 - 0 - - - 2 - 87 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_semaphore_info_get.c - tx_semaphore_info_get.c - 0 - 0 - - - 2 - 88 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_semaphore_initialize.c - tx_semaphore_initialize.c - 0 - 0 - - - 2 - 89 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_semaphore_performance_info_get.c - tx_semaphore_performance_info_get.c - 0 - 0 - - - 2 - 90 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c - tx_semaphore_performance_system_info_get.c - 0 - 0 - - - 2 - 91 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_semaphore_prioritize.c - tx_semaphore_prioritize.c - 0 - 0 - - - 2 - 92 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_semaphore_put.c - tx_semaphore_put.c - 0 - 0 - - - 2 - 93 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_semaphore_put_notify.c - tx_semaphore_put_notify.c - 0 - 0 - - - 2 - 94 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_create.c - tx_thread_create.c - 0 - 0 - - - 2 - 95 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_delete.c - tx_thread_delete.c - 0 - 0 - - - 2 - 96 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_entry_exit_notify.c - tx_thread_entry_exit_notify.c - 0 - 0 - - - 2 - 97 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_identify.c - tx_thread_identify.c - 0 - 0 - - - 2 - 98 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_info_get.c - tx_thread_info_get.c - 0 - 0 - - - 2 - 99 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_initialize.c - tx_thread_initialize.c - 0 - 0 - - - 2 - 100 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_performance_info_get.c - tx_thread_performance_info_get.c - 0 - 0 - - - 2 - 101 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_performance_system_info_get.c - tx_thread_performance_system_info_get.c - 0 - 0 - - - 2 - 102 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_preemption_change.c - tx_thread_preemption_change.c - 0 - 0 - - - 2 - 103 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_priority_change.c - tx_thread_priority_change.c - 0 - 0 - - - 2 - 104 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_relinquish.c - tx_thread_relinquish.c - 0 - 0 - - - 2 - 105 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_reset.c - tx_thread_reset.c - 0 - 0 - - - 2 - 106 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_resume.c - tx_thread_resume.c - 0 - 0 - - - 2 - 107 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_shell_entry.c - tx_thread_shell_entry.c - 0 - 0 - - - 2 - 108 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_sleep.c - tx_thread_sleep.c - 0 - 0 - - - 2 - 109 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_stack_analyze.c - tx_thread_stack_analyze.c - 0 - 0 - - - 2 - 110 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_stack_error_handler.c - tx_thread_stack_error_handler.c - 0 - 0 - - - 2 - 111 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_stack_error_notify.c - tx_thread_stack_error_notify.c - 0 - 0 - - - 2 - 112 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_suspend.c - tx_thread_suspend.c - 0 - 0 - - - 2 - 113 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_system_preempt_check.c - tx_thread_system_preempt_check.c - 0 - 0 - - - 2 - 114 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_system_resume.c - tx_thread_system_resume.c - 0 - 0 - - - 2 - 115 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_system_suspend.c - tx_thread_system_suspend.c - 0 - 0 - - - 2 - 116 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_terminate.c - tx_thread_terminate.c - 0 - 0 - - - 2 - 117 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_time_slice.c - tx_thread_time_slice.c - 0 - 0 - - - 2 - 118 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_time_slice_change.c - tx_thread_time_slice_change.c - 0 - 0 - - - 2 - 119 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_timeout.c - tx_thread_timeout.c - 0 - 0 - - - 2 - 120 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_thread_wait_abort.c - tx_thread_wait_abort.c - 0 - 0 - - - 2 - 121 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_time_get.c - tx_time_get.c - 0 - 0 - - - 2 - 122 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_time_set.c - tx_time_set.c - 0 - 0 - - - 2 - 123 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_timer_activate.c - tx_timer_activate.c - 0 - 0 - - - 2 - 124 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_timer_change.c - tx_timer_change.c - 0 - 0 - - - 2 - 125 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_timer_create.c - tx_timer_create.c - 0 - 0 - - - 2 - 126 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_timer_deactivate.c - tx_timer_deactivate.c - 0 - 0 - - - 2 - 127 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_timer_delete.c - tx_timer_delete.c - 0 - 0 - - - 2 - 128 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_timer_expiration_process.c - tx_timer_expiration_process.c - 0 - 0 - - - 2 - 129 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_timer_info_get.c - tx_timer_info_get.c - 0 - 0 - - - 2 - 130 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_timer_initialize.c - tx_timer_initialize.c - 0 - 0 - - - 2 - 131 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_timer_performance_info_get.c - tx_timer_performance_info_get.c - 0 - 0 - - - 2 - 132 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_timer_performance_system_info_get.c - tx_timer_performance_system_info_get.c - 0 - 0 - - - 2 - 133 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_timer_system_activate.c - tx_timer_system_activate.c - 0 - 0 - - - 2 - 134 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_timer_system_deactivate.c - tx_timer_system_deactivate.c - 0 - 0 - - - 2 - 135 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_timer_thread_entry.c - tx_timer_thread_entry.c - 0 - 0 - - - 2 - 136 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_trace_buffer_full_notify.c - tx_trace_buffer_full_notify.c - 0 - 0 - - - 2 - 137 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_trace_disable.c - tx_trace_disable.c - 0 - 0 - - - 2 - 138 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_trace_enable.c - tx_trace_enable.c - 0 - 0 - - - 2 - 139 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_trace_event_filter.c - tx_trace_event_filter.c - 0 - 0 - - - 2 - 140 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_trace_event_unfilter.c - tx_trace_event_unfilter.c - 0 - 0 - - - 2 - 141 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_trace_initialize.c - tx_trace_initialize.c - 0 - 0 - - - 2 - 142 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_trace_interrupt_control.c - tx_trace_interrupt_control.c - 0 - 0 - - - 2 - 143 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_trace_isr_enter_insert.c - tx_trace_isr_enter_insert.c - 0 - 0 - - - 2 - 144 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_trace_isr_exit_insert.c - tx_trace_isr_exit_insert.c - 0 - 0 - - - 2 - 145 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_trace_object_register.c - tx_trace_object_register.c - 0 - 0 - - - 2 - 146 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_trace_object_unregister.c - tx_trace_object_unregister.c - 0 - 0 - - - 2 - 147 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\tx_trace_user_event_insert.c - tx_trace_user_event_insert.c - 0 - 0 - - - 2 - 148 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_block_allocate.c - txe_block_allocate.c - 0 - 0 - - - 2 - 149 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_block_pool_create.c - txe_block_pool_create.c - 0 - 0 - - - 2 - 150 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_block_pool_delete.c - txe_block_pool_delete.c - 0 - 0 - - - 2 - 151 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_block_pool_info_get.c - txe_block_pool_info_get.c - 0 - 0 - - - 2 - 152 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_block_pool_prioritize.c - txe_block_pool_prioritize.c - 0 - 0 - - - 2 - 153 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_block_release.c - txe_block_release.c - 0 - 0 - - - 2 - 154 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_byte_allocate.c - txe_byte_allocate.c - 0 - 0 - - - 2 - 155 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_byte_pool_create.c - txe_byte_pool_create.c - 0 - 0 - - - 2 - 156 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_byte_pool_delete.c - txe_byte_pool_delete.c - 0 - 0 - - - 2 - 157 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_byte_pool_info_get.c - txe_byte_pool_info_get.c - 0 - 0 - - - 2 - 158 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_byte_pool_prioritize.c - txe_byte_pool_prioritize.c - 0 - 0 - - - 2 - 159 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_byte_release.c - txe_byte_release.c - 0 - 0 - - - 2 - 160 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_event_flags_create.c - txe_event_flags_create.c - 0 - 0 - - - 2 - 161 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_event_flags_delete.c - txe_event_flags_delete.c - 0 - 0 - - - 2 - 162 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_event_flags_get.c - txe_event_flags_get.c - 0 - 0 - - - 2 - 163 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_event_flags_info_get.c - txe_event_flags_info_get.c - 0 - 0 - - - 2 - 164 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_event_flags_set.c - txe_event_flags_set.c - 0 - 0 - - - 2 - 165 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_event_flags_set_notify.c - txe_event_flags_set_notify.c - 0 - 0 - - - 2 - 166 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_mutex_create.c - txe_mutex_create.c - 0 - 0 - - - 2 - 167 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_mutex_delete.c - txe_mutex_delete.c - 0 - 0 - - - 2 - 168 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_mutex_get.c - txe_mutex_get.c - 0 - 0 - - - 2 - 169 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_mutex_info_get.c - txe_mutex_info_get.c - 0 - 0 - - - 2 - 170 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_mutex_prioritize.c - txe_mutex_prioritize.c - 0 - 0 - - - 2 - 171 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_mutex_put.c - txe_mutex_put.c - 0 - 0 - - - 2 - 172 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_queue_create.c - txe_queue_create.c - 0 - 0 - - - 2 - 173 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_queue_delete.c - txe_queue_delete.c - 0 - 0 - - - 2 - 174 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_queue_flush.c - txe_queue_flush.c - 0 - 0 - - - 2 - 175 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_queue_front_send.c - txe_queue_front_send.c - 0 - 0 - - - 2 - 176 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_queue_info_get.c - txe_queue_info_get.c - 0 - 0 - - - 2 - 177 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_queue_prioritize.c - txe_queue_prioritize.c - 0 - 0 - - - 2 - 178 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_queue_receive.c - txe_queue_receive.c - 0 - 0 - - - 2 - 179 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_queue_send.c - txe_queue_send.c - 0 - 0 - - - 2 - 180 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_queue_send_notify.c - txe_queue_send_notify.c - 0 - 0 - - - 2 - 181 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_semaphore_ceiling_put.c - txe_semaphore_ceiling_put.c - 0 - 0 - - - 2 - 182 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_semaphore_create.c - txe_semaphore_create.c - 0 - 0 - - - 2 - 183 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_semaphore_delete.c - txe_semaphore_delete.c - 0 - 0 - - - 2 - 184 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_semaphore_get.c - txe_semaphore_get.c - 0 - 0 - - - 2 - 185 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_semaphore_info_get.c - txe_semaphore_info_get.c - 0 - 0 - - - 2 - 186 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_semaphore_prioritize.c - txe_semaphore_prioritize.c - 0 - 0 - - - 2 - 187 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_semaphore_put.c - txe_semaphore_put.c - 0 - 0 - - - 2 - 188 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_semaphore_put_notify.c - txe_semaphore_put_notify.c - 0 - 0 - - - 2 - 189 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_thread_create.c - txe_thread_create.c - 0 - 0 - - - 2 - 190 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_thread_delete.c - txe_thread_delete.c - 0 - 0 - - - 2 - 191 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_thread_entry_exit_notify.c - txe_thread_entry_exit_notify.c - 0 - 0 - - - 2 - 192 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_thread_info_get.c - txe_thread_info_get.c - 0 - 0 - - - 2 - 193 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_thread_preemption_change.c - txe_thread_preemption_change.c - 0 - 0 - - - 2 - 194 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_thread_priority_change.c - txe_thread_priority_change.c - 0 - 0 - - - 2 - 195 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_thread_relinquish.c - txe_thread_relinquish.c - 0 - 0 - - - 2 - 196 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_thread_reset.c - txe_thread_reset.c - 0 - 0 - - - 2 - 197 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_thread_resume.c - txe_thread_resume.c - 0 - 0 - - - 2 - 198 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_thread_suspend.c - txe_thread_suspend.c - 0 - 0 - - - 2 - 199 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_thread_terminate.c - txe_thread_terminate.c - 0 - 0 - - - 2 - 200 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_thread_time_slice_change.c - txe_thread_time_slice_change.c - 0 - 0 - - - 2 - 201 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_thread_wait_abort.c - txe_thread_wait_abort.c - 0 - 0 - - - 2 - 202 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_timer_activate.c - txe_timer_activate.c - 0 - 0 - - - 2 - 203 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_timer_change.c - txe_timer_change.c - 0 - 0 - - - 2 - 204 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_timer_create.c - txe_timer_create.c - 0 - 0 - - - 2 - 205 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_timer_deactivate.c - txe_timer_deactivate.c - 0 - 0 - - - 2 - 206 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_timer_delete.c - txe_timer_delete.c - 0 - 0 - - - 2 - 207 - 1 - 0 - 0 - 0 - ..\..\..\..\common\src\txe_timer_info_get.c - txe_timer_info_get.c - 0 - 0 - - - - diff --git a/ports/cortex_m0/keil/example_build/tx.uvprojx b/ports/cortex_m0/keil/example_build/tx.uvprojx deleted file mode 100644 index bd00f4820..000000000 --- a/ports/cortex_m0/keil/example_build/tx.uvprojx +++ /dev/null @@ -1,1453 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - tx - 0x4 - ARM-ADS - 5060750::V5.06 update 6 (build 750)::.\ARMCC - 0 - - - ARMCM0 - ARM - ARM.CMSIS.5.7.0 - http://www.keil.com/pack/ - IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) - 0 - $$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\Objects\ - tx - 0 - 1 - 0 - 1 - 1 - .\Listings\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DARMCM1.DLL - -pCM0 - SARMCM3.DLL - - TARMCM1.DLL - -pCM0 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M0" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 8 - 0 - 1 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x0 - 0x40000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x40000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 0 - 0 - 0 - 3 - 3 - 1 - 1 - 0 - 0 - 0 - - - - - ..\..\..\..\common\inc;..\inc - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x20000000 - - - - - - - - - - - - - inc - - - tx_port.h - 5 - ..\inc\tx_port.h - - - tx_api.h - 5 - ..\..\..\..\common\inc\tx_api.h - - - tx_block_pool.h - 5 - ..\..\..\..\common\inc\tx_block_pool.h - - - tx_byte_pool.h - 5 - ..\..\..\..\common\inc\tx_byte_pool.h - - - tx_event_flags.h - 5 - ..\..\..\..\common\inc\tx_event_flags.h - - - tx_initialize.h - 5 - ..\..\..\..\common\inc\tx_initialize.h - - - tx_mutex.h - 5 - ..\..\..\..\common\inc\tx_mutex.h - - - tx_queue.h - 5 - ..\..\..\..\common\inc\tx_queue.h - - - tx_semaphore.h - 5 - ..\..\..\..\common\inc\tx_semaphore.h - - - tx_thread.h - 5 - ..\..\..\..\common\inc\tx_thread.h - - - tx_timer.h - 5 - ..\..\..\..\common\inc\tx_timer.h - - - tx_trace.h - 5 - ..\..\..\..\common\inc\tx_trace.h - - - tx_user_sample.h - 5 - ..\..\..\..\common\inc\tx_user_sample.h - - - - - src - - - tx_thread_context_restore.s - 2 - ..\src\tx_thread_context_restore.s - - - tx_thread_context_save.s - 2 - ..\src\tx_thread_context_save.s - - - tx_thread_interrupt_control.s - 2 - ..\src\tx_thread_interrupt_control.s - - - tx_thread_interrupt_disable.s - 2 - ..\src\tx_thread_interrupt_disable.s - - - tx_thread_interrupt_restore.s - 2 - ..\src\tx_thread_interrupt_restore.s - - - tx_thread_schedule.s - 2 - ..\src\tx_thread_schedule.s - - - tx_thread_stack_build.s - 2 - ..\src\tx_thread_stack_build.s - - - tx_thread_system_return.s - 2 - ..\src\tx_thread_system_return.s - - - tx_timer_interrupt.s - 2 - ..\src\tx_timer_interrupt.s - - - tx_block_allocate.c - 1 - ..\..\..\..\common\src\tx_block_allocate.c - - - tx_block_pool_cleanup.c - 1 - ..\..\..\..\common\src\tx_block_pool_cleanup.c - - - tx_block_pool_create.c - 1 - ..\..\..\..\common\src\tx_block_pool_create.c - - - tx_block_pool_delete.c - 1 - ..\..\..\..\common\src\tx_block_pool_delete.c - - - tx_block_pool_info_get.c - 1 - ..\..\..\..\common\src\tx_block_pool_info_get.c - - - tx_block_pool_initialize.c - 1 - ..\..\..\..\common\src\tx_block_pool_initialize.c - - - tx_block_pool_performance_info_get.c - 1 - ..\..\..\..\common\src\tx_block_pool_performance_info_get.c - - - tx_block_pool_performance_system_info_get.c - 1 - ..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c - - - tx_block_pool_prioritize.c - 1 - ..\..\..\..\common\src\tx_block_pool_prioritize.c - - - tx_block_release.c - 1 - ..\..\..\..\common\src\tx_block_release.c - - - tx_byte_allocate.c - 1 - ..\..\..\..\common\src\tx_byte_allocate.c - - - tx_byte_pool_cleanup.c - 1 - ..\..\..\..\common\src\tx_byte_pool_cleanup.c - - - tx_byte_pool_create.c - 1 - ..\..\..\..\common\src\tx_byte_pool_create.c - - - tx_byte_pool_delete.c - 1 - ..\..\..\..\common\src\tx_byte_pool_delete.c - - - tx_byte_pool_info_get.c - 1 - ..\..\..\..\common\src\tx_byte_pool_info_get.c - - - tx_byte_pool_initialize.c - 1 - ..\..\..\..\common\src\tx_byte_pool_initialize.c - - - tx_byte_pool_performance_info_get.c - 1 - ..\..\..\..\common\src\tx_byte_pool_performance_info_get.c - - - tx_byte_pool_performance_system_info_get.c - 1 - ..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c - - - tx_byte_pool_prioritize.c - 1 - ..\..\..\..\common\src\tx_byte_pool_prioritize.c - - - tx_byte_pool_search.c - 1 - ..\..\..\..\common\src\tx_byte_pool_search.c - - - tx_byte_release.c - 1 - ..\..\..\..\common\src\tx_byte_release.c - - - tx_event_flags_cleanup.c - 1 - ..\..\..\..\common\src\tx_event_flags_cleanup.c - - - tx_event_flags_create.c - 1 - ..\..\..\..\common\src\tx_event_flags_create.c - - - tx_event_flags_delete.c - 1 - ..\..\..\..\common\src\tx_event_flags_delete.c - - - tx_event_flags_get.c - 1 - ..\..\..\..\common\src\tx_event_flags_get.c - - - tx_event_flags_info_get.c - 1 - ..\..\..\..\common\src\tx_event_flags_info_get.c - - - tx_event_flags_initialize.c - 1 - ..\..\..\..\common\src\tx_event_flags_initialize.c - - - tx_event_flags_performance_info_get.c - 1 - ..\..\..\..\common\src\tx_event_flags_performance_info_get.c - - - tx_event_flags_performance_system_info_get.c - 1 - ..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c - - - tx_event_flags_set.c - 1 - ..\..\..\..\common\src\tx_event_flags_set.c - - - tx_event_flags_set_notify.c - 1 - ..\..\..\..\common\src\tx_event_flags_set_notify.c - - - tx_initialize_high_level.c - 1 - ..\..\..\..\common\src\tx_initialize_high_level.c - - - tx_initialize_kernel_enter.c - 1 - ..\..\..\..\common\src\tx_initialize_kernel_enter.c - - - tx_initialize_kernel_setup.c - 1 - ..\..\..\..\common\src\tx_initialize_kernel_setup.c - - - tx_misra.c - 1 - ..\..\..\..\common\src\tx_misra.c - - - tx_mutex_cleanup.c - 1 - ..\..\..\..\common\src\tx_mutex_cleanup.c - - - tx_mutex_create.c - 1 - ..\..\..\..\common\src\tx_mutex_create.c - - - tx_mutex_delete.c - 1 - ..\..\..\..\common\src\tx_mutex_delete.c - - - tx_mutex_get.c - 1 - ..\..\..\..\common\src\tx_mutex_get.c - - - tx_mutex_info_get.c - 1 - ..\..\..\..\common\src\tx_mutex_info_get.c - - - tx_mutex_initialize.c - 1 - ..\..\..\..\common\src\tx_mutex_initialize.c - - - tx_mutex_performance_info_get.c - 1 - ..\..\..\..\common\src\tx_mutex_performance_info_get.c - - - tx_mutex_performance_system_info_get.c - 1 - ..\..\..\..\common\src\tx_mutex_performance_system_info_get.c - - - tx_mutex_prioritize.c - 1 - ..\..\..\..\common\src\tx_mutex_prioritize.c - - - tx_mutex_priority_change.c - 1 - ..\..\..\..\common\src\tx_mutex_priority_change.c - - - tx_mutex_put.c - 1 - ..\..\..\..\common\src\tx_mutex_put.c - - - tx_queue_cleanup.c - 1 - ..\..\..\..\common\src\tx_queue_cleanup.c - - - tx_queue_create.c - 1 - ..\..\..\..\common\src\tx_queue_create.c - - - tx_queue_delete.c - 1 - ..\..\..\..\common\src\tx_queue_delete.c - - - tx_queue_flush.c - 1 - ..\..\..\..\common\src\tx_queue_flush.c - - - tx_queue_front_send.c - 1 - ..\..\..\..\common\src\tx_queue_front_send.c - - - tx_queue_info_get.c - 1 - ..\..\..\..\common\src\tx_queue_info_get.c - - - tx_queue_initialize.c - 1 - ..\..\..\..\common\src\tx_queue_initialize.c - - - tx_queue_performance_info_get.c - 1 - ..\..\..\..\common\src\tx_queue_performance_info_get.c - - - tx_queue_performance_system_info_get.c - 1 - ..\..\..\..\common\src\tx_queue_performance_system_info_get.c - - - tx_queue_prioritize.c - 1 - ..\..\..\..\common\src\tx_queue_prioritize.c - - - tx_queue_receive.c - 1 - ..\..\..\..\common\src\tx_queue_receive.c - - - tx_queue_send.c - 1 - ..\..\..\..\common\src\tx_queue_send.c - - - tx_queue_send_notify.c - 1 - ..\..\..\..\common\src\tx_queue_send_notify.c - - - tx_semaphore_ceiling_put.c - 1 - ..\..\..\..\common\src\tx_semaphore_ceiling_put.c - - - tx_semaphore_cleanup.c - 1 - ..\..\..\..\common\src\tx_semaphore_cleanup.c - - - tx_semaphore_create.c - 1 - ..\..\..\..\common\src\tx_semaphore_create.c - - - tx_semaphore_delete.c - 1 - ..\..\..\..\common\src\tx_semaphore_delete.c - - - tx_semaphore_get.c - 1 - ..\..\..\..\common\src\tx_semaphore_get.c - - - tx_semaphore_info_get.c - 1 - ..\..\..\..\common\src\tx_semaphore_info_get.c - - - tx_semaphore_initialize.c - 1 - ..\..\..\..\common\src\tx_semaphore_initialize.c - - - tx_semaphore_performance_info_get.c - 1 - ..\..\..\..\common\src\tx_semaphore_performance_info_get.c - - - tx_semaphore_performance_system_info_get.c - 1 - ..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c - - - tx_semaphore_prioritize.c - 1 - ..\..\..\..\common\src\tx_semaphore_prioritize.c - - - tx_semaphore_put.c - 1 - ..\..\..\..\common\src\tx_semaphore_put.c - - - tx_semaphore_put_notify.c - 1 - ..\..\..\..\common\src\tx_semaphore_put_notify.c - - - tx_thread_create.c - 1 - ..\..\..\..\common\src\tx_thread_create.c - - - tx_thread_delete.c - 1 - ..\..\..\..\common\src\tx_thread_delete.c - - - tx_thread_entry_exit_notify.c - 1 - ..\..\..\..\common\src\tx_thread_entry_exit_notify.c - - - tx_thread_identify.c - 1 - ..\..\..\..\common\src\tx_thread_identify.c - - - tx_thread_info_get.c - 1 - ..\..\..\..\common\src\tx_thread_info_get.c - - - tx_thread_initialize.c - 1 - ..\..\..\..\common\src\tx_thread_initialize.c - - - tx_thread_performance_info_get.c - 1 - ..\..\..\..\common\src\tx_thread_performance_info_get.c - - - tx_thread_performance_system_info_get.c - 1 - ..\..\..\..\common\src\tx_thread_performance_system_info_get.c - - - tx_thread_preemption_change.c - 1 - ..\..\..\..\common\src\tx_thread_preemption_change.c - - - tx_thread_priority_change.c - 1 - ..\..\..\..\common\src\tx_thread_priority_change.c - - - tx_thread_relinquish.c - 1 - ..\..\..\..\common\src\tx_thread_relinquish.c - - - tx_thread_reset.c - 1 - ..\..\..\..\common\src\tx_thread_reset.c - - - tx_thread_resume.c - 1 - ..\..\..\..\common\src\tx_thread_resume.c - - - tx_thread_shell_entry.c - 1 - ..\..\..\..\common\src\tx_thread_shell_entry.c - - - tx_thread_sleep.c - 1 - ..\..\..\..\common\src\tx_thread_sleep.c - - - tx_thread_stack_analyze.c - 1 - ..\..\..\..\common\src\tx_thread_stack_analyze.c - - - tx_thread_stack_error_handler.c - 1 - ..\..\..\..\common\src\tx_thread_stack_error_handler.c - - - tx_thread_stack_error_notify.c - 1 - ..\..\..\..\common\src\tx_thread_stack_error_notify.c - - - tx_thread_suspend.c - 1 - ..\..\..\..\common\src\tx_thread_suspend.c - - - tx_thread_system_preempt_check.c - 1 - ..\..\..\..\common\src\tx_thread_system_preempt_check.c - - - tx_thread_system_resume.c - 1 - ..\..\..\..\common\src\tx_thread_system_resume.c - - - tx_thread_system_suspend.c - 1 - ..\..\..\..\common\src\tx_thread_system_suspend.c - - - tx_thread_terminate.c - 1 - ..\..\..\..\common\src\tx_thread_terminate.c - - - tx_thread_time_slice.c - 1 - ..\..\..\..\common\src\tx_thread_time_slice.c - - - tx_thread_time_slice_change.c - 1 - ..\..\..\..\common\src\tx_thread_time_slice_change.c - - - tx_thread_timeout.c - 1 - ..\..\..\..\common\src\tx_thread_timeout.c - - - tx_thread_wait_abort.c - 1 - ..\..\..\..\common\src\tx_thread_wait_abort.c - - - tx_time_get.c - 1 - ..\..\..\..\common\src\tx_time_get.c - - - tx_time_set.c - 1 - ..\..\..\..\common\src\tx_time_set.c - - - tx_timer_activate.c - 1 - ..\..\..\..\common\src\tx_timer_activate.c - - - tx_timer_change.c - 1 - ..\..\..\..\common\src\tx_timer_change.c - - - tx_timer_create.c - 1 - ..\..\..\..\common\src\tx_timer_create.c - - - tx_timer_deactivate.c - 1 - ..\..\..\..\common\src\tx_timer_deactivate.c - - - tx_timer_delete.c - 1 - ..\..\..\..\common\src\tx_timer_delete.c - - - tx_timer_expiration_process.c - 1 - ..\..\..\..\common\src\tx_timer_expiration_process.c - - - tx_timer_info_get.c - 1 - ..\..\..\..\common\src\tx_timer_info_get.c - - - tx_timer_initialize.c - 1 - ..\..\..\..\common\src\tx_timer_initialize.c - - - tx_timer_performance_info_get.c - 1 - ..\..\..\..\common\src\tx_timer_performance_info_get.c - - - tx_timer_performance_system_info_get.c - 1 - ..\..\..\..\common\src\tx_timer_performance_system_info_get.c - - - tx_timer_system_activate.c - 1 - ..\..\..\..\common\src\tx_timer_system_activate.c - - - tx_timer_system_deactivate.c - 1 - ..\..\..\..\common\src\tx_timer_system_deactivate.c - - - tx_timer_thread_entry.c - 1 - ..\..\..\..\common\src\tx_timer_thread_entry.c - - - tx_trace_buffer_full_notify.c - 1 - ..\..\..\..\common\src\tx_trace_buffer_full_notify.c - - - tx_trace_disable.c - 1 - ..\..\..\..\common\src\tx_trace_disable.c - - - tx_trace_enable.c - 1 - ..\..\..\..\common\src\tx_trace_enable.c - - - tx_trace_event_filter.c - 1 - ..\..\..\..\common\src\tx_trace_event_filter.c - - - tx_trace_event_unfilter.c - 1 - ..\..\..\..\common\src\tx_trace_event_unfilter.c - - - tx_trace_initialize.c - 1 - ..\..\..\..\common\src\tx_trace_initialize.c - - - tx_trace_interrupt_control.c - 1 - ..\..\..\..\common\src\tx_trace_interrupt_control.c - - - tx_trace_isr_enter_insert.c - 1 - ..\..\..\..\common\src\tx_trace_isr_enter_insert.c - - - tx_trace_isr_exit_insert.c - 1 - ..\..\..\..\common\src\tx_trace_isr_exit_insert.c - - - tx_trace_object_register.c - 1 - ..\..\..\..\common\src\tx_trace_object_register.c - - - tx_trace_object_unregister.c - 1 - ..\..\..\..\common\src\tx_trace_object_unregister.c - - - tx_trace_user_event_insert.c - 1 - ..\..\..\..\common\src\tx_trace_user_event_insert.c - - - txe_block_allocate.c - 1 - ..\..\..\..\common\src\txe_block_allocate.c - - - txe_block_pool_create.c - 1 - ..\..\..\..\common\src\txe_block_pool_create.c - - - txe_block_pool_delete.c - 1 - ..\..\..\..\common\src\txe_block_pool_delete.c - - - txe_block_pool_info_get.c - 1 - ..\..\..\..\common\src\txe_block_pool_info_get.c - - - txe_block_pool_prioritize.c - 1 - ..\..\..\..\common\src\txe_block_pool_prioritize.c - - - txe_block_release.c - 1 - ..\..\..\..\common\src\txe_block_release.c - - - txe_byte_allocate.c - 1 - ..\..\..\..\common\src\txe_byte_allocate.c - - - txe_byte_pool_create.c - 1 - ..\..\..\..\common\src\txe_byte_pool_create.c - - - txe_byte_pool_delete.c - 1 - ..\..\..\..\common\src\txe_byte_pool_delete.c - - - txe_byte_pool_info_get.c - 1 - ..\..\..\..\common\src\txe_byte_pool_info_get.c - - - txe_byte_pool_prioritize.c - 1 - ..\..\..\..\common\src\txe_byte_pool_prioritize.c - - - txe_byte_release.c - 1 - ..\..\..\..\common\src\txe_byte_release.c - - - txe_event_flags_create.c - 1 - ..\..\..\..\common\src\txe_event_flags_create.c - - - txe_event_flags_delete.c - 1 - ..\..\..\..\common\src\txe_event_flags_delete.c - - - txe_event_flags_get.c - 1 - ..\..\..\..\common\src\txe_event_flags_get.c - - - txe_event_flags_info_get.c - 1 - ..\..\..\..\common\src\txe_event_flags_info_get.c - - - txe_event_flags_set.c - 1 - ..\..\..\..\common\src\txe_event_flags_set.c - - - txe_event_flags_set_notify.c - 1 - ..\..\..\..\common\src\txe_event_flags_set_notify.c - - - txe_mutex_create.c - 1 - ..\..\..\..\common\src\txe_mutex_create.c - - - txe_mutex_delete.c - 1 - ..\..\..\..\common\src\txe_mutex_delete.c - - - txe_mutex_get.c - 1 - ..\..\..\..\common\src\txe_mutex_get.c - - - txe_mutex_info_get.c - 1 - ..\..\..\..\common\src\txe_mutex_info_get.c - - - txe_mutex_prioritize.c - 1 - ..\..\..\..\common\src\txe_mutex_prioritize.c - - - txe_mutex_put.c - 1 - ..\..\..\..\common\src\txe_mutex_put.c - - - txe_queue_create.c - 1 - ..\..\..\..\common\src\txe_queue_create.c - - - txe_queue_delete.c - 1 - ..\..\..\..\common\src\txe_queue_delete.c - - - txe_queue_flush.c - 1 - ..\..\..\..\common\src\txe_queue_flush.c - - - txe_queue_front_send.c - 1 - ..\..\..\..\common\src\txe_queue_front_send.c - - - txe_queue_info_get.c - 1 - ..\..\..\..\common\src\txe_queue_info_get.c - - - txe_queue_prioritize.c - 1 - ..\..\..\..\common\src\txe_queue_prioritize.c - - - txe_queue_receive.c - 1 - ..\..\..\..\common\src\txe_queue_receive.c - - - txe_queue_send.c - 1 - ..\..\..\..\common\src\txe_queue_send.c - - - txe_queue_send_notify.c - 1 - ..\..\..\..\common\src\txe_queue_send_notify.c - - - txe_semaphore_ceiling_put.c - 1 - ..\..\..\..\common\src\txe_semaphore_ceiling_put.c - - - txe_semaphore_create.c - 1 - ..\..\..\..\common\src\txe_semaphore_create.c - - - txe_semaphore_delete.c - 1 - ..\..\..\..\common\src\txe_semaphore_delete.c - - - txe_semaphore_get.c - 1 - ..\..\..\..\common\src\txe_semaphore_get.c - - - txe_semaphore_info_get.c - 1 - ..\..\..\..\common\src\txe_semaphore_info_get.c - - - txe_semaphore_prioritize.c - 1 - ..\..\..\..\common\src\txe_semaphore_prioritize.c - - - txe_semaphore_put.c - 1 - ..\..\..\..\common\src\txe_semaphore_put.c - - - txe_semaphore_put_notify.c - 1 - ..\..\..\..\common\src\txe_semaphore_put_notify.c - - - txe_thread_create.c - 1 - ..\..\..\..\common\src\txe_thread_create.c - - - txe_thread_delete.c - 1 - ..\..\..\..\common\src\txe_thread_delete.c - - - txe_thread_entry_exit_notify.c - 1 - ..\..\..\..\common\src\txe_thread_entry_exit_notify.c - - - txe_thread_info_get.c - 1 - ..\..\..\..\common\src\txe_thread_info_get.c - - - txe_thread_preemption_change.c - 1 - ..\..\..\..\common\src\txe_thread_preemption_change.c - - - txe_thread_priority_change.c - 1 - ..\..\..\..\common\src\txe_thread_priority_change.c - - - txe_thread_relinquish.c - 1 - ..\..\..\..\common\src\txe_thread_relinquish.c - - - txe_thread_reset.c - 1 - ..\..\..\..\common\src\txe_thread_reset.c - - - txe_thread_resume.c - 1 - ..\..\..\..\common\src\txe_thread_resume.c - - - txe_thread_suspend.c - 1 - ..\..\..\..\common\src\txe_thread_suspend.c - - - txe_thread_terminate.c - 1 - ..\..\..\..\common\src\txe_thread_terminate.c - - - txe_thread_time_slice_change.c - 1 - ..\..\..\..\common\src\txe_thread_time_slice_change.c - - - txe_thread_wait_abort.c - 1 - ..\..\..\..\common\src\txe_thread_wait_abort.c - - - txe_timer_activate.c - 1 - ..\..\..\..\common\src\txe_timer_activate.c - - - txe_timer_change.c - 1 - ..\..\..\..\common\src\txe_timer_change.c - - - txe_timer_create.c - 1 - ..\..\..\..\common\src\txe_timer_create.c - - - txe_timer_deactivate.c - 1 - ..\..\..\..\common\src\txe_timer_deactivate.c - - - txe_timer_delete.c - 1 - ..\..\..\..\common\src\txe_timer_delete.c - - - txe_timer_info_get.c - 1 - ..\..\..\..\common\src\txe_timer_info_get.c - - - - - - - - - - - - - - - - - <Project Info> - - - - - - 0 - 1 - - - - - diff --git a/ports/cortex_m23/ac6/inc/tx_port.h b/ports/cortex_m23/ac6/inc/tx_port.h index ccde44e9f..5de6c143b 100644 --- a/ports/cortex_m23/ac6/inc/tx_port.h +++ b/ports/cortex_m23/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M23/AC6 */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -62,6 +62,10 @@ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -342,7 +346,7 @@ ULONG _tx_misra_ipsr_get(VOID); #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) /* Initialize secure stacks for threads calling secure functions. */ extern void _tx_thread_secure_stack_initialize(void); -#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to @@ -411,7 +415,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/AC6 Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/AC6 Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m23/ac6/src/tx_misra.S b/ports/cortex_m23/ac6/src/tx_misra.S new file mode 100644 index 000000000..4393fc6ff --- /dev/null +++ b/ports/cortex_m23/ac6/src/tx_misra.S @@ -0,0 +1,724 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ThreadX MISRA Compliance */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + #define SHT_PROGBITS 0x1 + + .global __aeabi_memset + .global _tx_thread_current_ptr + .global _tx_thread_interrupt_disable + .global _tx_thread_interrupt_restore + .global _tx_thread_stack_analyze + .global _tx_thread_stack_error_handler + .global _tx_thread_system_state +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_trace_buffer_current_ptr + .global _tx_trace_buffer_end_ptr + .global _tx_trace_buffer_start_ptr + .global _tx_trace_event_enable_bits + .global _tx_trace_full_notify_function + .global _tx_trace_header_ptr +#endif + + .global _tx_misra_always_true + .global _tx_misra_block_pool_to_uchar_pointer_convert + .global _tx_misra_byte_pool_to_uchar_pointer_convert + .global _tx_misra_char_to_uchar_pointer_convert + .global _tx_misra_const_char_to_char_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_entry_to_uchar_pointer_convert +#endif + .global _tx_misra_indirect_void_to_uchar_pointer_convert + .global _tx_misra_memset + .global _tx_misra_message_copy +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_object_to_uchar_pointer_convert +#endif + .global _tx_misra_pointer_to_ulong_convert + .global _tx_misra_status_get + .global _tx_misra_thread_stack_check +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_time_stamp_get +#endif + .global _tx_misra_timer_indirect_to_void_pointer_convert + .global _tx_misra_timer_pointer_add + .global _tx_misra_timer_pointer_dif +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_trace_event_insert +#endif + .global _tx_misra_uchar_pointer_add + .global _tx_misra_uchar_pointer_dif + .global _tx_misra_uchar_pointer_sub + .global _tx_misra_uchar_to_align_type_pointer_convert + .global _tx_misra_uchar_to_block_pool_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_uchar_to_entry_pointer_convert + .global _tx_misra_uchar_to_header_pointer_convert +#endif + .global _tx_misra_uchar_to_indirect_byte_pool_pointer_convert + .global _tx_misra_uchar_to_indirect_uchar_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_uchar_to_object_pointer_convert +#endif + .global _tx_misra_uchar_to_void_pointer_convert + .global _tx_misra_ulong_pointer_add + .global _tx_misra_ulong_pointer_dif + .global _tx_misra_ulong_pointer_sub + .global _tx_misra_ulong_to_pointer_convert + .global _tx_misra_ulong_to_thread_pointer_convert + .global _tx_misra_user_timer_pointer_get + .global _tx_misra_void_to_block_pool_pointer_convert + .global _tx_misra_void_to_byte_pool_pointer_convert + .global _tx_misra_void_to_event_flags_pointer_convert + .global _tx_misra_void_to_indirect_uchar_pointer_convert + .global _tx_misra_void_to_mutex_pointer_convert + .global _tx_misra_void_to_queue_pointer_convert + .global _tx_misra_void_to_semaphore_pointer_convert + .global _tx_misra_void_to_thread_pointer_convert + .global _tx_misra_void_to_uchar_pointer_convert + .global _tx_misra_void_to_ulong_pointer_convert + .global _tx_misra_ipsr_get + .global _tx_misra_control_get + .global _tx_misra_control_set +#ifdef __ARM_FP + .global _tx_misra_fpccr_get + .global _tx_misra_vfp_touch +#endif + + .global _tx_misra_event_flags_group_not_used + .global _tx_misra_event_flags_set_notify_not_used + .global _tx_misra_queue_not_used + .global _tx_misra_queue_send_notify_not_used + .global _tx_misra_semaphore_not_used + .global _tx_misra_semaphore_put_notify_not_used + .global _tx_misra_thread_entry_exit_notify_not_used + .global _tx_misra_thread_not_used + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_memset(VOID *ptr, UINT value, UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .align 4 + .syntax unified + .thumb_func +_tx_misra_memset: + PUSH {R4,LR} + MOVS R4,R0 + MOVS R0,R2 + MOVS R2,R1 + MOVS R1,R0 + MOVS R0,R4 + BL __aeabi_memset + POP {R4,PC} // return + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_add(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_uchar_pointer_add: + ADD R0,R0,R1 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_sub(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_uchar_pointer_sub: + RSBS R1,R1,#+0 + ADD R0,R0,R1 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_uchar_pointer_dif(UCHAR *ptr1, UCHAR *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_uchar_pointer_dif: + SUBS R0,R0,R1 + BX LR // return + + +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ +/** */ +/** This single function serves all of the below prototypes. */ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** VOID _tx_misra_event_flags_group_not_used(TX_EVENT_FLAGS_GROUP *group_ptr); */ +/** VOID _tx_misra_event_flags_set_notify_not_used(VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); */ +/** VOID _tx_misra_queue_not_used(TX_QUEUE *queue_ptr); */ +/** VOID _tx_misra_queue_send_notify_not_used(VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); */ +/** VOID _tx_misra_semaphore_not_used(TX_SEMAPHORE *semaphore_ptr); */ +/** VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); */ +/** VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr); */ +/** VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)); */ +/** */ +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ + .text + .thumb_func +_tx_misra_pointer_to_ulong_convert: +_tx_misra_ulong_to_pointer_convert: +_tx_misra_indirect_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_indirect_uchar_pointer_convert: +_tx_misra_block_pool_to_uchar_pointer_convert: +_tx_misra_void_to_block_pool_pointer_convert: +_tx_misra_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_block_pool_pointer_convert: +_tx_misra_void_to_indirect_uchar_pointer_convert: +_tx_misra_void_to_byte_pool_pointer_convert: +_tx_misra_byte_pool_to_uchar_pointer_convert: +_tx_misra_uchar_to_align_type_pointer_convert: +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: +_tx_misra_void_to_event_flags_pointer_convert: +_tx_misra_void_to_ulong_pointer_convert: +_tx_misra_void_to_mutex_pointer_convert: +_tx_misra_void_to_queue_pointer_convert: +_tx_misra_void_to_semaphore_pointer_convert: +_tx_misra_uchar_to_void_pointer_convert: +_tx_misra_ulong_to_thread_pointer_convert: +_tx_misra_timer_indirect_to_void_pointer_convert: +_tx_misra_const_char_to_char_pointer_convert: +_tx_misra_void_to_thread_pointer_convert: +#ifdef TX_ENABLE_EVENT_TRACE +_tx_misra_object_to_uchar_pointer_convert: +_tx_misra_uchar_to_object_pointer_convert: +_tx_misra_uchar_to_header_pointer_convert: +_tx_misra_uchar_to_entry_pointer_convert: +_tx_misra_entry_to_uchar_pointer_convert: +#endif +_tx_misra_char_to_uchar_pointer_convert: +_tx_misra_event_flags_group_not_used: +_tx_misra_event_flags_set_notify_not_used: +_tx_misra_queue_not_used: +_tx_misra_queue_send_notify_not_used: +_tx_misra_semaphore_not_used: +_tx_misra_semaphore_put_notify_not_used: +_tx_misra_thread_entry_exit_notify_not_used: +_tx_misra_thread_not_used: + + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_add(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_ulong_pointer_add: + LSLS R1,#2 + ADD R0,R0,R1 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_sub(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_ulong_pointer_sub: + MOVS R3,#3 + MVNS R2,R3 + MULS R1,R2,R1 + ADD R0,R0,R1 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_ulong_pointer_dif(ULONG *ptr1, ULONG *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_ulong_pointer_dif: + SUBS R0,R0,R1 + ASRS R0,R0,#+2 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_message_copy(ULONG **source, ULONG **destination, */ +/** UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_message_copy: + PUSH {R4,R5} + LDR R3,[R0, #+0] + LDR R4,[R1, #+0] + LDR R5,[R3, #+0] + STR R5,[R4, #+0] + ADDS R4,R4,#+4 + ADDS R3,R3,#+4 + CMP R2,#+2 + BCC.N _tx_misra_message_copy_0 + SUBS R2,R2,#+1 + B.N _tx_misra_message_copy_1 +_tx_misra_message_copy_2: + LDR R5,[R3, #+0] + STR R5,[R4, #+0] + ADDS R4,R4,#+4 + ADDS R3,R3,#+4 + SUBS R2,R2,#+1 +_tx_misra_message_copy_1: + CMP R2,#+0 + BNE.N _tx_misra_message_copy_2 +_tx_misra_message_copy_0: + STR R3,[R0, #+0] + STR R4,[R1, #+0] + POP {R4,R5} + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_timer_pointer_dif(TX_TIMER_INTERNAL **ptr1, */ +/** TX_TIMER_INTERNAL **ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_timer_pointer_dif: + SUBS R0,R0,R1 + ASRS R0,R0,#+2 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** TX_TIMER_INTERNAL **_tx_misra_timer_pointer_add(TX_TIMER_INTERNAL */ +/** **ptr1, ULONG size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_timer_pointer_add: + LSLS R1,#2 + ADD R0,R0,R1 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL */ +/** *internal_timer, TX_TIMER **user_timer); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_user_timer_pointer_get: + SUBS R0,#8 + STR R0,[R1, #+0] + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, */ +/** VOID **highest_stack); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_thread_stack_check: + PUSH {R3-R7,LR} + MOVS R4,R0 + MOVS R5,R1 + BL _tx_thread_interrupt_disable + CMP R4,#0 + BEQ.N _tx_misra_thread_stack_check_0 + LDR R1,[R4] + LDR R2,=0x54485244 + CMP R1,R2 + BNE.N _tx_misra_thread_stack_check_0 + LDR R1,[R4, #8] + LDR R2,[R5] + CMP R1,R2 + BCS.N _tx_misra_thread_stack_check_1 + STR R1,[R5] +_tx_misra_thread_stack_check_1: + LDR R1,[R4, #12] + LDR R1,[R1] + LDR R6,=0xEFEFEFEF + CMP R1,R6 + BNE.N _tx_misra_thread_stack_check_2 + LDR R1,[R4, #16] + MOVS R7,#1 + LDR R1,[R1, R7] + CMP R1,R6 + BNE.N _tx_misra_thread_stack_check_2 + LDR R1,[R5] + LDR R2,[R4, #12] + CMP R1,R2 + BCS.N _tx_misra_thread_stack_check_3 +_tx_misra_thread_stack_check_2: + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_error_handler + BL _tx_thread_interrupt_disable +_tx_misra_thread_stack_check_3: + LDR R1,[R5] + LDR R7,=-4 + LDR R1,[R1, R7] + CMP R1,R6 + BEQ.N _tx_misra_thread_stack_check_0 + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_analyze + BL _tx_thread_interrupt_disable +_tx_misra_thread_stack_check_0: + BL _tx_thread_interrupt_restore + POP {R0,R4,R5,R6,R7,PC} // return + +#ifdef TX_ENABLE_EVENT_TRACE + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_trace_event_insert(ULONG event_id, */ +/** VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, */ +/** ULONG info_field_4, ULONG filter, ULONG time_stamp); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_trace_event_insert: + PUSH {R3-R7,LR} + LDR.N R4,DataTable2_1 + LDR R4,[R4, #+0] + CMP R4,#+0 + BEQ.N _tx_misra_trace_event_insert_0 + LDR.N R5,DataTable2_2 + LDR R5,[R5, #+0] + LDR R6,[SP, #+28] + TST R5,R6 + BEQ.N _tx_misra_trace_event_insert_0 + LDR.N R5,DataTable2_3 + LDR R5,[R5, #+0] + LDR.N R6,DataTable2_4 + LDR R6,[R6, #+0] + CMP R5,#+0 + BNE.N _tx_misra_trace_event_insert_1 + LDR R5,[R6, #+44] + LDR R7,[R6, #+60] + LSLS R7,R7,#+16 + ORRS R7,R7,#0x80000000 + ORRS R5,R7,R5 + B.N _tx_misra_trace_event_insert_2 +_tx_misra_trace_event_insert_1: + CMP R5,#-252645136 + BCS.N _tx_misra_trace_event_insert_3 + MOVS R5,R6 + MOVS R6,#-1 + B.N _tx_misra_trace_event_insert_2 +_tx_misra_trace_event_insert_3: + MOVS R6,#-252645136 + MOVS R5,#+0 +_tx_misra_trace_event_insert_2: + STR R6,[R4, #+0] + STR R5,[R4, #+4] + STR R0,[R4, #+8] + LDR R0,[SP, #+32] + STR R0,[R4, #+12] + STR R1,[R4, #+16] + STR R2,[R4, #+20] + STR R3,[R4, #+24] + LDR R0,[SP, #+24] + STR R0,[R4, #+28] + ADDS R4,R4,#+32 + LDR.N R0,DataTable2_5 + LDR R0,[R0, #+0] + CMP R4,R0 + BCC.N _tx_misra_trace_event_insert_4 + LDR.N R0,DataTable2_6 + LDR R4,[R0, #+0] + LDR.N R0,DataTable2_1 + STR R4,[R0, #+0] + LDR.N R0,DataTable2_7 + LDR R0,[R0, #+0] + STR R4,[R0, #+32] + LDR.N R0,DataTable2_8 + LDR R0,[R0, #+0] + CMP R0,#+0 + BEQ.N _tx_misra_trace_event_insert_0 + LDR.N R0,DataTable2_7 + LDR R0,[R0, #+0] + LDR.N R1,DataTable2_8 + LDR R1,[R1, #+0] + BLX R1 + B.N _tx_misra_trace_event_insert_0 +_tx_misra_trace_event_insert_4: + LDR.N R0,DataTable2_1 + STR R4,[R0, #+0] + LDR.N R0,DataTable2_7 + LDR R0,[R0, #+0] + STR R4,[R0, #+32] +_tx_misra_trace_event_insert_0: + POP {R0,R4-R7,PC} // return + + + .data +DataTable2_1: + .word _tx_trace_buffer_current_ptr + + .data +DataTable2_2: + .word _tx_trace_event_enable_bits + + .data +DataTable2_5: + .word _tx_trace_buffer_end_ptr + + .data +DataTable2_6: + .word _tx_trace_buffer_start_ptr + + .data +DataTable2_7: + .word _tx_trace_header_ptr + + .data +DataTable2_8: + .word _tx_trace_full_notify_function + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_time_stamp_get(VOID); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_time_stamp_get: + MOVS R0,#+0 + BX LR // return + +#endif + + .data +DataTable2_3: + .word _tx_thread_system_state + + .data +DataTable2_4: + .word _tx_thread_current_ptr + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_always_true(void); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_always_true: + MOVS R0,#+1 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_status_get(UINT status); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_status_get: + MOVS R0,#+0 + BX LR // return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_ipsr_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + .text + .thumb_func +_tx_misra_ipsr_get: + MRS R0, IPSR + BX LR // return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_control_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + .text + .thumb_func +_tx_misra_control_get: + MRS R0, CONTROL + BX LR // return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** void _tx_misra_control_set(ULONG value); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + .text + .thumb_func +_tx_misra_control_set: + MSR CONTROL, R0 + BX LR // return + + +#ifdef __ARM_FP + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_fpccr_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + .text + .thumb_func +_tx_misra_fpccr_get: + LDR r0, =0xE000EF34 // Build FPCCR address + LDR r0, [r0] // Load FPCCR value + BX LR // return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** void _tx_misra_vfp_touch(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + .text + .thumb_func +_tx_misra_vfp_touch: + vmov.f32 s0, s0 + BX LR // return + +#endif + + + .data + .word 0 diff --git a/ports/cortex_m23/ac6/src/tx_thread_secure_stack.c b/ports/cortex_m23/ac6/src/tx_thread_secure_stack.c index 7892402b3..f10967625 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_secure_stack.c +++ b/ports/cortex_m23/ac6/src/tx_thread_secure_stack.c @@ -23,7 +23,7 @@ #include "tx_api.h" -/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, +/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, no secure stack functionality is needed. */ #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) @@ -45,8 +45,14 @@ #define TX_THREAD_STACK_SEAL_SIZE 8 #define TX_THREAD_STACK_SEAL_VALUE 0xFEF5EDA5 -/* Secure stack info struct to hold stack start, stack limit, - current stack pointer, and pointer to owning thread. +/* max number of Secure context */ +#ifndef TX_MAX_SECURE_CONTEXTS +#define TX_MAX_SECURE_CONTEXTS 32 +#endif +#define TX_INVALID_SECURE_CONTEXT_IDX (-1) + +/* Secure stack info struct to hold stack start, stack limit, + current stack pointer, and pointer to owning thread. This will be allocated for each thread with a secure stack. */ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT { @@ -54,8 +60,14 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */ VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */ TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */ + INT tx_next_free_index; /* Next free index of free secure context */ } TX_THREAD_SECURE_STACK_INFO; +/* Static secure contexts */ +static TX_THREAD_SECURE_STACK_INFO tx_thread_secure_context[TX_MAX_SECURE_CONTEXTS]; +/* Head of free secure context */ +static INT tx_head_free_index = 0U; + /**************************************************************************/ @@ -63,7 +75,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_initialize Cortex-M23/AC6 */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -102,12 +114,16 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* changed name, execute in */ /* handler mode, */ /* resulting in version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) { UINT status; +INT index; /* Make sure function is called from interrupt (threads should not call). */ if (__get_IPSR() == 0) @@ -118,12 +134,26 @@ UINT status; { /* Set secure mode to use PSP. */ __set_CONTROL(__get_CONTROL() | 2); - + /* Set process stack pointer and stack limit to 0 to throw exception when a thread without a secure stack calls a secure function that tries to use secure stack. */ __set_PSPLIM(0); __set_PSP(0); - + + for (index = 0; index < TX_MAX_SECURE_CONTEXTS; index++) + { + + /* Check last index and mark next free to invalid index */ + if(index == (TX_MAX_SECURE_CONTEXTS - 1)) + { + tx_thread_secure_context[index].tx_next_free_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + else + { + tx_thread_secure_context[index].tx_next_free_index = index + 1; + } + } + status = TX_SUCCESS; } return status; @@ -136,7 +166,7 @@ UINT status; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_allocate Cortex-M23/AC6 */ -/* 6.1.1 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -160,9 +190,7 @@ UINT status; /* CALLS */ /* */ /* __get_IPSR Intrinsic to get IPSR */ -/* calloc Compiler's calloc function */ /* malloc Compiler's malloc function */ -/* free Compiler's free() function */ /* __set_PSPLIM Intrinsic to set PSP limit */ /* __set_PSP Intrinsic to set PSP */ /* __TZ_get_PSPLIM_NS Intrinsic to get NS PSP */ @@ -179,18 +207,22 @@ UINT status; /* 10-16-2020 Scott Larson Modified comment(s), */ /* added stack sealing, */ /* resulting in version 6.1.1 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; UCHAR *stack_mem; -ULONG sp; +INT secure_context_index; status = TX_SUCCESS; - + /* Make sure function is called from interrupt (threads should not call). */ if (__get_IPSR() == 0) { @@ -200,23 +232,38 @@ ULONG sp; { status = TX_SIZE_ERROR; } - + /* Check if thread already has secure stack allocated. */ else if (thread_ptr -> tx_thread_secure_stack_context != 0) { status = TX_THREAD_ERROR; } - + else { - /* Allocate space for secure stack info. */ - info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO)); - - if(info_ptr != TX_NULL) + TX_DISABLE + + /* Allocate free index for secure stack info. */ + if(tx_head_free_index != TX_INVALID_SECURE_CONTEXT_IDX) + { + secure_context_index = tx_head_free_index; + tx_head_free_index = tx_thread_secure_context[tx_head_free_index].tx_next_free_index; + tx_thread_secure_context[secure_context_index].tx_next_free_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + else + { + secure_context_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + + TX_RESTORE + + if(secure_context_index != TX_INVALID_SECURE_CONTEXT_IDX) { + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* If stack info allocated, allocate a stack & seal. */ stack_mem = malloc(stack_size + TX_THREAD_STACK_SEAL_SIZE); - + if(stack_mem != TX_NULL) { /* Secure stack has been allocated, save in the stack info struct. */ @@ -224,38 +271,41 @@ ULONG sp; info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size; info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start; info_ptr -> tx_thread_ptr = thread_ptr; - + /* Seal bottom of stack. */ *(ULONG*)info_ptr -> tx_thread_secure_stack_start = TX_THREAD_STACK_SEAL_VALUE; - - /* Save info pointer in thread. */ - thread_ptr -> tx_thread_secure_stack_context = info_ptr; - - /* Check if this thread is running by looking at PSP_NS and seeing if it is within - the stack_start and stack_end range. */ - sp = __TZ_get_PSP_NS(); - if(sp > ((ULONG) thread_ptr -> tx_thread_stack_start) && sp < ((ULONG) thread_ptr -> tx_thread_stack_end)) + + /* Save secure context id (i.e non-zero base index) in thread. */ + thread_ptr -> tx_thread_secure_stack_context = (VOID *)(secure_context_index + 1); + + /* Check if this thread is running by looking at its stack start and PSPLIM_NS */ + if(((ULONG) thread_ptr -> tx_thread_stack_start & 0xFFFFFFF8) == __TZ_get_PSPLIM_NS()) { /* If this thread is running, set Secure PSP and PSPLIM. */ __set_PSPLIM((ULONG)(info_ptr -> tx_thread_secure_stack_limit)); __set_PSP((ULONG)(info_ptr -> tx_thread_secure_stack_ptr)); } } - + else { + TX_DISABLE + /* Stack not allocated, free the info struct. */ - free(info_ptr); + tx_thread_secure_context[secure_context_index].tx_next_free_index = tx_head_free_index; + tx_head_free_index = secure_context_index; + TX_RESTORE + status = TX_NO_MEMORY; } } - + else { status = TX_NO_MEMORY; } } - + return(status); } @@ -266,7 +316,7 @@ ULONG sp; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_free Cortex-M23/AC6 */ -/* 6.1.1 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -301,44 +351,65 @@ ULONG sp; /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; +INT secure_context_index; status = TX_SUCCESS; - - /* Pickup stack info from thread. */ - info_ptr = thread_ptr -> tx_thread_secure_stack_context; - + + /* Pickup stack info id from thread. */ + secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; + /* Make sure function is called from interrupt (threads should not call). */ if (__get_IPSR() == 0) { status = TX_CALLER_ERROR; } - - /* Check that this secure context is for this thread. */ - else if (info_ptr -> tx_thread_ptr != thread_ptr) + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) { status = TX_THREAD_ERROR; } - else { - - /* Free secure stack. */ - free(info_ptr -> tx_thread_secure_stack_limit); - - /* Free info struct. */ - free(info_ptr); - - /* Clear secure context from thread. */ - thread_ptr -> tx_thread_secure_stack_context = 0; + + /* Pickup stack info from static array of secure contexts. */ + info_ptr = &tx_thread_secure_context[secure_context_index]; + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Free secure stack. */ + free(info_ptr -> tx_thread_secure_stack_limit); + + TX_DISABLE + + /* Free info struct. */ + tx_thread_secure_context[secure_context_index].tx_next_free_index = tx_head_free_index; + tx_head_free_index = secure_context_index; + TX_RESTORE + + /* Clear secure context from thread. */ + thread_ptr -> tx_thread_secure_stack_context = 0; + } } - + return(status); } @@ -349,7 +420,7 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_save Cortex-M23/AC6 */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -386,6 +457,9 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr; /* resulting in version 6.1.1 */ /* 06-02-2021 Scott Larson Fix stack pointer save, */ /* resulting in version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) @@ -393,38 +467,45 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; +INT secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { return; } - + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) + { + return; + } + /* Pickup the secure context pointer. */ - info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); - + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* Check that this secure context is for this thread. */ if (info_ptr -> tx_thread_ptr != thread_ptr) { return; } - + /* Check that stack pointer is in range */ sp = __get_PSP(); - if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || + if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start)) { return; } - + /* Save stack pointer. */ info_ptr -> tx_thread_secure_stack_ptr = (VOID *) sp; - + /* Set process stack pointer and stack limit to 0 to throw exception when a thread without a secure stack calls a secure function that tries to use secure stack. */ __set_PSPLIM(0); __set_PSP(0); - + return; } @@ -435,7 +516,7 @@ ULONG sp; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_restore Cortex-M23/AC6 */ -/* 6.1.1 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -469,32 +550,42 @@ ULONG sp; /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; +INT secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { return; } - + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) + { + return; + } + /* Pickup the secure context pointer. */ - info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); - + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* Check that this secure context is for this thread. */ if (info_ptr -> tx_thread_ptr != thread_ptr) { return; } - + /* Set stack pointer and limit. */ __set_PSPLIM((ULONG)info_ptr -> tx_thread_secure_stack_limit); __set_PSP ((ULONG)info_ptr -> tx_thread_secure_stack_ptr); - + return; } diff --git a/ports/cortex_m23/ac6/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_initialize.S index 06dc88122..bada32cee 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_initialize.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M23/AC6 */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -49,13 +49,17 @@ /* */ /* CALLED BY */ /* */ -/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */ +/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ /* RELEASE HISTORY */ /* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports/cortex_m23/gnu/inc/tx_port.h b/ports/cortex_m23/gnu/inc/tx_port.h index db5935cb8..5cf9896bc 100644 --- a/ports/cortex_m23/gnu/inc/tx_port.h +++ b/ports/cortex_m23/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M23/GNU */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -63,6 +63,10 @@ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -341,7 +345,7 @@ ULONG _tx_misra_ipsr_get(VOID); #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) /* Initialize secure stacks for threads calling secure functions. */ extern void _tx_thread_secure_stack_initialize(void); -#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to @@ -443,7 +447,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/GNU Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/GNU Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m23/gnu/src/tx_misra.S b/ports/cortex_m23/gnu/src/tx_misra.S new file mode 100644 index 000000000..4393fc6ff --- /dev/null +++ b/ports/cortex_m23/gnu/src/tx_misra.S @@ -0,0 +1,724 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ThreadX MISRA Compliance */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + #define SHT_PROGBITS 0x1 + + .global __aeabi_memset + .global _tx_thread_current_ptr + .global _tx_thread_interrupt_disable + .global _tx_thread_interrupt_restore + .global _tx_thread_stack_analyze + .global _tx_thread_stack_error_handler + .global _tx_thread_system_state +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_trace_buffer_current_ptr + .global _tx_trace_buffer_end_ptr + .global _tx_trace_buffer_start_ptr + .global _tx_trace_event_enable_bits + .global _tx_trace_full_notify_function + .global _tx_trace_header_ptr +#endif + + .global _tx_misra_always_true + .global _tx_misra_block_pool_to_uchar_pointer_convert + .global _tx_misra_byte_pool_to_uchar_pointer_convert + .global _tx_misra_char_to_uchar_pointer_convert + .global _tx_misra_const_char_to_char_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_entry_to_uchar_pointer_convert +#endif + .global _tx_misra_indirect_void_to_uchar_pointer_convert + .global _tx_misra_memset + .global _tx_misra_message_copy +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_object_to_uchar_pointer_convert +#endif + .global _tx_misra_pointer_to_ulong_convert + .global _tx_misra_status_get + .global _tx_misra_thread_stack_check +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_time_stamp_get +#endif + .global _tx_misra_timer_indirect_to_void_pointer_convert + .global _tx_misra_timer_pointer_add + .global _tx_misra_timer_pointer_dif +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_trace_event_insert +#endif + .global _tx_misra_uchar_pointer_add + .global _tx_misra_uchar_pointer_dif + .global _tx_misra_uchar_pointer_sub + .global _tx_misra_uchar_to_align_type_pointer_convert + .global _tx_misra_uchar_to_block_pool_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_uchar_to_entry_pointer_convert + .global _tx_misra_uchar_to_header_pointer_convert +#endif + .global _tx_misra_uchar_to_indirect_byte_pool_pointer_convert + .global _tx_misra_uchar_to_indirect_uchar_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_uchar_to_object_pointer_convert +#endif + .global _tx_misra_uchar_to_void_pointer_convert + .global _tx_misra_ulong_pointer_add + .global _tx_misra_ulong_pointer_dif + .global _tx_misra_ulong_pointer_sub + .global _tx_misra_ulong_to_pointer_convert + .global _tx_misra_ulong_to_thread_pointer_convert + .global _tx_misra_user_timer_pointer_get + .global _tx_misra_void_to_block_pool_pointer_convert + .global _tx_misra_void_to_byte_pool_pointer_convert + .global _tx_misra_void_to_event_flags_pointer_convert + .global _tx_misra_void_to_indirect_uchar_pointer_convert + .global _tx_misra_void_to_mutex_pointer_convert + .global _tx_misra_void_to_queue_pointer_convert + .global _tx_misra_void_to_semaphore_pointer_convert + .global _tx_misra_void_to_thread_pointer_convert + .global _tx_misra_void_to_uchar_pointer_convert + .global _tx_misra_void_to_ulong_pointer_convert + .global _tx_misra_ipsr_get + .global _tx_misra_control_get + .global _tx_misra_control_set +#ifdef __ARM_FP + .global _tx_misra_fpccr_get + .global _tx_misra_vfp_touch +#endif + + .global _tx_misra_event_flags_group_not_used + .global _tx_misra_event_flags_set_notify_not_used + .global _tx_misra_queue_not_used + .global _tx_misra_queue_send_notify_not_used + .global _tx_misra_semaphore_not_used + .global _tx_misra_semaphore_put_notify_not_used + .global _tx_misra_thread_entry_exit_notify_not_used + .global _tx_misra_thread_not_used + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_memset(VOID *ptr, UINT value, UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .align 4 + .syntax unified + .thumb_func +_tx_misra_memset: + PUSH {R4,LR} + MOVS R4,R0 + MOVS R0,R2 + MOVS R2,R1 + MOVS R1,R0 + MOVS R0,R4 + BL __aeabi_memset + POP {R4,PC} // return + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_add(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_uchar_pointer_add: + ADD R0,R0,R1 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_sub(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_uchar_pointer_sub: + RSBS R1,R1,#+0 + ADD R0,R0,R1 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_uchar_pointer_dif(UCHAR *ptr1, UCHAR *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_uchar_pointer_dif: + SUBS R0,R0,R1 + BX LR // return + + +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ +/** */ +/** This single function serves all of the below prototypes. */ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** VOID _tx_misra_event_flags_group_not_used(TX_EVENT_FLAGS_GROUP *group_ptr); */ +/** VOID _tx_misra_event_flags_set_notify_not_used(VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); */ +/** VOID _tx_misra_queue_not_used(TX_QUEUE *queue_ptr); */ +/** VOID _tx_misra_queue_send_notify_not_used(VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); */ +/** VOID _tx_misra_semaphore_not_used(TX_SEMAPHORE *semaphore_ptr); */ +/** VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); */ +/** VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr); */ +/** VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)); */ +/** */ +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ + .text + .thumb_func +_tx_misra_pointer_to_ulong_convert: +_tx_misra_ulong_to_pointer_convert: +_tx_misra_indirect_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_indirect_uchar_pointer_convert: +_tx_misra_block_pool_to_uchar_pointer_convert: +_tx_misra_void_to_block_pool_pointer_convert: +_tx_misra_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_block_pool_pointer_convert: +_tx_misra_void_to_indirect_uchar_pointer_convert: +_tx_misra_void_to_byte_pool_pointer_convert: +_tx_misra_byte_pool_to_uchar_pointer_convert: +_tx_misra_uchar_to_align_type_pointer_convert: +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: +_tx_misra_void_to_event_flags_pointer_convert: +_tx_misra_void_to_ulong_pointer_convert: +_tx_misra_void_to_mutex_pointer_convert: +_tx_misra_void_to_queue_pointer_convert: +_tx_misra_void_to_semaphore_pointer_convert: +_tx_misra_uchar_to_void_pointer_convert: +_tx_misra_ulong_to_thread_pointer_convert: +_tx_misra_timer_indirect_to_void_pointer_convert: +_tx_misra_const_char_to_char_pointer_convert: +_tx_misra_void_to_thread_pointer_convert: +#ifdef TX_ENABLE_EVENT_TRACE +_tx_misra_object_to_uchar_pointer_convert: +_tx_misra_uchar_to_object_pointer_convert: +_tx_misra_uchar_to_header_pointer_convert: +_tx_misra_uchar_to_entry_pointer_convert: +_tx_misra_entry_to_uchar_pointer_convert: +#endif +_tx_misra_char_to_uchar_pointer_convert: +_tx_misra_event_flags_group_not_used: +_tx_misra_event_flags_set_notify_not_used: +_tx_misra_queue_not_used: +_tx_misra_queue_send_notify_not_used: +_tx_misra_semaphore_not_used: +_tx_misra_semaphore_put_notify_not_used: +_tx_misra_thread_entry_exit_notify_not_used: +_tx_misra_thread_not_used: + + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_add(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_ulong_pointer_add: + LSLS R1,#2 + ADD R0,R0,R1 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_sub(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_ulong_pointer_sub: + MOVS R3,#3 + MVNS R2,R3 + MULS R1,R2,R1 + ADD R0,R0,R1 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_ulong_pointer_dif(ULONG *ptr1, ULONG *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_ulong_pointer_dif: + SUBS R0,R0,R1 + ASRS R0,R0,#+2 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_message_copy(ULONG **source, ULONG **destination, */ +/** UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_message_copy: + PUSH {R4,R5} + LDR R3,[R0, #+0] + LDR R4,[R1, #+0] + LDR R5,[R3, #+0] + STR R5,[R4, #+0] + ADDS R4,R4,#+4 + ADDS R3,R3,#+4 + CMP R2,#+2 + BCC.N _tx_misra_message_copy_0 + SUBS R2,R2,#+1 + B.N _tx_misra_message_copy_1 +_tx_misra_message_copy_2: + LDR R5,[R3, #+0] + STR R5,[R4, #+0] + ADDS R4,R4,#+4 + ADDS R3,R3,#+4 + SUBS R2,R2,#+1 +_tx_misra_message_copy_1: + CMP R2,#+0 + BNE.N _tx_misra_message_copy_2 +_tx_misra_message_copy_0: + STR R3,[R0, #+0] + STR R4,[R1, #+0] + POP {R4,R5} + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_timer_pointer_dif(TX_TIMER_INTERNAL **ptr1, */ +/** TX_TIMER_INTERNAL **ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_timer_pointer_dif: + SUBS R0,R0,R1 + ASRS R0,R0,#+2 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** TX_TIMER_INTERNAL **_tx_misra_timer_pointer_add(TX_TIMER_INTERNAL */ +/** **ptr1, ULONG size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_timer_pointer_add: + LSLS R1,#2 + ADD R0,R0,R1 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL */ +/** *internal_timer, TX_TIMER **user_timer); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_user_timer_pointer_get: + SUBS R0,#8 + STR R0,[R1, #+0] + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, */ +/** VOID **highest_stack); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_thread_stack_check: + PUSH {R3-R7,LR} + MOVS R4,R0 + MOVS R5,R1 + BL _tx_thread_interrupt_disable + CMP R4,#0 + BEQ.N _tx_misra_thread_stack_check_0 + LDR R1,[R4] + LDR R2,=0x54485244 + CMP R1,R2 + BNE.N _tx_misra_thread_stack_check_0 + LDR R1,[R4, #8] + LDR R2,[R5] + CMP R1,R2 + BCS.N _tx_misra_thread_stack_check_1 + STR R1,[R5] +_tx_misra_thread_stack_check_1: + LDR R1,[R4, #12] + LDR R1,[R1] + LDR R6,=0xEFEFEFEF + CMP R1,R6 + BNE.N _tx_misra_thread_stack_check_2 + LDR R1,[R4, #16] + MOVS R7,#1 + LDR R1,[R1, R7] + CMP R1,R6 + BNE.N _tx_misra_thread_stack_check_2 + LDR R1,[R5] + LDR R2,[R4, #12] + CMP R1,R2 + BCS.N _tx_misra_thread_stack_check_3 +_tx_misra_thread_stack_check_2: + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_error_handler + BL _tx_thread_interrupt_disable +_tx_misra_thread_stack_check_3: + LDR R1,[R5] + LDR R7,=-4 + LDR R1,[R1, R7] + CMP R1,R6 + BEQ.N _tx_misra_thread_stack_check_0 + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_analyze + BL _tx_thread_interrupt_disable +_tx_misra_thread_stack_check_0: + BL _tx_thread_interrupt_restore + POP {R0,R4,R5,R6,R7,PC} // return + +#ifdef TX_ENABLE_EVENT_TRACE + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_trace_event_insert(ULONG event_id, */ +/** VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, */ +/** ULONG info_field_4, ULONG filter, ULONG time_stamp); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_trace_event_insert: + PUSH {R3-R7,LR} + LDR.N R4,DataTable2_1 + LDR R4,[R4, #+0] + CMP R4,#+0 + BEQ.N _tx_misra_trace_event_insert_0 + LDR.N R5,DataTable2_2 + LDR R5,[R5, #+0] + LDR R6,[SP, #+28] + TST R5,R6 + BEQ.N _tx_misra_trace_event_insert_0 + LDR.N R5,DataTable2_3 + LDR R5,[R5, #+0] + LDR.N R6,DataTable2_4 + LDR R6,[R6, #+0] + CMP R5,#+0 + BNE.N _tx_misra_trace_event_insert_1 + LDR R5,[R6, #+44] + LDR R7,[R6, #+60] + LSLS R7,R7,#+16 + ORRS R7,R7,#0x80000000 + ORRS R5,R7,R5 + B.N _tx_misra_trace_event_insert_2 +_tx_misra_trace_event_insert_1: + CMP R5,#-252645136 + BCS.N _tx_misra_trace_event_insert_3 + MOVS R5,R6 + MOVS R6,#-1 + B.N _tx_misra_trace_event_insert_2 +_tx_misra_trace_event_insert_3: + MOVS R6,#-252645136 + MOVS R5,#+0 +_tx_misra_trace_event_insert_2: + STR R6,[R4, #+0] + STR R5,[R4, #+4] + STR R0,[R4, #+8] + LDR R0,[SP, #+32] + STR R0,[R4, #+12] + STR R1,[R4, #+16] + STR R2,[R4, #+20] + STR R3,[R4, #+24] + LDR R0,[SP, #+24] + STR R0,[R4, #+28] + ADDS R4,R4,#+32 + LDR.N R0,DataTable2_5 + LDR R0,[R0, #+0] + CMP R4,R0 + BCC.N _tx_misra_trace_event_insert_4 + LDR.N R0,DataTable2_6 + LDR R4,[R0, #+0] + LDR.N R0,DataTable2_1 + STR R4,[R0, #+0] + LDR.N R0,DataTable2_7 + LDR R0,[R0, #+0] + STR R4,[R0, #+32] + LDR.N R0,DataTable2_8 + LDR R0,[R0, #+0] + CMP R0,#+0 + BEQ.N _tx_misra_trace_event_insert_0 + LDR.N R0,DataTable2_7 + LDR R0,[R0, #+0] + LDR.N R1,DataTable2_8 + LDR R1,[R1, #+0] + BLX R1 + B.N _tx_misra_trace_event_insert_0 +_tx_misra_trace_event_insert_4: + LDR.N R0,DataTable2_1 + STR R4,[R0, #+0] + LDR.N R0,DataTable2_7 + LDR R0,[R0, #+0] + STR R4,[R0, #+32] +_tx_misra_trace_event_insert_0: + POP {R0,R4-R7,PC} // return + + + .data +DataTable2_1: + .word _tx_trace_buffer_current_ptr + + .data +DataTable2_2: + .word _tx_trace_event_enable_bits + + .data +DataTable2_5: + .word _tx_trace_buffer_end_ptr + + .data +DataTable2_6: + .word _tx_trace_buffer_start_ptr + + .data +DataTable2_7: + .word _tx_trace_header_ptr + + .data +DataTable2_8: + .word _tx_trace_full_notify_function + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_time_stamp_get(VOID); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_time_stamp_get: + MOVS R0,#+0 + BX LR // return + +#endif + + .data +DataTable2_3: + .word _tx_thread_system_state + + .data +DataTable2_4: + .word _tx_thread_current_ptr + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_always_true(void); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_always_true: + MOVS R0,#+1 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_status_get(UINT status); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_status_get: + MOVS R0,#+0 + BX LR // return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_ipsr_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + .text + .thumb_func +_tx_misra_ipsr_get: + MRS R0, IPSR + BX LR // return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_control_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + .text + .thumb_func +_tx_misra_control_get: + MRS R0, CONTROL + BX LR // return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** void _tx_misra_control_set(ULONG value); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + .text + .thumb_func +_tx_misra_control_set: + MSR CONTROL, R0 + BX LR // return + + +#ifdef __ARM_FP + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_fpccr_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + .text + .thumb_func +_tx_misra_fpccr_get: + LDR r0, =0xE000EF34 // Build FPCCR address + LDR r0, [r0] // Load FPCCR value + BX LR // return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** void _tx_misra_vfp_touch(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + .text + .thumb_func +_tx_misra_vfp_touch: + vmov.f32 s0, s0 + BX LR // return + +#endif + + + .data + .word 0 diff --git a/ports/cortex_m23/gnu/src/tx_thread_secure_stack.c b/ports/cortex_m23/gnu/src/tx_thread_secure_stack.c index cd91548dc..ac7c70a56 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_secure_stack.c +++ b/ports/cortex_m23/gnu/src/tx_thread_secure_stack.c @@ -23,7 +23,7 @@ #include "tx_api.h" -/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, +/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, no secure stack functionality is needed. */ #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) @@ -44,8 +44,14 @@ #define TX_THREAD_STACK_SEAL_SIZE 8 #define TX_THREAD_STACK_SEAL_VALUE 0xFEF5EDA5 -/* Secure stack info struct to hold stack start, stack limit, - current stack pointer, and pointer to owning thread. +/* max number of Secure context */ +#ifndef TX_MAX_SECURE_CONTEXTS +#define TX_MAX_SECURE_CONTEXTS 32 +#endif +#define TX_INVALID_SECURE_CONTEXT_IDX (-1) + +/* Secure stack info struct to hold stack start, stack limit, + current stack pointer, and pointer to owning thread. This will be allocated for each thread with a secure stack. */ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT { @@ -53,8 +59,14 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */ VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */ TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */ + INT tx_next_free_index; /* Next free index of free secure context */ } TX_THREAD_SECURE_STACK_INFO; +/* Static secure contexts */ +static TX_THREAD_SECURE_STACK_INFO tx_thread_secure_context[TX_MAX_SECURE_CONTEXTS]; +/* Head of free secure context */ +static INT tx_head_free_index = 0U; + /**************************************************************************/ @@ -62,7 +74,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_initialize Cortex-M23/GNU */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -98,6 +110,9 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* name, execute in handler */ /* mode, disable optimization, */ /* resulting in version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry, optimize(0))) @@ -106,6 +121,7 @@ UINT _tx_thread_secure_mode_stack_initialize(void) UINT status; ULONG control; ULONG ipsr; +INT index; /* Make sure function is called from interrupt (threads should not call). */ asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ @@ -119,12 +135,26 @@ ULONG ipsr; asm volatile("MRS %0, CONTROL" : "=r" (control)); /* Get CONTROL register. */ control |= 2; /* Use PSP. */ asm volatile("MSR CONTROL, %0" :: "r" (control)); /* Set CONTROL register. */ - + /* Set process stack pointer and stack limit to 0 to throw exception when a thread without a secure stack calls a secure function that tries to use secure stack. */ asm volatile("MSR PSPLIM, %0" :: "r" (0)); asm volatile("MSR PSP, %0" :: "r" (0)); - + + for (index = 0; index < TX_MAX_SECURE_CONTEXTS; index++) + { + + /* Check last index and mark next free to invalid index */ + if(index == (TX_MAX_SECURE_CONTEXTS - 1)) + { + tx_thread_secure_context[index].tx_next_free_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + else + { + tx_thread_secure_context[index].tx_next_free_index = index + 1; + } + } + status = TX_SUCCESS; } return status; @@ -137,7 +167,7 @@ ULONG ipsr; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_allocate Cortex-M23/GNU */ -/* 6.1.3 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -160,9 +190,7 @@ ULONG ipsr; /* */ /* CALLS */ /* */ -/* calloc Compiler's calloc function */ /* malloc Compiler's malloc function */ -/* free Compiler's free() function */ /* */ /* CALLED BY */ /* */ @@ -179,20 +207,26 @@ ULONG ipsr; /* 12-31-2020 Scott Larson Modified comment(s), and */ /* fixed M23 GCC build, */ /* resulting in version 6.1.3 */ - +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* added */ +/* TX_INTERRUPT_SAVE_AREA, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; UCHAR *stack_mem; ULONG ipsr; ULONG psplim_ns; +INT secure_context_index; status = TX_SUCCESS; - + /* Make sure function is called from interrupt (threads should not call). */ asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ if (ipsr == 0) @@ -203,23 +237,38 @@ ULONG psplim_ns; { status = TX_SIZE_ERROR; } - + /* Check if thread already has secure stack allocated. */ else if (thread_ptr -> tx_thread_secure_stack_context != 0) { status = TX_THREAD_ERROR; } - + else { - /* Allocate space for secure stack info. */ - info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO)); - - if(info_ptr != TX_NULL) + TX_DISABLE + + /* Allocate free index for secure stack info. */ + if(tx_head_free_index != TX_INVALID_SECURE_CONTEXT_IDX) + { + secure_context_index = tx_head_free_index; + tx_head_free_index = tx_thread_secure_context[tx_head_free_index].tx_next_free_index; + tx_thread_secure_context[secure_context_index].tx_next_free_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + else + { + secure_context_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + + TX_RESTORE + + if(secure_context_index != TX_INVALID_SECURE_CONTEXT_IDX) { + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* If stack info allocated, allocate a stack & seal. */ stack_mem = malloc(stack_size + TX_THREAD_STACK_SEAL_SIZE); - + if(stack_mem != TX_NULL) { /* Secure stack has been allocated, save in the stack info struct. */ @@ -227,13 +276,13 @@ ULONG psplim_ns; info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size; info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start; info_ptr -> tx_thread_ptr = thread_ptr; - + /* Seal bottom of stack. */ *(ULONG*)info_ptr -> tx_thread_secure_stack_start = TX_THREAD_STACK_SEAL_VALUE; - - /* Save info pointer in thread. */ - thread_ptr -> tx_thread_secure_stack_context = info_ptr; - + + /* Save secure context id (i.e non-zero base index) in thread. */ + thread_ptr -> tx_thread_secure_stack_context = (VOID *)(secure_context_index + 1); + /* Check if this thread is running by looking at its stack start and PSPLIM_NS */ asm volatile("MRS %0, PSPLIM_NS" : "=r" (psplim_ns)); /* Get PSPLIM_NS register. */ if(((ULONG) thread_ptr -> tx_thread_stack_start & 0xFFFFFFF8) == psplim_ns) @@ -243,21 +292,26 @@ ULONG psplim_ns; asm volatile("MSR PSP, %0" :: "r" ((ULONG)(info_ptr -> tx_thread_secure_stack_ptr))); } } - + else { + TX_DISABLE + /* Stack not allocated, free the info struct. */ - free(info_ptr); + tx_thread_secure_context[secure_context_index].tx_next_free_index = tx_head_free_index; + tx_head_free_index = secure_context_index; + TX_RESTORE + status = TX_NO_MEMORY; } } - + else { status = TX_NO_MEMORY; } } - + return(status); } @@ -268,7 +322,7 @@ ULONG psplim_ns; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_free Cortex-M23/GNU */ -/* 6.1.3 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -305,46 +359,67 @@ ULONG psplim_ns; /* 12-31-2020 Scott Larson Modified comment(s), and */ /* fixed M23 GCC build, */ /* resulting in version 6.1.3 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG ipsr; +INT secure_context_index; status = TX_SUCCESS; - - /* Pickup stack info from thread. */ - info_ptr = thread_ptr -> tx_thread_secure_stack_context; - + + /* Pickup stack info id from thread. */ + secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; + /* Make sure function is called from interrupt (threads should not call). */ asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ if (ipsr == 0) { status = TX_CALLER_ERROR; } - - /* Check that this secure context is for this thread. */ - else if (info_ptr -> tx_thread_ptr != thread_ptr) + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) { status = TX_THREAD_ERROR; } - else { - - /* Free secure stack. */ - free(info_ptr -> tx_thread_secure_stack_limit); - - /* Free info struct. */ - free(info_ptr); - - /* Clear secure context from thread. */ - thread_ptr -> tx_thread_secure_stack_context = 0; + + /* Pickup stack info from static array of secure contexts. */ + info_ptr = &tx_thread_secure_context[secure_context_index]; + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Free secure stack. */ + free(info_ptr -> tx_thread_secure_stack_limit); + + TX_DISABLE + + /* Free info struct. */ + tx_thread_secure_context[secure_context_index].tx_next_free_index = tx_head_free_index; + tx_head_free_index = secure_context_index; + TX_RESTORE + + /* Clear secure context from thread. */ + thread_ptr -> tx_thread_secure_stack_context = 0; + } } - + return(status); } @@ -355,7 +430,7 @@ ULONG ipsr; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_save Cortex-M23/GNU */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -392,6 +467,9 @@ ULONG ipsr; /* resulting in version 6.1.3 */ /* 06-02-2021 Scott Larson Fix stack pointer save, */ /* resulting in version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) @@ -400,6 +478,7 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; ULONG ipsr; +INT secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; /* This function should be called from scheduler only. */ asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ @@ -407,32 +486,38 @@ ULONG ipsr; { return; } - + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) + { + return; + } + /* Pickup the secure context pointer. */ - info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); - + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* Check that this secure context is for this thread. */ if (info_ptr -> tx_thread_ptr != thread_ptr) { return; } - + /* Check that stack pointer is in range */ asm volatile("MRS %0, PSP" : "=r" (sp)); /* Get PSP register. */ - if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || + if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start)) { return; } - + /* Save stack pointer. */ info_ptr -> tx_thread_secure_stack_ptr = (VOID *) sp; - + /* Set process stack pointer and stack limit to 0 to throw exception when a thread without a secure stack calls a secure function that tries to use secure stack. */ asm volatile("MSR PSPLIM, %0" :: "r" (0)); asm volatile("MSR PSP, %0" :: "r" (0)); - + return; } @@ -443,7 +528,7 @@ ULONG ipsr; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_restore Cortex-M23/GNU */ -/* 6.1.3 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -478,6 +563,9 @@ ULONG ipsr; /* 12-31-2020 Scott Larson Modified comment(s), and */ /* fixed M23 GCC build, */ /* resulting in version 6.1.3 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) @@ -485,6 +573,7 @@ void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG ipsr; +INT secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; /* This function should be called from scheduler only. */ asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ @@ -492,20 +581,26 @@ ULONG ipsr; { return; } - + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) + { + return; + } + /* Pickup the secure context pointer. */ - info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); - + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* Check that this secure context is for this thread. */ if (info_ptr -> tx_thread_ptr != thread_ptr) { return; } - + /* Set stack pointer and limit. */ asm volatile("MSR PSPLIM, %0" :: "r" ((ULONG)info_ptr -> tx_thread_secure_stack_limit)); asm volatile("MSR PSP, %0" :: "r" ((ULONG)info_ptr -> tx_thread_secure_stack_ptr)); - + return; } diff --git a/ports/cortex_m23/gnu/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_initialize.S index 2d8bb868a..7efcef408 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_initialize.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M23/GNU */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -49,13 +49,17 @@ /* */ /* CALLED BY */ /* */ -/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */ +/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ /* RELEASE HISTORY */ /* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports/cortex_m23/iar/inc/tx_port.h b/ports/cortex_m23/iar/inc/tx_port.h index 73a540800..ba65d9be9 100644 --- a/ports/cortex_m23/iar/inc/tx_port.h +++ b/ports/cortex_m23/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M23/IAR */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -61,6 +61,10 @@ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -366,7 +370,7 @@ ULONG _tx_misra_ipsr_get(VOID); #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) /* Initialize secure stacks for threads calling secure functions. */ extern void _tx_thread_secure_stack_initialize(void); -#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to @@ -433,7 +437,7 @@ __istate_t interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/IAR Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/IAR Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m23/iar/src/tx_misra.s b/ports/cortex_m23/iar/src/tx_misra.s index acb85cc9b..11b2a1c7b 100644 --- a/ports/cortex_m23/iar/src/tx_misra.s +++ b/ports/cortex_m23/iar/src/tx_misra.s @@ -96,6 +96,22 @@ PUBLIC _tx_misra_void_to_uchar_pointer_convert PUBLIC _tx_misra_void_to_ulong_pointer_convert PUBLIC _tx_misra_ipsr_get + PUBLIC _tx_misra_control_get + PUBLIC _tx_misra_control_set +#ifdef __ARMVFP__ + PUBLIC _tx_misra_fpccr_get + PUBLIC _tx_misra_vfp_touch +#endif + + PUBLIC _tx_misra_event_flags_group_not_used + PUBLIC _tx_misra_event_flags_set_notify_not_used + PUBLIC _tx_misra_queue_not_used + PUBLIC _tx_misra_queue_send_notify_not_used + PUBLIC _tx_misra_semaphore_not_used + PUBLIC _tx_misra_semaphore_put_notify_not_used + PUBLIC _tx_misra_thread_entry_exit_notify_not_used + PUBLIC _tx_misra_thread_not_used + PUBLIC _tx_version_id @@ -109,7 +125,7 @@ _tx_version_id: DC8 45H, 78H, 70H, 72H, 65H, 73H, 73H, 20H DC8 4CH, 6FH, 67H, 69H, 63H, 20H, 49H, 6EH DC8 63H, 2EH, 20H, 2AH, 20H, 54H, 68H, 72H - DC8 65H, 61H, 64H, 58H, 20H, 36H, 2EH, 30H + DC8 65H, 61H, 64H, 58H, 20H, 36H, 2EH, 31H DC8 20H, 4DH, 49H, 53H, 52H, 41H, 20H, 43H DC8 20H, 43H, 6FH, 6DH, 70H, 6CH, 69H, 61H DC8 6EH, 74H, 20H, 2AH, 0 @@ -133,7 +149,7 @@ _tx_misra_memset: MOVS R1,R0 MOVS R0,R4 BL __aeabi_memset - POP {R4,PC} ;; return + POP {R4,PC} // return /**************************************************************************/ /**************************************************************************/ @@ -147,7 +163,7 @@ _tx_misra_memset: THUMB _tx_misra_uchar_pointer_add: ADD R0,R0,R1 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -163,7 +179,7 @@ _tx_misra_uchar_pointer_add: _tx_misra_uchar_pointer_sub: RSBS R1,R1,#+0 ADD R0,R0,R1 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -178,21 +194,97 @@ _tx_misra_uchar_pointer_sub: THUMB _tx_misra_uchar_pointer_dif: SUBS R0,R0,R1 - BX LR ;; return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - + BX LR // return + + +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ +/** */ +/** This single function serves all of the below prototypes. */ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** VOID _tx_misra_event_flags_group_not_used(TX_EVENT_FLAGS_GROUP *group_ptr); */ +/** VOID _tx_misra_event_flags_set_notify_not_used(VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); */ +/** VOID _tx_misra_queue_not_used(TX_QUEUE *queue_ptr); */ +/** VOID _tx_misra_queue_send_notify_not_used(VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); */ +/** VOID _tx_misra_semaphore_not_used(TX_SEMAPHORE *semaphore_ptr); */ +/** VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); */ +/** VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr); */ +/** VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)); */ +/** */ +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ SECTION `.text`:CODE:NOROOT(1) THUMB _tx_misra_pointer_to_ulong_convert: - BX LR ;; return +_tx_misra_ulong_to_pointer_convert: +_tx_misra_indirect_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_indirect_uchar_pointer_convert: +_tx_misra_block_pool_to_uchar_pointer_convert: +_tx_misra_void_to_block_pool_pointer_convert: +_tx_misra_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_block_pool_pointer_convert: +_tx_misra_void_to_indirect_uchar_pointer_convert: +_tx_misra_void_to_byte_pool_pointer_convert: +_tx_misra_byte_pool_to_uchar_pointer_convert: +_tx_misra_uchar_to_align_type_pointer_convert: +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: +_tx_misra_void_to_event_flags_pointer_convert: +_tx_misra_void_to_ulong_pointer_convert: +_tx_misra_void_to_mutex_pointer_convert: +_tx_misra_void_to_queue_pointer_convert: +_tx_misra_void_to_semaphore_pointer_convert: +_tx_misra_uchar_to_void_pointer_convert: +_tx_misra_ulong_to_thread_pointer_convert: +_tx_misra_timer_indirect_to_void_pointer_convert: +_tx_misra_const_char_to_char_pointer_convert: +_tx_misra_void_to_thread_pointer_convert: +#ifdef TX_ENABLE_EVENT_TRACE +_tx_misra_object_to_uchar_pointer_convert: +_tx_misra_uchar_to_object_pointer_convert: +_tx_misra_uchar_to_header_pointer_convert: +_tx_misra_uchar_to_entry_pointer_convert: +_tx_misra_entry_to_uchar_pointer_convert: +#endif +_tx_misra_char_to_uchar_pointer_convert: +_tx_misra_event_flags_group_not_used: +_tx_misra_event_flags_set_notify_not_used: +_tx_misra_queue_not_used: +_tx_misra_queue_send_notify_not_used: +_tx_misra_semaphore_not_used: +_tx_misra_semaphore_put_notify_not_used: +_tx_misra_thread_entry_exit_notify_not_used: +_tx_misra_thread_not_used: + + BX LR // return /**************************************************************************/ @@ -206,8 +298,9 @@ _tx_misra_pointer_to_ulong_convert: SECTION `.text`:CODE:NOROOT(1) THUMB _tx_misra_ulong_pointer_add: - ADD R0,R0,R1, LSL #+2 - BX LR ;; return + LSLS R1,#2 + ADD R0,R0,R1 + BX LR // return /**************************************************************************/ @@ -221,10 +314,11 @@ _tx_misra_ulong_pointer_add: SECTION `.text`:CODE:NOROOT(1) THUMB _tx_misra_ulong_pointer_sub: - MVNS R2,#+3 - MULS R1,R2,R1 - ADD R0,R0,R1 - BX LR ;; return + MOVS R3,#3 + MVNS R2,R3 + MULS R1,R2,R1 + ADD R0,R0,R1 + BX LR // return /**************************************************************************/ @@ -240,21 +334,7 @@ _tx_misra_ulong_pointer_sub: _tx_misra_ulong_pointer_dif: SUBS R0,R0,R1 ASRS R0,R0,#+2 - BX LR ;; return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_ulong_to_pointer_convert: - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -293,7 +373,7 @@ _tx_misra_message_copy: STR R3,[R0, #+0] STR R4,[R1, #+0] POP {R4,R5} - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -310,7 +390,7 @@ _tx_misra_message_copy: _tx_misra_timer_pointer_dif: SUBS R0,R0,R1 ASRS R0,R0,#+2 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -325,8 +405,9 @@ _tx_misra_timer_pointer_dif: SECTION `.text`:CODE:NOROOT(1) THUMB _tx_misra_timer_pointer_add: - ADD R0,R0,R1, LSL #+2 - BX LR ;; return + LSLS R1,#2 + ADD R0,R0,R1 + BX LR // return /**************************************************************************/ @@ -341,12 +422,9 @@ _tx_misra_timer_pointer_add: SECTION `.text`:CODE:NOROOT(1) THUMB _tx_misra_user_timer_pointer_get: - ADDS R2,R0,#+8 - SUBS R2,R2,R0 - RSBS R2,R2,#+0 - ADD R0,R0,R2 - STR R0,[R1, #+0] - BX LR ;; return + SUBS R0,#8 + STR R0,[R1, #+0] + BX LR // return /**************************************************************************/ @@ -361,52 +439,54 @@ _tx_misra_user_timer_pointer_get: SECTION `.text`:CODE:NOROOT(1) THUMB _tx_misra_thread_stack_check: - PUSH {R3-R5,LR} - MOVS R4,R0 - MOVS R5,R1 - BL _tx_thread_interrupt_disable - CMP R4,#+0 - BEQ.N ??_tx_misra_thread_stack_check_0 - LDR R1,[R4, #+0] - LDR.N R2,??DataTable2 ;; 0x54485244 - CMP R1,R2 - BNE.N ??_tx_misra_thread_stack_check_0 - LDR R1,[R4, #+8] - LDR R2,[R5, #+0] - CMP R1,R2 - BCS.N ??_tx_misra_thread_stack_check_1 - LDR R1,[R4, #+8] - STR R1,[R5, #+0] + PUSH {R3-R5,LR} + MOVS R4,R0 + MOVS R5,R1 + BL _tx_thread_interrupt_disable + CMP R4,#0 + BEQ.N ??_tx_misra_thread_stack_check_0 + LDR R1,[R4] + LDR.N R2,??DataTable2 // 0x54485244 + CMP R1,R2 + BNE.N ??_tx_misra_thread_stack_check_0 + LDR R1,[R4, #8] + LDR R2,[R5] + CMP R1,R2 + BCS.N ??_tx_misra_thread_stack_check_1 + STR R1,[R5] ??_tx_misra_thread_stack_check_1: - LDR R1,[R4, #+12] - LDR R1,[R1, #+0] - CMP R1,#-269488145 - BNE.N ??_tx_misra_thread_stack_check_2 - LDR R1,[R4, #+16] - LDR R1,[R1, #+1] - CMP R1,#-269488145 - BNE.N ??_tx_misra_thread_stack_check_2 - LDR R1,[R5, #+0] - LDR R2,[R4, #+12] - CMP R1,R2 - BCS.N ??_tx_misra_thread_stack_check_3 + LDR R1,[R4, #12] + LDR R1,[R1] + LDR R6,=0xEFEFEFEF + CMP R1,R6 + BNE.N ??_tx_misra_thread_stack_check_2 + LDR R1,[R4, #16] + MOVS R7,#1 + LDR R1,[R1, R7] + CMP R1,R6 + BNE.N ??_tx_misra_thread_stack_check_2 + LDR R1,[R5] + LDR R2,[R4, #12] + CMP R1,R2 + BCS.N ??_tx_misra_thread_stack_check_3 ??_tx_misra_thread_stack_check_2: - BL _tx_thread_interrupt_restore - MOVS R0,R4 - BL _tx_thread_stack_error_handler - BL _tx_thread_interrupt_disable + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_error_handler + BL _tx_thread_interrupt_disable ??_tx_misra_thread_stack_check_3: - LDR R1,[R5, #+0] - LDR R1,[R1, #-4] - CMP R1,#-269488145 - BEQ.N ??_tx_misra_thread_stack_check_0 - BL _tx_thread_interrupt_restore - MOVS R0,R4 - BL _tx_thread_stack_analyze - BL _tx_thread_interrupt_disable + LDR R1,[R5] + LDR R7,=-4 + LDR R1,[R1, R7] + CMP R1,R6 + BEQ.N ??_tx_misra_thread_stack_check_0 + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_analyze + BL _tx_thread_interrupt_disable ??_tx_misra_thread_stack_check_0: - BL _tx_thread_interrupt_restore - POP {R0,R4,R5,PC} ;; return + BL _tx_thread_interrupt_restore + POP {R0,R4,R5,R6,R7,PC} // return #ifdef TX_ENABLE_EVENT_TRACE @@ -494,7 +574,7 @@ _tx_misra_trace_event_insert: LDR R0,[R0, #+0] STR R4,[R0, #+32] ??_tx_misra_trace_event_insert_0: - POP {R0,R4-R7,PC} ;; return + POP {R0,R4-R7,PC} // return SECTION `.text`:CODE:NOROOT(2) @@ -546,7 +626,7 @@ _tx_misra_trace_event_insert: THUMB _tx_misra_time_stamp_get: MOVS R0,#+0 - BX LR ;; return + BX LR // return #endif @@ -581,203 +661,7 @@ _tx_misra_time_stamp_get: THUMB _tx_misra_always_true: MOVS R0,#+1 - BX LR ;; return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_indirect_void_to_uchar_pointer_convert: - BX LR ;; return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_indirect_uchar_pointer_convert: - BX LR ;; return - - -/***********************************************************************************/ -/***********************************************************************************/ -/** */ -/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ -/** */ -/***********************************************************************************/ -/***********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_block_pool_to_uchar_pointer_convert: - BX LR ;; return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_block_pool_pointer_convert: - BX LR ;; return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_uchar_pointer_convert: - BX LR ;; return - - -/************************************************************************************/ -/************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************/ -/************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_block_pool_pointer_convert: - BX LR ;; return - - -/**************************************************************************************/ -/**************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************/ -/**************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_indirect_uchar_pointer_convert: - BX LR ;; return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_byte_pool_pointer_convert: - BX LR ;; return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_byte_pool_to_uchar_pointer_convert: - BX LR ;; return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_align_type_pointer_convert: - BX LR ;; return - - -/****************************************************************************************************/ -/****************************************************************************************************/ -/** */ -/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/****************************************************************************************************/ -/****************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: - BX LR ;; return - - -/**************************************************************************************************/ -/**************************************************************************************************/ -/** */ -/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************************/ -/**************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_event_flags_pointer_convert: - BX LR ;; return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_ulong_pointer_convert: - BX LR ;; return - - -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_mutex_pointer_convert: - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -792,209 +676,89 @@ _tx_misra_void_to_mutex_pointer_convert: THUMB _tx_misra_status_get: MOVS R0,#+0 - BX LR ;; return - - -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_queue_pointer_convert: - BX LR ;; return - - -/****************************************************************************************/ -/****************************************************************************************/ -/** */ -/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ -/** */ -/****************************************************************************************/ -/****************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_semaphore_pointer_convert: - BX LR ;; return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_void_pointer_convert: - BX LR ;; return - - -/*********************************************************************************/ -/*********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ -/** */ -/*********************************************************************************/ -/*********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_ulong_to_thread_pointer_convert: - BX LR ;; return + BX LR // return -/***************************************************************************************************/ -/***************************************************************************************************/ -/** */ -/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ -/** */ -/***************************************************************************************************/ -/***************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_timer_indirect_to_void_pointer_convert: - BX LR ;; return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_const_char_to_char_pointer_convert: - BX LR ;; return - - -/**********************************************************************************/ -/**********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ -/** */ -/**********************************************************************************/ -/**********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_thread_pointer_convert: - BX LR ;; return - - -#ifdef TX_ENABLE_EVENT_TRACE - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_object_to_uchar_pointer_convert: - BX LR ;; return - - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_object_pointer_convert: - BX LR ;; return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_ipsr_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ SECTION `.text`:CODE:NOROOT(1) THUMB -_tx_misra_uchar_to_header_pointer_convert: - BX LR ;; return +_tx_misra_ipsr_get: + MRS R0, IPSR + BX LR // return /***********************************************************************************************/ /***********************************************************************************************/ /** */ -/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** ULONG _tx_misra_control_get(void); */ /** */ /***********************************************************************************************/ /***********************************************************************************************/ SECTION `.text`:CODE:NOROOT(1) THUMB -_tx_misra_uchar_to_entry_pointer_convert: - BX LR ;; return - +_tx_misra_control_get: + MRS R0, CONTROL + BX LR // return + /***********************************************************************************************/ /***********************************************************************************************/ /** */ -/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** void _tx_misra_control_set(ULONG value); */ /** */ /***********************************************************************************************/ /***********************************************************************************************/ SECTION `.text`:CODE:NOROOT(1) THUMB -_tx_misra_entry_to_uchar_pointer_convert: - BX LR ;; return -#endif +_tx_misra_control_set: + MSR CONTROL, R0 + BX LR // return + +#ifdef __ARMVFP__ /***********************************************************************************************/ /***********************************************************************************************/ /** */ -/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** ULONG _tx_misra_fpccr_get(void); */ /** */ /***********************************************************************************************/ /***********************************************************************************************/ - SECTION `.text`:CODE:NOROOT(1) + SECTION `.text`:CODE:NOROOT(2) THUMB -_tx_misra_char_to_uchar_pointer_convert: - BX LR ;; return - - -***********************************************************************************************/ +_tx_misra_fpccr_get: + LDR r0, =0xE000EF34 // Build FPCCR address + LDR r0, [r0] // Load FPCCR value + BX LR // return + + +/***********************************************************************************************/ /***********************************************************************************************/ /** */ -/** ULONG _tx_misra_ipsr_get(void); */ +/** void _tx_misra_vfp_touch(void); */ /** */ /***********************************************************************************************/ /***********************************************************************************************/ SECTION `.text`:CODE:NOROOT(1) THUMB -_tx_misra_ipsr_get: - MRS R0, IPSR - BX LR ;; return - - +_tx_misra_vfp_touch: + vmov.f32 s0, s0 + BX LR // return + +#endif + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports/cortex_m23/iar/src/tx_thread_secure_stack.c b/ports/cortex_m23/iar/src/tx_thread_secure_stack.c index 72e3af971..7cb0061ea 100644 --- a/ports/cortex_m23/iar/src/tx_thread_secure_stack.c +++ b/ports/cortex_m23/iar/src/tx_thread_secure_stack.c @@ -23,7 +23,7 @@ #include "tx_api.h" -/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, +/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, no secure stack functionality is needed. */ #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) @@ -45,8 +45,14 @@ #define TX_THREAD_STACK_SEAL_SIZE 8 #define TX_THREAD_STACK_SEAL_VALUE 0xFEF5EDA5 -/* Secure stack info struct to hold stack start, stack limit, - current stack pointer, and pointer to owning thread. +/* max number of Secure context */ +#ifndef TX_MAX_SECURE_CONTEXTS +#define TX_MAX_SECURE_CONTEXTS 32 +#endif +#define TX_INVALID_SECURE_CONTEXT_IDX (-1) + +/* Secure stack info struct to hold stack start, stack limit, + current stack pointer, and pointer to owning thread. This will be allocated for each thread with a secure stack. */ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT { @@ -54,8 +60,14 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */ VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */ TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */ + INT tx_next_free_index; /* Next free index of free secure context */ } TX_THREAD_SECURE_STACK_INFO; +/* Static secure contexts */ +static TX_THREAD_SECURE_STACK_INFO tx_thread_secure_context[TX_MAX_SECURE_CONTEXTS]; +/* Head of free secure context */ +static INT tx_head_free_index = 0U; + /**************************************************************************/ @@ -63,7 +75,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_initialize Cortex-M23/IAR */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -102,12 +114,16 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* name, execute in handler */ /* mode, disable optimization, */ /* resulting in version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) { UINT status; +INT index; /* Make sure function is called from interrupt (threads should not call). */ if (__get_IPSR() == 0) @@ -118,12 +134,26 @@ UINT status; { /* Set secure mode to use PSP. */ __set_CONTROL(__get_CONTROL() | 2); - + /* Set process stack pointer and stack limit to 0 to throw exception when a thread without a secure stack calls a secure function that tries to use secure stack. */ __set_PSPLIM(0); __set_PSP(0); - + + for (index = 0; index < TX_MAX_SECURE_CONTEXTS; index++) + { + + /* Check last index and mark next free to invalid index */ + if(index == (TX_MAX_SECURE_CONTEXTS - 1)) + { + tx_thread_secure_context[index].tx_next_free_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + else + { + tx_thread_secure_context[index].tx_next_free_index = index + 1; + } + } + status = TX_SUCCESS; } return status; @@ -136,7 +166,7 @@ UINT status; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_allocate Cortex-M23/IAR */ -/* 6.1.1 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -160,9 +190,7 @@ UINT status; /* CALLS */ /* */ /* __get_IPSR Intrinsic to get IPSR */ -/* calloc Compiler's calloc function */ /* malloc Compiler's malloc function */ -/* free Compiler's free() function */ /* __set_PSPLIM Intrinsic to set PSP limit */ /* __set_PSP Intrinsic to set PSP */ /* __TZ_get_PSPLIM_NS Intrinsic to get NS PSP */ @@ -179,18 +207,24 @@ UINT status; /* 10-16-2020 Scott Larson Modified comment(s), */ /* added stack sealing, */ /* resulting in version 6.1.1 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* added */ +/* TX_INTERRUPT_SAVE_AREA, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; UCHAR *stack_mem; -ULONG sp; +INT secure_context_index; status = TX_SUCCESS; - + /* Make sure function is called from interrupt (threads should not call). */ if (__get_IPSR() == 0) { @@ -200,23 +234,38 @@ ULONG sp; { status = TX_SIZE_ERROR; } - + /* Check if thread already has secure stack allocated. */ else if (thread_ptr -> tx_thread_secure_stack_context != 0) { status = TX_THREAD_ERROR; } - + else { - /* Allocate space for secure stack info. */ - info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO)); - - if(info_ptr != TX_NULL) + TX_DISABLE + + /* Allocate free index for secure stack info. */ + if(tx_head_free_index != TX_INVALID_SECURE_CONTEXT_IDX) + { + secure_context_index = tx_head_free_index; + tx_head_free_index = tx_thread_secure_context[tx_head_free_index].tx_next_free_index; + tx_thread_secure_context[secure_context_index].tx_next_free_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + else + { + secure_context_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + + TX_RESTORE + + if(secure_context_index != TX_INVALID_SECURE_CONTEXT_IDX) { + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* If stack info allocated, allocate a stack & seal. */ stack_mem = malloc(stack_size + TX_THREAD_STACK_SEAL_SIZE); - + if(stack_mem != TX_NULL) { /* Secure stack has been allocated, save in the stack info struct. */ @@ -224,38 +273,41 @@ ULONG sp; info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size; info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start; info_ptr -> tx_thread_ptr = thread_ptr; - + /* Seal bottom of stack. */ *(ULONG*)info_ptr -> tx_thread_secure_stack_start = TX_THREAD_STACK_SEAL_VALUE; - - /* Save info pointer in thread. */ - thread_ptr -> tx_thread_secure_stack_context = info_ptr; - - /* Check if this thread is running by looking at PSP_NS and seeing if it is within - the stack_start and stack_end range. */ - sp = __TZ_get_PSP_NS(); - if(sp > ((ULONG) thread_ptr -> tx_thread_stack_start) && sp < ((ULONG) thread_ptr -> tx_thread_stack_end)) + + /* Save secure context id (i.e non-zero base index) in thread. */ + thread_ptr -> tx_thread_secure_stack_context = (VOID *)(secure_context_index + 1); + + /* Check if this thread is running by looking at its stack start and PSPLIM_NS */ + if(((ULONG) thread_ptr -> tx_thread_stack_start & 0xFFFFFFF8) == __TZ_get_PSPLIM_NS()) { /* If this thread is running, set Secure PSP and PSPLIM. */ __set_PSPLIM((ULONG)(info_ptr -> tx_thread_secure_stack_limit)); __set_PSP((ULONG)(info_ptr -> tx_thread_secure_stack_ptr)); } } - + else { + TX_DISABLE + /* Stack not allocated, free the info struct. */ - free(info_ptr); + tx_thread_secure_context[secure_context_index].tx_next_free_index = tx_head_free_index; + tx_head_free_index = secure_context_index; + TX_RESTORE + status = TX_NO_MEMORY; } } - + else { status = TX_NO_MEMORY; } } - + return(status); } @@ -266,7 +318,7 @@ ULONG sp; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_free Cortex-M23/IAR */ -/* 6.1.1 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -301,44 +353,67 @@ ULONG sp; /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* added */ +/* TX_INTERRUPT_SAVE_AREA, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; +INT secure_context_index; status = TX_SUCCESS; - - /* Pickup stack info from thread. */ - info_ptr = thread_ptr -> tx_thread_secure_stack_context; - + + /* Pickup stack info id from thread. */ + secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; + /* Make sure function is called from interrupt (threads should not call). */ if (__get_IPSR() == 0) { status = TX_CALLER_ERROR; } - - /* Check that this secure context is for this thread. */ - else if (info_ptr -> tx_thread_ptr != thread_ptr) + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) { status = TX_THREAD_ERROR; } - else { - - /* Free secure stack. */ - free(info_ptr -> tx_thread_secure_stack_limit); - - /* Free info struct. */ - free(info_ptr); - - /* Clear secure context from thread. */ - thread_ptr -> tx_thread_secure_stack_context = 0; + + /* Pickup stack info from static array of secure contexts. */ + info_ptr = &tx_thread_secure_context[secure_context_index]; + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Free secure stack. */ + free(info_ptr -> tx_thread_secure_stack_limit); + + TX_DISABLE + + /* Free info struct. */ + tx_thread_secure_context[secure_context_index].tx_next_free_index = tx_head_free_index; + tx_head_free_index = secure_context_index; + TX_RESTORE + + /* Clear secure context from thread. */ + thread_ptr -> tx_thread_secure_stack_context = 0; + } } - + return(status); } @@ -349,7 +424,7 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_save Cortex-M23/IAR */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -386,6 +461,9 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr; /* resulting in version 6.1.1 */ /* 06-02-2021 Scott Larson Fix stack pointer save, */ /* resulting in version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) @@ -393,38 +471,45 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; +INT secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { return; } - + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) + { + return; + } + /* Pickup the secure context pointer. */ - info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); - + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* Check that this secure context is for this thread. */ if (info_ptr -> tx_thread_ptr != thread_ptr) { return; } - + /* Check that stack pointer is in range */ sp = __get_PSP(); - if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || + if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start)) { return; } - + /* Save stack pointer. */ info_ptr -> tx_thread_secure_stack_ptr = (VOID *) sp; - + /* Set process stack pointer and stack limit to 0 to throw exception when a thread without a secure stack calls a secure function that tries to use secure stack. */ __set_PSPLIM(0); __set_PSP(0); - + return; } @@ -435,7 +520,7 @@ ULONG sp; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_restore Cortex-M23/IAR */ -/* 6.1.1 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -469,32 +554,42 @@ ULONG sp; /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; +INT secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { return; } - + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) + { + return; + } + /* Pickup the secure context pointer. */ - info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); - + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* Check that this secure context is for this thread. */ if (info_ptr -> tx_thread_ptr != thread_ptr) { return; } - + /* Set stack pointer and limit. */ __set_PSPLIM((ULONG)info_ptr -> tx_thread_secure_stack_limit); __set_PSP ((ULONG)info_ptr -> tx_thread_secure_stack_ptr); - + return; } diff --git a/ports/cortex_m23/iar/src/tx_thread_secure_stack_initialize.s b/ports/cortex_m23/iar/src/tx_thread_secure_stack_initialize.s index 092ed49c9..26ec4fb57 100644 --- a/ports/cortex_m23/iar/src/tx_thread_secure_stack_initialize.s +++ b/ports/cortex_m23/iar/src/tx_thread_secure_stack_initialize.s @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M23/IAR */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -50,13 +50,17 @@ /* */ /* CALLED BY */ /* */ -/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */ +/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ /* RELEASE HISTORY */ /* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports/cortex_m3/ac5/inc/tx_port.h b/ports/cortex_m3/ac5/inc/tx_port.h index e29c80c8c..b446fc833 100644 --- a/ports/cortex_m3/ac5/inc/tx_port.h +++ b/ports/cortex_m3/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/AC5 */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -59,6 +59,9 @@ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -146,6 +149,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -707,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC5 Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC5 Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/ac6/inc/tx_port.h b/ports/cortex_m3/ac6/inc/tx_port.h index eedf0164b..ebbe5133c 100644 --- a/ports/cortex_m3/ac6/inc/tx_port.h +++ b/ports/cortex_m3/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/AC6 */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -59,6 +59,9 @@ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -146,6 +149,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -707,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC6 Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC6 Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/ac6/src/tx_misra.S b/ports/cortex_m3/ac6/src/tx_misra.S index b03fdcd01..155512be4 100644 --- a/ports/cortex_m3/ac6/src/tx_misra.S +++ b/ports/cortex_m3/ac6/src/tx_misra.S @@ -103,6 +103,14 @@ .global _tx_misra_vfp_touch #endif + .global _tx_misra_event_flags_group_not_used + .global _tx_misra_event_flags_set_notify_not_used + .global _tx_misra_queue_not_used + .global _tx_misra_queue_send_notify_not_used + .global _tx_misra_semaphore_not_used + .global _tx_misra_semaphore_put_notify_not_used + .global _tx_misra_thread_entry_exit_notify_not_used + .global _tx_misra_thread_not_used /**************************************************************************/ /**************************************************************************/ @@ -172,17 +180,93 @@ _tx_misra_uchar_pointer_dif: BX LR // return -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ +/** */ +/** This single function serves all of the below prototypes. */ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** VOID _tx_misra_event_flags_group_not_used(TX_EVENT_FLAGS_GROUP *group_ptr); */ +/** VOID _tx_misra_event_flags_set_notify_not_used(VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); */ +/** VOID _tx_misra_queue_not_used(TX_QUEUE *queue_ptr); */ +/** VOID _tx_misra_queue_send_notify_not_used(VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); */ +/** VOID _tx_misra_semaphore_not_used(TX_SEMAPHORE *semaphore_ptr); */ +/** VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); */ +/** VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr); */ +/** VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)); */ +/** */ +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ .text .thumb_func _tx_misra_pointer_to_ulong_convert: +_tx_misra_ulong_to_pointer_convert: +_tx_misra_indirect_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_indirect_uchar_pointer_convert: +_tx_misra_block_pool_to_uchar_pointer_convert: +_tx_misra_void_to_block_pool_pointer_convert: +_tx_misra_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_block_pool_pointer_convert: +_tx_misra_void_to_indirect_uchar_pointer_convert: +_tx_misra_void_to_byte_pool_pointer_convert: +_tx_misra_byte_pool_to_uchar_pointer_convert: +_tx_misra_uchar_to_align_type_pointer_convert: +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: +_tx_misra_void_to_event_flags_pointer_convert: +_tx_misra_void_to_ulong_pointer_convert: +_tx_misra_void_to_mutex_pointer_convert: +_tx_misra_void_to_queue_pointer_convert: +_tx_misra_void_to_semaphore_pointer_convert: +_tx_misra_uchar_to_void_pointer_convert: +_tx_misra_ulong_to_thread_pointer_convert: +_tx_misra_timer_indirect_to_void_pointer_convert: +_tx_misra_const_char_to_char_pointer_convert: +_tx_misra_void_to_thread_pointer_convert: +#ifdef TX_ENABLE_EVENT_TRACE +_tx_misra_object_to_uchar_pointer_convert: +_tx_misra_uchar_to_object_pointer_convert: +_tx_misra_uchar_to_header_pointer_convert: +_tx_misra_uchar_to_entry_pointer_convert: +_tx_misra_entry_to_uchar_pointer_convert: +#endif +_tx_misra_char_to_uchar_pointer_convert: +_tx_misra_event_flags_group_not_used: +_tx_misra_event_flags_set_notify_not_used: +_tx_misra_queue_not_used: +_tx_misra_queue_send_notify_not_used: +_tx_misra_semaphore_not_used: +_tx_misra_semaphore_put_notify_not_used: +_tx_misra_thread_entry_exit_notify_not_used: +_tx_misra_thread_not_used: + BX LR // return @@ -234,20 +318,6 @@ _tx_misra_ulong_pointer_dif: BX LR // return -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - .text - .thumb_func -_tx_misra_ulong_to_pointer_convert: - BX LR // return - - /**************************************************************************/ /**************************************************************************/ /** */ @@ -332,12 +402,9 @@ _tx_misra_timer_pointer_add: .text .thumb_func _tx_misra_user_timer_pointer_get: - ADDS R2,R0,#+8 - SUBS R2,R2,R0 - RSBS R2,R2,#+0 - ADD R0,R0,R2 - STR R0,[R1, #+0] - BX LR // return + SUBS R0,#8 + STR R0,[R1, #+0] + BX LR // return /**************************************************************************/ @@ -553,202 +620,6 @@ _tx_misra_always_true: BX LR // return -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - .text - .thumb_func -_tx_misra_indirect_void_to_uchar_pointer_convert: - BX LR // return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_indirect_uchar_pointer_convert: - BX LR // return - - -/***********************************************************************************/ -/***********************************************************************************/ -/** */ -/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ -/** */ -/***********************************************************************************/ -/***********************************************************************************/ - - .text - .thumb_func -_tx_misra_block_pool_to_uchar_pointer_convert: - BX LR // return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_block_pool_pointer_convert: - BX LR // return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_uchar_pointer_convert: - BX LR // return - - -/************************************************************************************/ -/************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************/ -/************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_block_pool_pointer_convert: - BX LR // return - - -/**************************************************************************************/ -/**************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************/ -/**************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_indirect_uchar_pointer_convert: - BX LR // return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_byte_pool_pointer_convert: - BX LR // return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - .text - .thumb_func -_tx_misra_byte_pool_to_uchar_pointer_convert: - BX LR // return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_align_type_pointer_convert: - BX LR // return - - -/****************************************************************************************************/ -/****************************************************************************************************/ -/** */ -/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/****************************************************************************************************/ -/****************************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: - BX LR // return - - -/**************************************************************************************************/ -/**************************************************************************************************/ -/** */ -/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************************/ -/**************************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_event_flags_pointer_convert: - BX LR // return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_ulong_pointer_convert: - BX LR // return - - -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_mutex_pointer_convert: - BX LR // return - - /**************************************************************************/ /**************************************************************************/ /** */ @@ -764,191 +635,6 @@ _tx_misra_status_get: BX LR // return -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_queue_pointer_convert: - BX LR // return - - -/****************************************************************************************/ -/****************************************************************************************/ -/** */ -/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ -/** */ -/****************************************************************************************/ -/****************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_semaphore_pointer_convert: - BX LR // return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_void_pointer_convert: - BX LR // return - - -/*********************************************************************************/ -/*********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ -/** */ -/*********************************************************************************/ -/*********************************************************************************/ - - .text - .thumb_func -_tx_misra_ulong_to_thread_pointer_convert: - BX LR // return - - -/***************************************************************************************************/ -/***************************************************************************************************/ -/** */ -/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ -/** */ -/***************************************************************************************************/ -/***************************************************************************************************/ - - .text - .thumb_func -_tx_misra_timer_indirect_to_void_pointer_convert: - BX LR // return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - .text - .thumb_func -_tx_misra_const_char_to_char_pointer_convert: - BX LR // return - - -/**********************************************************************************/ -/**********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ -/** */ -/**********************************************************************************/ -/**********************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_thread_pointer_convert: - BX LR // return - - -#ifdef TX_ENABLE_EVENT_TRACE - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - .text - .thumb_func -_tx_misra_object_to_uchar_pointer_convert: - BX LR // return - - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_object_pointer_convert: - BX LR // return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_header_pointer_convert: - BX LR // return - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_entry_pointer_convert: - BX LR // return - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - .text - .thumb_func -_tx_misra_entry_to_uchar_pointer_convert: - BX LR // return -#endif - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - .text - .thumb_func -_tx_misra_char_to_uchar_pointer_convert: - BX LR // return - - /***********************************************************************************************/ /***********************************************************************************************/ /** */ diff --git a/ports/cortex_m3/gnu/example_build/build_threadx.bat b/ports/cortex_m3/gnu/example_build/build_threadx.bat index 79f240b03..de39b850e 100644 --- a/ports/cortex_m3/gnu/example_build/build_threadx.bat +++ b/ports/cortex_m3/gnu/example_build/build_threadx.bat @@ -1,5 +1,4 @@ del tx.a -arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb tx_initialize_low_level.S arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ../src/tx_thread_stack_build.S arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ../src/tx_thread_schedule.S arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ../src/tx_thread_system_return.S @@ -7,7 +6,7 @@ arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ../src/tx_thread_context_save.S arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ../src/tx_thread_context_restore.S arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ../src/tx_thread_interrupt_control.S arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ../src/tx_timer_interrupt.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ../src/tx_thread_interrupt_control.S + arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c @@ -192,8 +191,8 @@ arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../in arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c + arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o -arm-none-eabi-ar -r tx.a tx_thread_interrupt_control.o tx_initialize_low_level.o arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o diff --git a/ports/cortex_m3/gnu/example_build/build_threadx_sample.bat b/ports/cortex_m3/gnu/example_build/build_threadx_sample.bat index cc93371f3..5b060df8b 100644 --- a/ports/cortex_m3/gnu/example_build/build_threadx_sample.bat +++ b/ports/cortex_m3/gnu/example_build/build_threadx_sample.bat @@ -1,7 +1,5 @@ -arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb tx_simulator_startup.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb cortexm3_vectors.S arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb cortexm3_crt0.S arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb tx_initialize_low_level.S arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc sample_threadx.c -arm-none-eabi-ld -A cortex-m3 -ereset_handler -T sample_threadx.ld tx_simulator_startup.o cortexm3_crt0.o tx_initialize_low_level.o sample_threadx.o tx.a libc.a -o sample_threadx.out -M > sample_threadx.map - - +arm-none-eabi-gcc -g -mcpu=cortex-m3 -mthumb -T sample_threadx.ld -ereset_handler -nostartfiles -o sample_threadx.out -Wl,-Map=sample_threadx.map cortexm3_vectors.o cortexm3_crt0.o tx_initialize_low_level.o sample_threadx.o tx.a diff --git a/ports/cortex_m4/gnu/example_build/cortexm4_crt0.s b/ports/cortex_m3/gnu/example_build/cortexm3_crt0.S similarity index 72% rename from ports/cortex_m4/gnu/example_build/cortexm4_crt0.s rename to ports/cortex_m3/gnu/example_build/cortexm3_crt0.S index d4cb16360..4228fc110 100644 --- a/ports/cortex_m4/gnu/example_build/cortexm4_crt0.s +++ b/ports/cortex_m3/gnu/example_build/cortexm3_crt0.S @@ -1,45 +1,20 @@ - .global _start - .extern main - - + .syntax unified .section .init, "ax" .code 16 .align 2 .thumb_func - + .global _start _start: CPSID i ldr r1, =__stack_end__ mov sp, r1 - /* Copy initialised sections into RAM if required. */ ldr r0, =__data_load_start__ ldr r1, =__data_start__ ldr r2, =__data_end__ bl crt0_memory_copy - ldr r0, =__text_load_start__ - ldr r1, =__text_start__ - ldr r2, =__text_end__ - bl crt0_memory_copy - ldr r0, =__fast_load_start__ - ldr r1, =__fast_start__ - ldr r2, =__fast_end__ - bl crt0_memory_copy - ldr r0, =__ctors_load_start__ - ldr r1, =__ctors_start__ - ldr r2, =__ctors_end__ - bl crt0_memory_copy - ldr r0, =__dtors_load_start__ - ldr r1, =__dtors_start__ - ldr r2, =__dtors_end__ - bl crt0_memory_copy - ldr r0, =__rodata_load_start__ - ldr r1, =__rodata_start__ - ldr r2, =__rodata_end__ - bl crt0_memory_copy - /* Zero bss. */ ldr r0, =__bss_start__ @@ -47,7 +22,6 @@ _start: mov r2, #0 bl crt0_memory_set - /* Setup heap - not recommended for Threadx but here for compatibility reasons */ ldr r0, = __heap_start__ ldr r1, = __heap_end__ @@ -57,7 +31,6 @@ _start: add r0, r0, #4 str r1, [r0] - /* constructors in case of using C++ */ ldr r0, =__ctors_start__ ldr r1, =__ctors_end__ @@ -72,13 +45,11 @@ crt0_ctor_loop: b crt0_ctor_loop crt0_ctor_end: - /* Setup call frame for main() */ mov r0, #0 mov lr, r0 mov r12, sp - start: /* Jump to main() */ mov r0, #0 @@ -88,28 +59,22 @@ start: /* when main returns, loop forever. */ crt0_exit_loop: b crt0_exit_loop - - /* Startup helper functions. */ - crt0_memory_copy: cmp r0, r1 beq memory_copy_done - sub r2, r2, r1 - beq memory_copy_done memory_copy_loop: ldrb r3, [r0] add r0, r0, #1 strb r3, [r1] add r1, r1, #1 - sub r2, r2, #1 + cmp r1, r2 bne memory_copy_loop memory_copy_done: bx lr - crt0_memory_set: cmp r0, r1 beq memory_set_done @@ -119,7 +84,6 @@ crt0_memory_set: memory_set_done: bx lr - /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */ .section .stack, "wa", %nobits .section .stack_process, "wa", %nobits diff --git a/ports/cortex_m3/gnu/example_build/tx_simulator_startup.s b/ports/cortex_m3/gnu/example_build/cortexm3_vectors.S similarity index 90% rename from ports/cortex_m3/gnu/example_build/tx_simulator_startup.s rename to ports/cortex_m3/gnu/example_build/cortexm3_vectors.S index cf0db9742..6ae558e4d 100644 --- a/ports/cortex_m3/gnu/example_build/tx_simulator_startup.s +++ b/ports/cortex_m3/gnu/example_build/cortexm3_vectors.S @@ -1,5 +1,3 @@ - - .global reset_handler .global __tx_NMIHandler @@ -10,7 +8,6 @@ .global __tx_SysTickHandler .global __tx_BadHandler - .syntax unified .section .vectors, "ax" .code 16 @@ -29,7 +26,7 @@ _vectors: .word 0 // Reserved .word 0 // Reserved .word 0 // Reserved - .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // + .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved .word __tx_PendSVHandler @@ -70,14 +67,10 @@ _vectors: .word __tx_BadHandler .word __tx_BadHandler - - - .section .init, "ax" - .thumb_func + .section .init, "ax" + .thumb_func reset_handler: - -// low level hardware config, such as PLL setup goes here - + // low level hardware config, such as PLL setup goes here b _start diff --git a/ports/cortex_m3/gnu/example_build/sample_threadx.ld b/ports/cortex_m3/gnu/example_build/sample_threadx.ld index 28f203fdf..c65a13464 100644 --- a/ports/cortex_m3/gnu/example_build/sample_threadx.ld +++ b/ports/cortex_m3/gnu/example_build/sample_threadx.ld @@ -1,206 +1,125 @@ MEMORY { - UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0 - CM3_System_Control_Space (wx) : ORIGIN = 0xe000e000, LENGTH = 0x00001000 - AHB_Peripherals (wx) : ORIGIN = 0x50000000, LENGTH = 0x00200000 - APB1_Peripherals (wx) : ORIGIN = 0x40080000, LENGTH = 0x00080000 - APB0_Peripherals (wx) : ORIGIN = 0x40000000, LENGTH = 0x00080000 - GPIO (wx) : ORIGIN = 0x2009c000, LENGTH = 0x00004000 - AHBSRAM1 (wx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 - AHBSRAM0 (wx) : ORIGIN = 0x2007c000, LENGTH = 0x00004000 - RAM (wx) : ORIGIN = 0x10000000, LENGTH = 0x00008000 - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + RAM (wx) : ORIGIN = 0x20000000, LENGTH = 0x00800000 + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00400000 } +__STACKSIZE__ = 1024; +__STACKSIZE_PROCESS__ = 0; +__HEAPSIZE__ = 128; SECTIONS { - __CM3_System_Control_Space_segment_start__ = 0xe000e000; - __CM3_System_Control_Space_segment_end__ = 0xe000f000; - __AHB_Peripherals_segment_start__ = 0x50000000; - __AHB_Peripherals_segment_end__ = 0x50200000; - __APB1_Peripherals_segment_start__ = 0x40080000; - __APB1_Peripherals_segment_end__ = 0x40100000; - __APB0_Peripherals_segment_start__ = 0x40000000; - __APB0_Peripherals_segment_end__ = 0x40080000; - __GPIO_segment_start__ = 0x2009c000; - __GPIO_segment_end__ = 0x200a0000; - __AHBSRAM1_segment_start__ = 0x20080000; - __AHBSRAM1_segment_end__ = 0x20084000; - __AHBSRAM0_segment_start__ = 0x2007c000; - __AHBSRAM0_segment_end__ = 0x20080000; - __RAM_segment_start__ = 0x10000000; - __RAM_segment_end__ = 0x10008000; - __FLASH_segment_start__ = 0x00000000; - __FLASH_segment_end__ = 0x00080000; - - __STACKSIZE__ = 1024; - __STACKSIZE_PROCESS__ = 0; - __STACKSIZE_IRQ__ = 0; - __STACKSIZE_FIQ__ = 0; - __STACKSIZE_SVC__ = 0; - __STACKSIZE_ABT__ = 0; - __STACKSIZE_UND__ = 0; - __HEAPSIZE__ = 128; - - __vectors_load_start__ = __FLASH_segment_start__; - .vectors __FLASH_segment_start__ : AT(__FLASH_segment_start__) + .vectors : { - __vectors_start__ = .; - *(.vectors .vectors.*) - } - __vectors_end__ = __vectors_start__ + SIZEOF(.vectors); - - . = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .vectors is too large to fit in FLASH memory segment"); - - __init_load_start__ = ALIGN(__vectors_end__ , 4); - .init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4)) - { - __init_start__ = .; - *(.init .init.*) - } - __init_end__ = __init_start__ + SIZEOF(.init); - - . = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .init is too large to fit in FLASH memory segment"); - - __text_load_start__ = ALIGN(__init_end__ , 4); - .text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4)) - { - __text_start__ = .; - *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table) - } - __text_end__ = __text_start__ + SIZEOF(.text); - - . = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .text is too large to fit in FLASH memory segment"); - - __dtors_load_start__ = ALIGN(__text_end__ , 4); - .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4)) - { - __dtors_start__ = .; - KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) - } - __dtors_end__ = __dtors_start__ + SIZEOF(.dtors); - - . = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .dtors is too large to fit in FLASH memory segment"); - - __ctors_load_start__ = ALIGN(__dtors_end__ , 4); - .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4)) - { - __ctors_start__ = .; - KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) - } - __ctors_end__ = __ctors_start__ + SIZEOF(.ctors); - - . = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .ctors is too large to fit in FLASH memory segment"); - - __rodata_load_start__ = ALIGN(__ctors_end__ , 4); - .rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4)) - { - __rodata_start__ = .; - *(.rodata .rodata.* .gnu.linkonce.r.*) - } - __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - - . = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .rodata is too large to fit in FLASH memory segment"); - - __fast_load_start__ = ALIGN(__rodata_end__ , 4); - .fast ALIGN(__RAM_segment_start__ , 4) : AT(ALIGN(__rodata_end__ , 4)) - { - __fast_start__ = .; - *(.fast .fast.*) - } - __fast_end__ = __fast_start__ + SIZEOF(.fast); - - __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast); - - . = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00080000) , "error: .fast is too large to fit in FLASH memory segment"); - - .fast_run ALIGN(__RAM_segment_start__ , 4) (NOLOAD) : - { - __fast_run_start__ = .; - . = MAX(__fast_run_start__ + SIZEOF(.fast), .); - } - __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run); - - . = ASSERT(__fast_run_end__ >= __RAM_segment_start__ && __fast_run_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .fast_run is too large to fit in RAM memory segment"); - - __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4); - .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4)) - { - __data_start__ = .; - *(.data .data.* .gnu.linkonce.d.*) - } - __data_end__ = __data_start__ + SIZEOF(.data); - - __data_load_end__ = __data_load_start__ + SIZEOF(.data); - - __FLASH_segment_used_end__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4) + SIZEOF(.data); - - . = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00080000) , "error: .data is too large to fit in FLASH memory segment"); - - .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) : - { - __data_run_start__ = .; - . = MAX(__data_run_start__ + SIZEOF(.data), .); - } - __data_run_end__ = __data_run_start__ + SIZEOF(.data_run); - - . = ASSERT(__data_run_end__ >= __RAM_segment_start__ && __data_run_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .data_run is too large to fit in RAM memory segment"); - - __bss_load_start__ = ALIGN(__data_run_end__ , 4); - .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4)) - { - __bss_start__ = .; - *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) - } - __bss_end__ = __bss_start__ + SIZEOF(.bss); - - . = ASSERT(__bss_end__ >= __RAM_segment_start__ && __bss_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .bss is too large to fit in RAM memory segment"); - - __non_init_load_start__ = ALIGN(__bss_end__ , 4); - .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4)) - { - __non_init_start__ = .; - *(.non_init .non_init.*) - } - __non_init_end__ = __non_init_start__ + SIZEOF(.non_init); - - . = ASSERT(__non_init_end__ >= __RAM_segment_start__ && __non_init_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .non_init is too large to fit in RAM memory segment"); - - __heap_load_start__ = ALIGN(__non_init_end__ , 4); - .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4)) - { - __heap_start__ = .; + KEEP(*(.vectors .vectors.*)) + } > FLASH + + .text : + { + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + __ctors_start__ = ALIGN(4); + *(SORT(.ctors.*)) + *(.ctors) + __ctors_end__ = ALIGN(4); + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + __dtors_start__ = ALIGN(4); + *(SORT(.dtors.*)) + *(.dtors) + __dtors_end__ = ALIGN(4); + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __data_load_start__ = ALIGN (4); + + .data : AT (__data_load_start__) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + + } > RAM + + .heap (COPY): + { + __heap_start__ = ALIGN(4); *(.heap) - . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4); - } - __heap_end__ = __heap_start__ + SIZEOF(.heap); - - . = ASSERT(__heap_end__ >= __RAM_segment_start__ && __heap_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .heap is too large to fit in RAM memory segment"); + . = ALIGN(. + __HEAPSIZE__, 4); + __heap_end__ = ALIGN(4); + } > RAM - __stack_load_start__ = ALIGN(__heap_end__ , 4); - .stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4)) + .stack ALIGN(4) (NOLOAD) : { - __stack_start__ = .; + __stack_start__ = ALIGN(4); *(.stack) - . = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4); - } - __stack_end__ = __stack_start__ + SIZEOF(.stack); - - . = ASSERT(__stack_end__ >= __RAM_segment_start__ && __stack_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .stack is too large to fit in RAM memory segment"); - - __stack_process_load_start__ = ALIGN(__stack_end__ , 4); - .stack_process ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4)) - { - __stack_process_start__ = .; - *(.stack_process) - . = ALIGN(MAX(__stack_process_start__ + __STACKSIZE_PROCESS__ , .), 4); - } - __stack_process_end__ = __stack_process_start__ + SIZEOF(.stack_process); - - __RAM_segment_used_end__ = ALIGN(__stack_end__ , 4) + SIZEOF(.stack_process); - - . = ASSERT(__stack_process_end__ >= __RAM_segment_start__ && __stack_process_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .stack_process is too large to fit in RAM memory segment"); + . = ALIGN(. + __STACKSIZE__, 4); + __stack_end__ = ALIGN(4); + } > RAM + __RAM_segment_used_end__ = .; } - diff --git a/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S index e9e90acae..14a85b892 100644 --- a/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S @@ -1,226 +1,201 @@ -@/**************************************************************************/ -@/* */ -@/* Copyright (c) Microsoft Corporation. All rights reserved. */ -@/* */ -@/* This software is licensed under the Microsoft Software License */ -@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -@/* and in the root directory of this software. */ -@/* */ -@/**************************************************************************/ -@ -@ -@/**************************************************************************/ -@/**************************************************************************/ -@/** */ -@/** ThreadX Component */ -@/** */ -@/** Initialize */ -@/** */ -@/**************************************************************************/ -@/**************************************************************************/ -@ -@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + .global _tx_thread_system_stack_ptr .global _tx_initialize_unused_memory .global __RAM_segment_used_end__ .global _tx_timer_interrupt .global __main - .global __tx_SVCallHandler - .global __tx_PendSVHandler .global _vectors - .global __tx_NMIHandler @ NMI - .global __tx_BadHandler @ HardFault - .global __tx_SVCallHandler @ SVCall - .global __tx_DBGHandler @ Monitor - .global __tx_PendSVHandler @ PendSV - .global __tx_SysTickHandler @ SysTick - .global __tx_IntHandler @ Int 0 -@ -@ + .global __tx_NMIHandler // NMI + .global __tx_BadHandler // HardFault + .global __tx_SVCallHandler // SVCall + .global __tx_DBGHandler // Monitor + .global __tx_PendSVHandler // PendSV + .global __tx_SysTickHandler // SysTick + .global __tx_IntHandler // Int 0 + SYSTEM_CLOCK = 6000000 SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) .text 32 .align 4 .syntax unified -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_initialize_low_level Cortex-M3/GNU */ -@/* 6.1 */ -@/* AUTHOR */ -@/* */ -@/* William E. Lamie, Microsoft Corporation */ -@/* */ -@/* DESCRIPTION */ -@/* */ -@/* This function is responsible for any low-level processor */ -@/* initialization, including setting up interrupt vectors, setting */ -@/* up a periodic timer interrupt source, saving the system stack */ -@/* pointer for use in ISR processing later, and finding the first */ -@/* available RAM memory address for tx_application_define. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 09-30-2020 William E. Lamie Modified Comment(s), fixed */ -@/* GNU assembly comment, clean */ -@/* up whitespace, resulting */ -@/* in version 6.1 */ -@/* */ -@/**************************************************************************/ -@VOID _tx_initialize_low_level(VOID) -@{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M3/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified Comment(s), fixed */ +/* GNU assembly comment, clean */ +/* up whitespace, resulting */ +/* in version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { .global _tx_initialize_low_level .thumb_func _tx_initialize_low_level: -@ -@ /* Disable interrupts during ThreadX initialization. */ -@ + + /* Disable interrupts during ThreadX initialization. */ CPSID i -@ -@ /* Set base of available memory to end of non-initialised RAM area. */ -@ - LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer - LDR r1, =__RAM_segment_used_end__ @ Build first free address - ADD r1, r1, #4 @ - STR r1, [r0] @ Setup first unused memory pointer -@ -@ /* Setup Vector Table Offset Register. */ -@ - MOV r0, #0xE000E000 @ Build address of NVIC registers - LDR r1, =_vectors @ Pickup address of vector table - STR r1, [r0, #0xD08] @ Set vector table address -@ -@ /* Set system stack pointer from vector value. */ -@ - LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer - LDR r1, =_vectors @ Pickup address of vector table - LDR r1, [r1] @ Pickup reset stack pointer - STR r1, [r0] @ Save system stack pointer -@ -@ /* Enable the cycle count register. */ -@ - LDR r0, =0xE0001000 @ Build address of DWT register - LDR r1, [r0] @ Pickup the current value - ORR r1, r1, #1 @ Set the CYCCNTENA bit - STR r1, [r0] @ Enable the cycle count register -@ -@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ -@ - MOV r0, #0xE000E000 @ Build address of NVIC registers + + /* Set base of available memory to end of non-initialised RAM area. */ + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =__RAM_segment_used_end__ // Build first free address + ADD r1, r1, #4 // + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =_vectors // Pickup address of vector table + STR r1, [r0, #0xD08] // Set vector table address + + /* Set system stack pointer from vector value. */ + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =_vectors // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Enable the cycle count register. */ + LDR r0, =0xE0001000 // Build address of DWT register + LDR r1, [r0] // Pickup the current value + ORR r1, r1, #1 // Set the CYCCNTENA bit + STR r1, [r0] // Enable the cycle count register + + /* Configure SysTick. */ + MOV r0, #0xE000E000 // Build address of NVIC registers LDR r1, =SYSTICK_CYCLES - STR r1, [r0, #0x14] @ Setup SysTick Reload Value - MOV r1, #0x7 @ Build SysTick Control Enable Value - STR r1, [r0, #0x10] @ Setup SysTick Control -@ -@ /* Configure handler priorities. */ -@ - LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM - STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers - - LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv - STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers - @ Note: SVC must be lowest priority, which is 0xFF - - LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM - STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers - @ Note: PnSV must be lowest priority, which is 0xFF -@ -@ /* Return to caller. */ -@ + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOV r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control + + /* Configure handler priorities. */ + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF + + /* Return to caller. */ BX lr -@} -@ +// } -@/* Define shells for each of the unused vectors. */ -@ +/* Define shells for each of the unused vectors. */ .global __tx_BadHandler .thumb_func __tx_BadHandler: B __tx_BadHandler -@ /* added to catch the hardfault */ - +/* added to catch the hardfault */ .global __tx_HardfaultHandler .thumb_func __tx_HardfaultHandler: B __tx_HardfaultHandler - -@ /* added to catch the SVC */ - +/* added to catch the SVC */ .global __tx_SVCallHandler .thumb_func __tx_SVCallHandler: B __tx_SVCallHandler - -@ /* Generic interrupt handler template */ +/* Generic interrupt handler template */ .global __tx_IntHandler .thumb_func __tx_IntHandler: -@ VOID InterruptHandler (VOID) -@ { +// VOID InterruptHandler (VOID) +// { PUSH {r0, lr} #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_enter @ Call the ISR enter function + BL _tx_execution_isr_enter // Call the ISR enter function #endif - -@ /* Do interrupt handler work here */ -@ /* BL .... */ - + /* Do interrupt handler work here */ + /* BL .... */ #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_exit @ Call the ISR exit function + BL _tx_execution_isr_exit // Call the ISR exit function #endif POP {r0, lr} BX LR -@ } +// } -@ /* System Tick timer interrupt handler */ +/* System Tick timer interrupt handler */ .global __tx_SysTickHandler .global SysTick_Handler .thumb_func __tx_SysTickHandler: .thumb_func SysTick_Handler: -@ VOID TimerInterruptHandler (VOID) -@ { -@ +// VOID SysTick_Handler (VOID) +// { PUSH {r0, lr} #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_enter @ Call the ISR enter function + BL _tx_execution_isr_enter // Call the ISR enter function #endif BL _tx_timer_interrupt #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_exit @ Call the ISR exit function + BL _tx_execution_isr_exit // Call the ISR exit function #endif POP {r0, lr} - BX LR -@ } - + BX lr +// } -@ /* NMI, DBG handlers */ +/* NMI, DBG handlers */ .global __tx_NMIHandler .thumb_func __tx_NMIHandler: diff --git a/ports/cortex_m3/gnu/inc/tx_port.h b/ports/cortex_m3/gnu/inc/tx_port.h index 54a16b801..7d94c5d58 100644 --- a/ports/cortex_m3/gnu/inc/tx_port.h +++ b/ports/cortex_m3/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/GNU */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -59,6 +59,9 @@ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -146,6 +149,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -707,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/GNU Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/GNU Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/gnu/src/tx_misra.S b/ports/cortex_m3/gnu/src/tx_misra.S index b03fdcd01..155512be4 100644 --- a/ports/cortex_m3/gnu/src/tx_misra.S +++ b/ports/cortex_m3/gnu/src/tx_misra.S @@ -103,6 +103,14 @@ .global _tx_misra_vfp_touch #endif + .global _tx_misra_event_flags_group_not_used + .global _tx_misra_event_flags_set_notify_not_used + .global _tx_misra_queue_not_used + .global _tx_misra_queue_send_notify_not_used + .global _tx_misra_semaphore_not_used + .global _tx_misra_semaphore_put_notify_not_used + .global _tx_misra_thread_entry_exit_notify_not_used + .global _tx_misra_thread_not_used /**************************************************************************/ /**************************************************************************/ @@ -172,17 +180,93 @@ _tx_misra_uchar_pointer_dif: BX LR // return -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ +/** */ +/** This single function serves all of the below prototypes. */ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** VOID _tx_misra_event_flags_group_not_used(TX_EVENT_FLAGS_GROUP *group_ptr); */ +/** VOID _tx_misra_event_flags_set_notify_not_used(VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); */ +/** VOID _tx_misra_queue_not_used(TX_QUEUE *queue_ptr); */ +/** VOID _tx_misra_queue_send_notify_not_used(VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); */ +/** VOID _tx_misra_semaphore_not_used(TX_SEMAPHORE *semaphore_ptr); */ +/** VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); */ +/** VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr); */ +/** VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)); */ +/** */ +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ .text .thumb_func _tx_misra_pointer_to_ulong_convert: +_tx_misra_ulong_to_pointer_convert: +_tx_misra_indirect_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_indirect_uchar_pointer_convert: +_tx_misra_block_pool_to_uchar_pointer_convert: +_tx_misra_void_to_block_pool_pointer_convert: +_tx_misra_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_block_pool_pointer_convert: +_tx_misra_void_to_indirect_uchar_pointer_convert: +_tx_misra_void_to_byte_pool_pointer_convert: +_tx_misra_byte_pool_to_uchar_pointer_convert: +_tx_misra_uchar_to_align_type_pointer_convert: +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: +_tx_misra_void_to_event_flags_pointer_convert: +_tx_misra_void_to_ulong_pointer_convert: +_tx_misra_void_to_mutex_pointer_convert: +_tx_misra_void_to_queue_pointer_convert: +_tx_misra_void_to_semaphore_pointer_convert: +_tx_misra_uchar_to_void_pointer_convert: +_tx_misra_ulong_to_thread_pointer_convert: +_tx_misra_timer_indirect_to_void_pointer_convert: +_tx_misra_const_char_to_char_pointer_convert: +_tx_misra_void_to_thread_pointer_convert: +#ifdef TX_ENABLE_EVENT_TRACE +_tx_misra_object_to_uchar_pointer_convert: +_tx_misra_uchar_to_object_pointer_convert: +_tx_misra_uchar_to_header_pointer_convert: +_tx_misra_uchar_to_entry_pointer_convert: +_tx_misra_entry_to_uchar_pointer_convert: +#endif +_tx_misra_char_to_uchar_pointer_convert: +_tx_misra_event_flags_group_not_used: +_tx_misra_event_flags_set_notify_not_used: +_tx_misra_queue_not_used: +_tx_misra_queue_send_notify_not_used: +_tx_misra_semaphore_not_used: +_tx_misra_semaphore_put_notify_not_used: +_tx_misra_thread_entry_exit_notify_not_used: +_tx_misra_thread_not_used: + BX LR // return @@ -234,20 +318,6 @@ _tx_misra_ulong_pointer_dif: BX LR // return -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - .text - .thumb_func -_tx_misra_ulong_to_pointer_convert: - BX LR // return - - /**************************************************************************/ /**************************************************************************/ /** */ @@ -332,12 +402,9 @@ _tx_misra_timer_pointer_add: .text .thumb_func _tx_misra_user_timer_pointer_get: - ADDS R2,R0,#+8 - SUBS R2,R2,R0 - RSBS R2,R2,#+0 - ADD R0,R0,R2 - STR R0,[R1, #+0] - BX LR // return + SUBS R0,#8 + STR R0,[R1, #+0] + BX LR // return /**************************************************************************/ @@ -553,202 +620,6 @@ _tx_misra_always_true: BX LR // return -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - .text - .thumb_func -_tx_misra_indirect_void_to_uchar_pointer_convert: - BX LR // return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_indirect_uchar_pointer_convert: - BX LR // return - - -/***********************************************************************************/ -/***********************************************************************************/ -/** */ -/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ -/** */ -/***********************************************************************************/ -/***********************************************************************************/ - - .text - .thumb_func -_tx_misra_block_pool_to_uchar_pointer_convert: - BX LR // return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_block_pool_pointer_convert: - BX LR // return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_uchar_pointer_convert: - BX LR // return - - -/************************************************************************************/ -/************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************/ -/************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_block_pool_pointer_convert: - BX LR // return - - -/**************************************************************************************/ -/**************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************/ -/**************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_indirect_uchar_pointer_convert: - BX LR // return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_byte_pool_pointer_convert: - BX LR // return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - .text - .thumb_func -_tx_misra_byte_pool_to_uchar_pointer_convert: - BX LR // return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_align_type_pointer_convert: - BX LR // return - - -/****************************************************************************************************/ -/****************************************************************************************************/ -/** */ -/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/****************************************************************************************************/ -/****************************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: - BX LR // return - - -/**************************************************************************************************/ -/**************************************************************************************************/ -/** */ -/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************************/ -/**************************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_event_flags_pointer_convert: - BX LR // return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_ulong_pointer_convert: - BX LR // return - - -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_mutex_pointer_convert: - BX LR // return - - /**************************************************************************/ /**************************************************************************/ /** */ @@ -764,191 +635,6 @@ _tx_misra_status_get: BX LR // return -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_queue_pointer_convert: - BX LR // return - - -/****************************************************************************************/ -/****************************************************************************************/ -/** */ -/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ -/** */ -/****************************************************************************************/ -/****************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_semaphore_pointer_convert: - BX LR // return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_void_pointer_convert: - BX LR // return - - -/*********************************************************************************/ -/*********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ -/** */ -/*********************************************************************************/ -/*********************************************************************************/ - - .text - .thumb_func -_tx_misra_ulong_to_thread_pointer_convert: - BX LR // return - - -/***************************************************************************************************/ -/***************************************************************************************************/ -/** */ -/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ -/** */ -/***************************************************************************************************/ -/***************************************************************************************************/ - - .text - .thumb_func -_tx_misra_timer_indirect_to_void_pointer_convert: - BX LR // return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - .text - .thumb_func -_tx_misra_const_char_to_char_pointer_convert: - BX LR // return - - -/**********************************************************************************/ -/**********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ -/** */ -/**********************************************************************************/ -/**********************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_thread_pointer_convert: - BX LR // return - - -#ifdef TX_ENABLE_EVENT_TRACE - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - .text - .thumb_func -_tx_misra_object_to_uchar_pointer_convert: - BX LR // return - - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_object_pointer_convert: - BX LR // return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_header_pointer_convert: - BX LR // return - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_entry_pointer_convert: - BX LR // return - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - .text - .thumb_func -_tx_misra_entry_to_uchar_pointer_convert: - BX LR // return -#endif - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - .text - .thumb_func -_tx_misra_char_to_uchar_pointer_convert: - BX LR // return - - /***********************************************************************************************/ /***********************************************************************************************/ /** */ diff --git a/ports/cortex_m3/iar/CMakeLists.txt b/ports/cortex_m3/iar/CMakeLists.txt new file mode 100644 index 000000000..a524d79f0 --- /dev/null +++ b/ports/cortex_m3/iar/CMakeLists.txt @@ -0,0 +1,21 @@ + +target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} + ${CMAKE_CURRENT_LIST_DIR}/src/tx_iar.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_disable.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S + # {{END_TARGET_SOURCES}} +) + +target_include_directories(${PROJECT_NAME} + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/inc +) diff --git a/ports/cortex_m3/iar/inc/tx_port.h b/ports/cortex_m3/iar/inc/tx_port.h index 77c52fba1..0781aecd1 100644 --- a/ports/cortex_m3/iar/inc/tx_port.h +++ b/ports/cortex_m3/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/IAR */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -59,6 +59,9 @@ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -146,6 +149,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -707,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/IAR Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/IAR Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/iar/src/tx_misra.s b/ports/cortex_m3/iar/src/tx_misra.s index 2add69b34..c81c3e5cc 100644 --- a/ports/cortex_m3/iar/src/tx_misra.s +++ b/ports/cortex_m3/iar/src/tx_misra.s @@ -102,6 +102,16 @@ PUBLIC _tx_misra_fpccr_get PUBLIC _tx_misra_vfp_touch #endif + + PUBLIC _tx_misra_event_flags_group_not_used + PUBLIC _tx_misra_event_flags_set_notify_not_used + PUBLIC _tx_misra_queue_not_used + PUBLIC _tx_misra_queue_send_notify_not_used + PUBLIC _tx_misra_semaphore_not_used + PUBLIC _tx_misra_semaphore_put_notify_not_used + PUBLIC _tx_misra_thread_entry_exit_notify_not_used + PUBLIC _tx_misra_thread_not_used + PUBLIC _tx_version_id @@ -115,7 +125,7 @@ _tx_version_id: DC8 45H, 78H, 70H, 72H, 65H, 73H, 73H, 20H DC8 4CH, 6FH, 67H, 69H, 63H, 20H, 49H, 6EH DC8 63H, 2EH, 20H, 2AH, 20H, 54H, 68H, 72H - DC8 65H, 61H, 64H, 58H, 20H, 35H, 2EH, 38H + DC8 65H, 61H, 64H, 58H, 20H, 36H, 2EH, 31H DC8 20H, 4DH, 49H, 53H, 52H, 41H, 20H, 43H DC8 20H, 43H, 6FH, 6DH, 70H, 6CH, 69H, 61H DC8 6EH, 74H, 20H, 2AH, 0 @@ -139,7 +149,7 @@ _tx_misra_memset: MOVS R1,R0 MOVS R0,R4 BL __aeabi_memset - POP {R4,PC} ;; return + POP {R4,PC} // return /**************************************************************************/ /**************************************************************************/ @@ -153,7 +163,7 @@ _tx_misra_memset: THUMB _tx_misra_uchar_pointer_add: ADD R0,R0,R1 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -169,7 +179,7 @@ _tx_misra_uchar_pointer_add: _tx_misra_uchar_pointer_sub: RSBS R1,R1,#+0 ADD R0,R0,R1 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -184,21 +194,97 @@ _tx_misra_uchar_pointer_sub: THUMB _tx_misra_uchar_pointer_dif: SUBS R0,R0,R1 - BX LR ;; return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - + BX LR // return + + +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ +/** */ +/** This single function serves all of the below prototypes. */ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** VOID _tx_misra_event_flags_group_not_used(TX_EVENT_FLAGS_GROUP *group_ptr); */ +/** VOID _tx_misra_event_flags_set_notify_not_used(VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); */ +/** VOID _tx_misra_queue_not_used(TX_QUEUE *queue_ptr); */ +/** VOID _tx_misra_queue_send_notify_not_used(VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); */ +/** VOID _tx_misra_semaphore_not_used(TX_SEMAPHORE *semaphore_ptr); */ +/** VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); */ +/** VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr); */ +/** VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)); */ +/** */ +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ SECTION `.text`:CODE:NOROOT(1) THUMB _tx_misra_pointer_to_ulong_convert: - BX LR ;; return +_tx_misra_ulong_to_pointer_convert: +_tx_misra_indirect_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_indirect_uchar_pointer_convert: +_tx_misra_block_pool_to_uchar_pointer_convert: +_tx_misra_void_to_block_pool_pointer_convert: +_tx_misra_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_block_pool_pointer_convert: +_tx_misra_void_to_indirect_uchar_pointer_convert: +_tx_misra_void_to_byte_pool_pointer_convert: +_tx_misra_byte_pool_to_uchar_pointer_convert: +_tx_misra_uchar_to_align_type_pointer_convert: +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: +_tx_misra_void_to_event_flags_pointer_convert: +_tx_misra_void_to_ulong_pointer_convert: +_tx_misra_void_to_mutex_pointer_convert: +_tx_misra_void_to_queue_pointer_convert: +_tx_misra_void_to_semaphore_pointer_convert: +_tx_misra_uchar_to_void_pointer_convert: +_tx_misra_ulong_to_thread_pointer_convert: +_tx_misra_timer_indirect_to_void_pointer_convert: +_tx_misra_const_char_to_char_pointer_convert: +_tx_misra_void_to_thread_pointer_convert: +#ifdef TX_ENABLE_EVENT_TRACE +_tx_misra_object_to_uchar_pointer_convert: +_tx_misra_uchar_to_object_pointer_convert: +_tx_misra_uchar_to_header_pointer_convert: +_tx_misra_uchar_to_entry_pointer_convert: +_tx_misra_entry_to_uchar_pointer_convert: +#endif +_tx_misra_char_to_uchar_pointer_convert: +_tx_misra_event_flags_group_not_used: +_tx_misra_event_flags_set_notify_not_used: +_tx_misra_queue_not_used: +_tx_misra_queue_send_notify_not_used: +_tx_misra_semaphore_not_used: +_tx_misra_semaphore_put_notify_not_used: +_tx_misra_thread_entry_exit_notify_not_used: +_tx_misra_thread_not_used: + + BX LR // return /**************************************************************************/ @@ -213,7 +299,7 @@ _tx_misra_pointer_to_ulong_convert: THUMB _tx_misra_ulong_pointer_add: ADD R0,R0,R1, LSL #+2 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -230,7 +316,7 @@ _tx_misra_ulong_pointer_sub: MVNS R2,#+3 MULS R1,R2,R1 ADD R0,R0,R1 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -246,21 +332,7 @@ _tx_misra_ulong_pointer_sub: _tx_misra_ulong_pointer_dif: SUBS R0,R0,R1 ASRS R0,R0,#+2 - BX LR ;; return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_ulong_to_pointer_convert: - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -299,7 +371,7 @@ _tx_misra_message_copy: STR R3,[R0, #+0] STR R4,[R1, #+0] POP {R4,R5} - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -316,7 +388,7 @@ _tx_misra_message_copy: _tx_misra_timer_pointer_dif: SUBS R0,R0,R1 ASRS R0,R0,#+2 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -332,7 +404,7 @@ _tx_misra_timer_pointer_dif: THUMB _tx_misra_timer_pointer_add: ADD R0,R0,R1, LSL #+2 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -347,12 +419,9 @@ _tx_misra_timer_pointer_add: SECTION `.text`:CODE:NOROOT(1) THUMB _tx_misra_user_timer_pointer_get: - ADDS R2,R0,#+8 - SUBS R2,R2,R0 - RSBS R2,R2,#+0 - ADD R0,R0,R2 - STR R0,[R1, #+0] - BX LR ;; return + SUBS R0,#8 + STR R0,[R1, #+0] + BX LR // return /**************************************************************************/ @@ -374,7 +443,7 @@ _tx_misra_thread_stack_check: CMP R4,#+0 BEQ.N ??_tx_misra_thread_stack_check_0 LDR R1,[R4, #+0] - LDR.N R2,??DataTable2 ;; 0x54485244 + LDR.N R2,??DataTable2 // 0x54485244 CMP R1,R2 BNE.N ??_tx_misra_thread_stack_check_0 LDR R1,[R4, #+8] @@ -412,7 +481,7 @@ _tx_misra_thread_stack_check: BL _tx_thread_interrupt_disable ??_tx_misra_thread_stack_check_0: BL _tx_thread_interrupt_restore - POP {R0,R4,R5,PC} ;; return + POP {R0,R4,R5,PC} // return #ifdef TX_ENABLE_EVENT_TRACE @@ -500,7 +569,7 @@ _tx_misra_trace_event_insert: LDR R0,[R0, #+0] STR R4,[R0, #+32] ??_tx_misra_trace_event_insert_0: - POP {R0,R4-R7,PC} ;; return + POP {R0,R4-R7,PC} // return SECTION `.text`:CODE:NOROOT(2) @@ -552,7 +621,7 @@ _tx_misra_trace_event_insert: THUMB _tx_misra_time_stamp_get: MOVS R0,#+0 - BX LR ;; return + BX LR // return #endif @@ -587,203 +656,7 @@ _tx_misra_time_stamp_get: THUMB _tx_misra_always_true: MOVS R0,#+1 - BX LR ;; return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_indirect_void_to_uchar_pointer_convert: - BX LR ;; return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_indirect_uchar_pointer_convert: - BX LR ;; return - - -/***********************************************************************************/ -/***********************************************************************************/ -/** */ -/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ -/** */ -/***********************************************************************************/ -/***********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_block_pool_to_uchar_pointer_convert: - BX LR ;; return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_block_pool_pointer_convert: - BX LR ;; return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_uchar_pointer_convert: - BX LR ;; return - - -/************************************************************************************/ -/************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************/ -/************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_block_pool_pointer_convert: - BX LR ;; return - - -/**************************************************************************************/ -/**************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************/ -/**************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_indirect_uchar_pointer_convert: - BX LR ;; return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_byte_pool_pointer_convert: - BX LR ;; return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_byte_pool_to_uchar_pointer_convert: - BX LR ;; return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_align_type_pointer_convert: - BX LR ;; return - - -/****************************************************************************************************/ -/****************************************************************************************************/ -/** */ -/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/****************************************************************************************************/ -/****************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: - BX LR ;; return - - -/**************************************************************************************************/ -/**************************************************************************************************/ -/** */ -/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************************/ -/**************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_event_flags_pointer_convert: - BX LR ;; return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_ulong_pointer_convert: - BX LR ;; return - - -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_mutex_pointer_convert: - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -798,192 +671,7 @@ _tx_misra_void_to_mutex_pointer_convert: THUMB _tx_misra_status_get: MOVS R0,#+0 - BX LR ;; return - - -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_queue_pointer_convert: - BX LR ;; return - - -/****************************************************************************************/ -/****************************************************************************************/ -/** */ -/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ -/** */ -/****************************************************************************************/ -/****************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_semaphore_pointer_convert: - BX LR ;; return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_void_pointer_convert: - BX LR ;; return - - -/*********************************************************************************/ -/*********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ -/** */ -/*********************************************************************************/ -/*********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_ulong_to_thread_pointer_convert: - BX LR ;; return - - -/***************************************************************************************************/ -/***************************************************************************************************/ -/** */ -/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ -/** */ -/***************************************************************************************************/ -/***************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_timer_indirect_to_void_pointer_convert: - BX LR ;; return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_const_char_to_char_pointer_convert: - BX LR ;; return - - -/**********************************************************************************/ -/**********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ -/** */ -/**********************************************************************************/ -/**********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_thread_pointer_convert: - BX LR ;; return - - -#ifdef TX_ENABLE_EVENT_TRACE - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_object_to_uchar_pointer_convert: - BX LR ;; return - - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_object_pointer_convert: - BX LR ;; return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_header_pointer_convert: - BX LR ;; return - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_entry_pointer_convert: - BX LR ;; return - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_entry_to_uchar_pointer_convert: - BX LR ;; return -#endif - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_char_to_uchar_pointer_convert: - BX LR ;; return + BX LR // return /***********************************************************************************************/ @@ -998,7 +686,7 @@ _tx_misra_char_to_uchar_pointer_convert: THUMB _tx_misra_ipsr_get: MRS R0, IPSR - BX LR ;; return + BX LR // return /***********************************************************************************************/ @@ -1013,7 +701,7 @@ _tx_misra_ipsr_get: THUMB _tx_misra_control_get: MRS R0, CONTROL - BX LR ;; return + BX LR // return /***********************************************************************************************/ @@ -1028,7 +716,7 @@ _tx_misra_control_get: THUMB _tx_misra_control_set: MSR CONTROL, R0 - BX LR ;; return + BX LR // return #ifdef __ARMVFP__ @@ -1044,9 +732,9 @@ _tx_misra_control_set: SECTION `.text`:CODE:NOROOT(2) THUMB _tx_misra_fpccr_get: - LDR r0, =0xE000EF34 ; Build FPCCR address - LDR r0, [r0] ; Load FPCCR value - BX LR ;; return + LDR r0, =0xE000EF34 // Build FPCCR address + LDR r0, [r0] // Load FPCCR value + BX LR // return /***********************************************************************************************/ @@ -1061,7 +749,7 @@ _tx_misra_fpccr_get: THUMB _tx_misra_vfp_touch: vmov.f32 s0, s0 - BX LR ;; return + BX LR // return #endif diff --git a/ports/cortex_m3/keil/example_build/ThreadX_Demo.uvopt b/ports/cortex_m3/keil/example_build/ThreadX_Demo.uvopt index 5fcedc851..703846828 100644 --- a/ports/cortex_m3/keil/example_build/ThreadX_Demo.uvopt +++ b/ports/cortex_m3/keil/example_build/ThreadX_Demo.uvopt @@ -10,7 +10,7 @@ *.s*; *.src; *.a* *.obj *.lib - *.txt; *.h; *.inc + *.txt; *.h; *.inc; *.md *.plm *.cpp 0 diff --git a/ports/cortex_m3/keil/example_build/ThreadX_Demo.uvproj b/ports/cortex_m3/keil/example_build/ThreadX_Demo.uvproj index 1d887f06f..1700c5e12 100644 --- a/ports/cortex_m3/keil/example_build/ThreadX_Demo.uvproj +++ b/ports/cortex_m3/keil/example_build/ThreadX_Demo.uvproj @@ -555,19 +555,4 @@ - - - - <Project Info> - - - - - - 0 - 1 - - - - diff --git a/ports/cortex_m3/keil/example_build/ThreadX_Library.uvopt b/ports/cortex_m3/keil/example_build/ThreadX_Library.uvopt index ac554f540..f85946182 100644 --- a/ports/cortex_m3/keil/example_build/ThreadX_Library.uvopt +++ b/ports/cortex_m3/keil/example_build/ThreadX_Library.uvopt @@ -10,7 +10,7 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc + *.txt; *.h; *.inc; *.md *.plm *.cpp 0 diff --git a/ports/cortex_m3/keil/example_build/ThreadX_Library.uvproj b/ports/cortex_m3/keil/example_build/ThreadX_Library.uvproj index 560ac2086..39e74b01a 100644 --- a/ports/cortex_m3/keil/example_build/ThreadX_Library.uvproj +++ b/ports/cortex_m3/keil/example_build/ThreadX_Library.uvproj @@ -1532,19 +1532,4 @@ - - - - <Project Info> - - - - - - 0 - 1 - - - - diff --git a/ports/cortex_m3/keil/inc/tx_port.h b/ports/cortex_m3/keil/inc/tx_port.h index d12b1ad96..59a1b36c7 100644 --- a/ports/cortex_m3/keil/inc/tx_port.h +++ b/ports/cortex_m3/keil/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/Keil */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -59,6 +59,9 @@ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -146,6 +149,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -707,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/Keil Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/Keil Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m55/ac6/CmakeLists.txt b/ports/cortex_m33/ac6/CMakeLists.txt similarity index 100% rename from ports/cortex_m55/ac6/CmakeLists.txt rename to ports/cortex_m33/ac6/CMakeLists.txt diff --git a/ports/cortex_m33/ac6/inc/tx_port.h b/ports/cortex_m33/ac6/inc/tx_port.h index aaa029954..90573b503 100644 --- a/ports/cortex_m33/ac6/inc/tx_port.h +++ b/ports/cortex_m33/ac6/inc/tx_port.h @@ -25,8 +25,8 @@ /* */ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ -/* tx_port.h Cortex-M33 */ -/* 6.1.11 */ +/* tx_port.h Cortex-M33/AC6 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -61,16 +61,21 @@ /* added symbol to enable */ /* stack error handler, */ /* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ +/* 10-15-2021 Scott Larson Modified comment(s), improved */ /* stack check error handling, */ /* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ +/* 01-31-2022 Scott Larson Modified comment(s), unified */ /* this file across compilers, */ /* fixed predefined macro, */ /* resulting in version 6.1.10 */ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -188,6 +193,12 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -524,7 +535,7 @@ ULONG _tx_misra_ipsr_get(VOID); #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) /* Initialize secure stacks for threads calling secure functions. */ extern void _tx_thread_secure_stack_initialize(void); -#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to @@ -637,7 +648,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33 Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/AC6 Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m33/ac6/src/tx_initialize_low_level.S b/ports/cortex_m33/ac6/src/tx_initialize_low_level.S new file mode 100644 index 000000000..a5e8e946c --- /dev/null +++ b/ports/cortex_m33/ac6/src/tx_initialize_low_level.S @@ -0,0 +1,278 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +SYSTEM_CLOCK = 6000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + +/* Setup the stack and heap areas. */ + +STACK_SIZE = 0x00000400 +HEAP_SIZE = 0x00000000 + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M33/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_initialize_low_level + .thumb_func +.type _tx_initialize_low_level, function +_tx_initialize_low_level: + + /* Disable interrupts during ThreadX initialization. */ + CPSID i + + /* Set base of available memory to end of non-initialised RAM area. */ + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit // Build first free address + ADD r1, r1, #4 // + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =__Vectors // Pickup address of vector table + STR r1, [r0, #0xD08] // Set vector table address + + /* Enable the cycle count register. */ + LDR r0, =0xE0001000 // Build address of DWT register + LDR r1, [r0] // Pickup the current value + ORR r1, r1, #1 // Set the CYCCNTENA bit + STR r1, [r0] // Enable the cycle count register + + /* Set system stack pointer from vector value. */ + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =__Vectors // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Configure SysTick. */ + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOV r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control + + /* Configure handler priorities. */ + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF + + /* Return to caller. */ + BX lr +// } + + +/* Define shells for each of the unused vectors. */ + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global __tx_BadHandler + .thumb_func +.type __tx_BadHandler, function +__tx_BadHandler: + B __tx_BadHandler + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global __tx_IntHandler + .thumb_func +.type __tx_IntHandler, function +__tx_IntHandler: +// VOID InterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + /* Do interrupt handler work here */ + /* .... */ +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0,lr} + BX LR +// } + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global SysTick_Handler + .thumb_func +.type SysTick_Handler, function +SysTick_Handler: +// VOID TimerInterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + BL _tx_timer_interrupt +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0,lr} + BX LR +// } + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global HardFault_Handler + .thumb_func +.type HardFault_Handler, function +HardFault_Handler: + B HardFault_Handler + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global UsageFault_Handler + .thumb_func +.type UsageFault_Handler, function +UsageFault_Handler: + CPSID i // Disable interrupts + // Check for stack limit fault + LDR r0, =0xE000ED28 // CFSR address + LDR r1,[r0] // Pick up CFSR + TST r1, #0x00100000 // Check for Stack Overflow +_unhandled_usage_loop: + BEQ _unhandled_usage_loop // If not stack overflow then loop + + // Handle stack overflow + STR r1, [r0] // Clear CFSR flag(s) + +#ifdef __ARM_PCS_VFP + LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address + LDR r1, [r0] // Load FPCCR + BIC r1, r1, #1 // Clear the lazy preservation active bit + STR r1, [r0] // Store the value +#endif + + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r0,[r0] // Pick up current thread pointer + PUSH {r0,lr} // Save LR (and r0 to maintain stack alignment) + BL _tx_thread_stack_error_handler // Call ThreadX/user handler + POP {r0,lr} // Restore LR and dummy reg + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + // Call the thread exit function to indicate the thread is no longer executing. + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, lr} // Recover LR +#endif + + MOV r1, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer + STR r1, [r0] // Clear current thread pointer + + // Return from UsageFault_Handler exception + LDR r0, =0xE000ED04 // Load ICSR + LDR r1, =0x10000000 // Set PENDSVSET bit + STR r1, [r0] // Store ICSR + DSB // Wait for memory access to complete + CPSIE i // Enable interrupts + BX lr // Return from exception + + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global __tx_NMIHandler + .thumb_func +.type __tx_NMIHandler, function +__tx_NMIHandler: + B __tx_NMIHandler + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global __tx_DBGHandler + .thumb_func +.type __tx_DBGHandler, function +__tx_DBGHandler: + B __tx_DBGHandler + + .end diff --git a/ports/cortex_m33/ac6/src/tx_misra.S b/ports/cortex_m33/ac6/src/tx_misra.S new file mode 100644 index 000000000..155512be4 --- /dev/null +++ b/ports/cortex_m33/ac6/src/tx_misra.S @@ -0,0 +1,719 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ThreadX MISRA Compliance */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + #define SHT_PROGBITS 0x1 + + .global __aeabi_memset + .global _tx_thread_current_ptr + .global _tx_thread_interrupt_disable + .global _tx_thread_interrupt_restore + .global _tx_thread_stack_analyze + .global _tx_thread_stack_error_handler + .global _tx_thread_system_state +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_trace_buffer_current_ptr + .global _tx_trace_buffer_end_ptr + .global _tx_trace_buffer_start_ptr + .global _tx_trace_event_enable_bits + .global _tx_trace_full_notify_function + .global _tx_trace_header_ptr +#endif + + .global _tx_misra_always_true + .global _tx_misra_block_pool_to_uchar_pointer_convert + .global _tx_misra_byte_pool_to_uchar_pointer_convert + .global _tx_misra_char_to_uchar_pointer_convert + .global _tx_misra_const_char_to_char_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_entry_to_uchar_pointer_convert +#endif + .global _tx_misra_indirect_void_to_uchar_pointer_convert + .global _tx_misra_memset + .global _tx_misra_message_copy +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_object_to_uchar_pointer_convert +#endif + .global _tx_misra_pointer_to_ulong_convert + .global _tx_misra_status_get + .global _tx_misra_thread_stack_check +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_time_stamp_get +#endif + .global _tx_misra_timer_indirect_to_void_pointer_convert + .global _tx_misra_timer_pointer_add + .global _tx_misra_timer_pointer_dif +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_trace_event_insert +#endif + .global _tx_misra_uchar_pointer_add + .global _tx_misra_uchar_pointer_dif + .global _tx_misra_uchar_pointer_sub + .global _tx_misra_uchar_to_align_type_pointer_convert + .global _tx_misra_uchar_to_block_pool_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_uchar_to_entry_pointer_convert + .global _tx_misra_uchar_to_header_pointer_convert +#endif + .global _tx_misra_uchar_to_indirect_byte_pool_pointer_convert + .global _tx_misra_uchar_to_indirect_uchar_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_uchar_to_object_pointer_convert +#endif + .global _tx_misra_uchar_to_void_pointer_convert + .global _tx_misra_ulong_pointer_add + .global _tx_misra_ulong_pointer_dif + .global _tx_misra_ulong_pointer_sub + .global _tx_misra_ulong_to_pointer_convert + .global _tx_misra_ulong_to_thread_pointer_convert + .global _tx_misra_user_timer_pointer_get + .global _tx_misra_void_to_block_pool_pointer_convert + .global _tx_misra_void_to_byte_pool_pointer_convert + .global _tx_misra_void_to_event_flags_pointer_convert + .global _tx_misra_void_to_indirect_uchar_pointer_convert + .global _tx_misra_void_to_mutex_pointer_convert + .global _tx_misra_void_to_queue_pointer_convert + .global _tx_misra_void_to_semaphore_pointer_convert + .global _tx_misra_void_to_thread_pointer_convert + .global _tx_misra_void_to_uchar_pointer_convert + .global _tx_misra_void_to_ulong_pointer_convert + .global _tx_misra_ipsr_get + .global _tx_misra_control_get + .global _tx_misra_control_set +#ifdef __ARM_FP + .global _tx_misra_fpccr_get + .global _tx_misra_vfp_touch +#endif + + .global _tx_misra_event_flags_group_not_used + .global _tx_misra_event_flags_set_notify_not_used + .global _tx_misra_queue_not_used + .global _tx_misra_queue_send_notify_not_used + .global _tx_misra_semaphore_not_used + .global _tx_misra_semaphore_put_notify_not_used + .global _tx_misra_thread_entry_exit_notify_not_used + .global _tx_misra_thread_not_used + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_memset(VOID *ptr, UINT value, UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .align 4 + .syntax unified + .thumb_func +_tx_misra_memset: + PUSH {R4,LR} + MOVS R4,R0 + MOVS R0,R2 + MOVS R2,R1 + MOVS R1,R0 + MOVS R0,R4 + BL __aeabi_memset + POP {R4,PC} // return + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_add(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_uchar_pointer_add: + ADD R0,R0,R1 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_sub(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_uchar_pointer_sub: + RSBS R1,R1,#+0 + ADD R0,R0,R1 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_uchar_pointer_dif(UCHAR *ptr1, UCHAR *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_uchar_pointer_dif: + SUBS R0,R0,R1 + BX LR // return + + +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ +/** */ +/** This single function serves all of the below prototypes. */ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** VOID _tx_misra_event_flags_group_not_used(TX_EVENT_FLAGS_GROUP *group_ptr); */ +/** VOID _tx_misra_event_flags_set_notify_not_used(VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); */ +/** VOID _tx_misra_queue_not_used(TX_QUEUE *queue_ptr); */ +/** VOID _tx_misra_queue_send_notify_not_used(VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); */ +/** VOID _tx_misra_semaphore_not_used(TX_SEMAPHORE *semaphore_ptr); */ +/** VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); */ +/** VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr); */ +/** VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)); */ +/** */ +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ + .text + .thumb_func +_tx_misra_pointer_to_ulong_convert: +_tx_misra_ulong_to_pointer_convert: +_tx_misra_indirect_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_indirect_uchar_pointer_convert: +_tx_misra_block_pool_to_uchar_pointer_convert: +_tx_misra_void_to_block_pool_pointer_convert: +_tx_misra_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_block_pool_pointer_convert: +_tx_misra_void_to_indirect_uchar_pointer_convert: +_tx_misra_void_to_byte_pool_pointer_convert: +_tx_misra_byte_pool_to_uchar_pointer_convert: +_tx_misra_uchar_to_align_type_pointer_convert: +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: +_tx_misra_void_to_event_flags_pointer_convert: +_tx_misra_void_to_ulong_pointer_convert: +_tx_misra_void_to_mutex_pointer_convert: +_tx_misra_void_to_queue_pointer_convert: +_tx_misra_void_to_semaphore_pointer_convert: +_tx_misra_uchar_to_void_pointer_convert: +_tx_misra_ulong_to_thread_pointer_convert: +_tx_misra_timer_indirect_to_void_pointer_convert: +_tx_misra_const_char_to_char_pointer_convert: +_tx_misra_void_to_thread_pointer_convert: +#ifdef TX_ENABLE_EVENT_TRACE +_tx_misra_object_to_uchar_pointer_convert: +_tx_misra_uchar_to_object_pointer_convert: +_tx_misra_uchar_to_header_pointer_convert: +_tx_misra_uchar_to_entry_pointer_convert: +_tx_misra_entry_to_uchar_pointer_convert: +#endif +_tx_misra_char_to_uchar_pointer_convert: +_tx_misra_event_flags_group_not_used: +_tx_misra_event_flags_set_notify_not_used: +_tx_misra_queue_not_used: +_tx_misra_queue_send_notify_not_used: +_tx_misra_semaphore_not_used: +_tx_misra_semaphore_put_notify_not_used: +_tx_misra_thread_entry_exit_notify_not_used: +_tx_misra_thread_not_used: + + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_add(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_ulong_pointer_add: + ADD R0,R0,R1, LSL #+2 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_sub(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_ulong_pointer_sub: + MVNS R2,#+3 + MULS R1,R2,R1 + ADD R0,R0,R1 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_ulong_pointer_dif(ULONG *ptr1, ULONG *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_ulong_pointer_dif: + SUBS R0,R0,R1 + ASRS R0,R0,#+2 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_message_copy(ULONG **source, ULONG **destination, */ +/** UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_message_copy: + PUSH {R4,R5} + LDR R3,[R0, #+0] + LDR R4,[R1, #+0] + LDR R5,[R3, #+0] + STR R5,[R4, #+0] + ADDS R4,R4,#+4 + ADDS R3,R3,#+4 + CMP R2,#+2 + BCC.N _tx_misra_message_copy_0 + SUBS R2,R2,#+1 + B.N _tx_misra_message_copy_1 +_tx_misra_message_copy_2: + LDR R5,[R3, #+0] + STR R5,[R4, #+0] + ADDS R4,R4,#+4 + ADDS R3,R3,#+4 + SUBS R2,R2,#+1 +_tx_misra_message_copy_1: + CMP R2,#+0 + BNE.N _tx_misra_message_copy_2 +_tx_misra_message_copy_0: + STR R3,[R0, #+0] + STR R4,[R1, #+0] + POP {R4,R5} + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_timer_pointer_dif(TX_TIMER_INTERNAL **ptr1, */ +/** TX_TIMER_INTERNAL **ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_timer_pointer_dif: + SUBS R0,R0,R1 + ASRS R0,R0,#+2 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** TX_TIMER_INTERNAL **_tx_misra_timer_pointer_add(TX_TIMER_INTERNAL */ +/** **ptr1, ULONG size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_timer_pointer_add: + ADD R0,R0,R1, LSL #+2 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL */ +/** *internal_timer, TX_TIMER **user_timer); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_user_timer_pointer_get: + SUBS R0,#8 + STR R0,[R1, #+0] + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, */ +/** VOID **highest_stack); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_thread_stack_check: + PUSH {R3-R5,LR} + MOVS R4,R0 + MOVS R5,R1 + BL _tx_thread_interrupt_disable + CMP R4,#+0 + BEQ.N _tx_misra_thread_stack_check_0 + LDR R1,[R4, #+0] + LDR R2,=0x54485244 + CMP R1,R2 + BNE.N _tx_misra_thread_stack_check_0 + LDR R1,[R4, #+8] + LDR R2,[R5, #+0] + CMP R1,R2 + BCS.N _tx_misra_thread_stack_check_1 + LDR R1,[R4, #+8] + STR R1,[R5, #+0] +_tx_misra_thread_stack_check_1: + LDR R1,[R4, #+12] + LDR R1,[R1, #+0] + CMP R1,#-269488145 + BNE.N _tx_misra_thread_stack_check_2 + LDR R1,[R4, #+16] + LDR R1,[R1, #+1] + CMP R1,#-269488145 + BNE.N _tx_misra_thread_stack_check_2 + LDR R1,[R5, #+0] + LDR R2,[R4, #+12] + CMP R1,R2 + BCS.N _tx_misra_thread_stack_check_3 +_tx_misra_thread_stack_check_2: + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_error_handler + BL _tx_thread_interrupt_disable +_tx_misra_thread_stack_check_3: + LDR R1,[R5, #+0] + LDR R1,[R1, #-4] + CMP R1,#-269488145 + BEQ.N _tx_misra_thread_stack_check_0 + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_analyze + BL _tx_thread_interrupt_disable +_tx_misra_thread_stack_check_0: + BL _tx_thread_interrupt_restore + POP {R0,R4,R5,PC} // return + +#ifdef TX_ENABLE_EVENT_TRACE + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_trace_event_insert(ULONG event_id, */ +/** VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, */ +/** ULONG info_field_4, ULONG filter, ULONG time_stamp); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_trace_event_insert: + PUSH {R3-R7,LR} + LDR.N R4,DataTable2_1 + LDR R4,[R4, #+0] + CMP R4,#+0 + BEQ.N _tx_misra_trace_event_insert_0 + LDR.N R5,DataTable2_2 + LDR R5,[R5, #+0] + LDR R6,[SP, #+28] + TST R5,R6 + BEQ.N _tx_misra_trace_event_insert_0 + LDR.N R5,DataTable2_3 + LDR R5,[R5, #+0] + LDR.N R6,DataTable2_4 + LDR R6,[R6, #+0] + CMP R5,#+0 + BNE.N _tx_misra_trace_event_insert_1 + LDR R5,[R6, #+44] + LDR R7,[R6, #+60] + LSLS R7,R7,#+16 + ORRS R7,R7,#0x80000000 + ORRS R5,R7,R5 + B.N _tx_misra_trace_event_insert_2 +_tx_misra_trace_event_insert_1: + CMP R5,#-252645136 + BCS.N _tx_misra_trace_event_insert_3 + MOVS R5,R6 + MOVS R6,#-1 + B.N _tx_misra_trace_event_insert_2 +_tx_misra_trace_event_insert_3: + MOVS R6,#-252645136 + MOVS R5,#+0 +_tx_misra_trace_event_insert_2: + STR R6,[R4, #+0] + STR R5,[R4, #+4] + STR R0,[R4, #+8] + LDR R0,[SP, #+32] + STR R0,[R4, #+12] + STR R1,[R4, #+16] + STR R2,[R4, #+20] + STR R3,[R4, #+24] + LDR R0,[SP, #+24] + STR R0,[R4, #+28] + ADDS R4,R4,#+32 + LDR.N R0,DataTable2_5 + LDR R0,[R0, #+0] + CMP R4,R0 + BCC.N _tx_misra_trace_event_insert_4 + LDR.N R0,DataTable2_6 + LDR R4,[R0, #+0] + LDR.N R0,DataTable2_1 + STR R4,[R0, #+0] + LDR.N R0,DataTable2_7 + LDR R0,[R0, #+0] + STR R4,[R0, #+32] + LDR.N R0,DataTable2_8 + LDR R0,[R0, #+0] + CMP R0,#+0 + BEQ.N _tx_misra_trace_event_insert_0 + LDR.N R0,DataTable2_7 + LDR R0,[R0, #+0] + LDR.N R1,DataTable2_8 + LDR R1,[R1, #+0] + BLX R1 + B.N _tx_misra_trace_event_insert_0 +_tx_misra_trace_event_insert_4: + LDR.N R0,DataTable2_1 + STR R4,[R0, #+0] + LDR.N R0,DataTable2_7 + LDR R0,[R0, #+0] + STR R4,[R0, #+32] +_tx_misra_trace_event_insert_0: + POP {R0,R4-R7,PC} // return + + + .data +DataTable2_1: + .word _tx_trace_buffer_current_ptr + + .data +DataTable2_2: + .word _tx_trace_event_enable_bits + + .data +DataTable2_5: + .word _tx_trace_buffer_end_ptr + + .data +DataTable2_6: + .word _tx_trace_buffer_start_ptr + + .data +DataTable2_7: + .word _tx_trace_header_ptr + + .data +DataTable2_8: + .word _tx_trace_full_notify_function + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_time_stamp_get(VOID); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_time_stamp_get: + MOVS R0,#+0 + BX LR // return + +#endif + + .data +DataTable2_3: + .word _tx_thread_system_state + + .data +DataTable2_4: + .word _tx_thread_current_ptr + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_always_true(void); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_always_true: + MOVS R0,#+1 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_status_get(UINT status); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_status_get: + MOVS R0,#+0 + BX LR // return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_ipsr_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + .text + .thumb_func +_tx_misra_ipsr_get: + MRS R0, IPSR + BX LR // return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_control_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + .text + .thumb_func +_tx_misra_control_get: + MRS R0, CONTROL + BX LR // return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** void _tx_misra_control_set(ULONG value); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + .text + .thumb_func +_tx_misra_control_set: + MSR CONTROL, R0 + BX LR // return + + +#ifdef __ARM_FP + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_fpccr_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + .text + .thumb_func +_tx_misra_fpccr_get: + LDR r0, =0xE000EF34 // Build FPCCR address + LDR r0, [r0] // Load FPCCR value + BX LR // return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** void _tx_misra_vfp_touch(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + .text + .thumb_func +_tx_misra_vfp_touch: + vmov.f32 s0, s0 + BX LR // return + +#endif + + + .data + .word 0 diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c b/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c index d41bdbbe4..099ae737e 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c @@ -219,7 +219,7 @@ TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; UCHAR *stack_mem; -INT secure_context_index; +INT secure_context_index; status = TX_SUCCESS; @@ -241,7 +241,6 @@ INT secure_context_index; else { - TX_DISABLE /* Allocate free index for secure stack info. */ diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_initialize.S index 4baf378a6..a96e30abb 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_initialize.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M33/AC6 */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -49,13 +49,17 @@ /* */ /* CALLED BY */ /* */ -/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */ +/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ /* RELEASE HISTORY */ /* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports/cortex_m85/ac6/CmakeLists.txt b/ports/cortex_m33/gnu/CMakeLists.txt similarity index 100% rename from ports/cortex_m85/ac6/CmakeLists.txt rename to ports/cortex_m33/gnu/CMakeLists.txt diff --git a/ports/cortex_m33/gnu/inc/tx_port.h b/ports/cortex_m33/gnu/inc/tx_port.h index aaa029954..24c5adf21 100644 --- a/ports/cortex_m33/gnu/inc/tx_port.h +++ b/ports/cortex_m33/gnu/inc/tx_port.h @@ -25,8 +25,8 @@ /* */ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ -/* tx_port.h Cortex-M33 */ -/* 6.1.11 */ +/* tx_port.h Cortex-M33/GNU */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -61,16 +61,21 @@ /* added symbol to enable */ /* stack error handler, */ /* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ +/* 10-15-2021 Scott Larson Modified comment(s), improved */ /* stack check error handling, */ /* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ +/* 01-31-2022 Scott Larson Modified comment(s), unified */ /* this file across compilers, */ /* fixed predefined macro, */ /* resulting in version 6.1.10 */ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -188,6 +193,12 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -524,7 +535,7 @@ ULONG _tx_misra_ipsr_get(VOID); #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) /* Initialize secure stacks for threads calling secure functions. */ extern void _tx_thread_secure_stack_initialize(void); -#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to @@ -637,7 +648,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33 Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/GNU Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m33/gnu/src/tx_misra.S b/ports/cortex_m33/gnu/src/tx_misra.S new file mode 100644 index 000000000..155512be4 --- /dev/null +++ b/ports/cortex_m33/gnu/src/tx_misra.S @@ -0,0 +1,719 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ThreadX MISRA Compliance */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + #define SHT_PROGBITS 0x1 + + .global __aeabi_memset + .global _tx_thread_current_ptr + .global _tx_thread_interrupt_disable + .global _tx_thread_interrupt_restore + .global _tx_thread_stack_analyze + .global _tx_thread_stack_error_handler + .global _tx_thread_system_state +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_trace_buffer_current_ptr + .global _tx_trace_buffer_end_ptr + .global _tx_trace_buffer_start_ptr + .global _tx_trace_event_enable_bits + .global _tx_trace_full_notify_function + .global _tx_trace_header_ptr +#endif + + .global _tx_misra_always_true + .global _tx_misra_block_pool_to_uchar_pointer_convert + .global _tx_misra_byte_pool_to_uchar_pointer_convert + .global _tx_misra_char_to_uchar_pointer_convert + .global _tx_misra_const_char_to_char_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_entry_to_uchar_pointer_convert +#endif + .global _tx_misra_indirect_void_to_uchar_pointer_convert + .global _tx_misra_memset + .global _tx_misra_message_copy +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_object_to_uchar_pointer_convert +#endif + .global _tx_misra_pointer_to_ulong_convert + .global _tx_misra_status_get + .global _tx_misra_thread_stack_check +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_time_stamp_get +#endif + .global _tx_misra_timer_indirect_to_void_pointer_convert + .global _tx_misra_timer_pointer_add + .global _tx_misra_timer_pointer_dif +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_trace_event_insert +#endif + .global _tx_misra_uchar_pointer_add + .global _tx_misra_uchar_pointer_dif + .global _tx_misra_uchar_pointer_sub + .global _tx_misra_uchar_to_align_type_pointer_convert + .global _tx_misra_uchar_to_block_pool_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_uchar_to_entry_pointer_convert + .global _tx_misra_uchar_to_header_pointer_convert +#endif + .global _tx_misra_uchar_to_indirect_byte_pool_pointer_convert + .global _tx_misra_uchar_to_indirect_uchar_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + .global _tx_misra_uchar_to_object_pointer_convert +#endif + .global _tx_misra_uchar_to_void_pointer_convert + .global _tx_misra_ulong_pointer_add + .global _tx_misra_ulong_pointer_dif + .global _tx_misra_ulong_pointer_sub + .global _tx_misra_ulong_to_pointer_convert + .global _tx_misra_ulong_to_thread_pointer_convert + .global _tx_misra_user_timer_pointer_get + .global _tx_misra_void_to_block_pool_pointer_convert + .global _tx_misra_void_to_byte_pool_pointer_convert + .global _tx_misra_void_to_event_flags_pointer_convert + .global _tx_misra_void_to_indirect_uchar_pointer_convert + .global _tx_misra_void_to_mutex_pointer_convert + .global _tx_misra_void_to_queue_pointer_convert + .global _tx_misra_void_to_semaphore_pointer_convert + .global _tx_misra_void_to_thread_pointer_convert + .global _tx_misra_void_to_uchar_pointer_convert + .global _tx_misra_void_to_ulong_pointer_convert + .global _tx_misra_ipsr_get + .global _tx_misra_control_get + .global _tx_misra_control_set +#ifdef __ARM_FP + .global _tx_misra_fpccr_get + .global _tx_misra_vfp_touch +#endif + + .global _tx_misra_event_flags_group_not_used + .global _tx_misra_event_flags_set_notify_not_used + .global _tx_misra_queue_not_used + .global _tx_misra_queue_send_notify_not_used + .global _tx_misra_semaphore_not_used + .global _tx_misra_semaphore_put_notify_not_used + .global _tx_misra_thread_entry_exit_notify_not_used + .global _tx_misra_thread_not_used + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_memset(VOID *ptr, UINT value, UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .align 4 + .syntax unified + .thumb_func +_tx_misra_memset: + PUSH {R4,LR} + MOVS R4,R0 + MOVS R0,R2 + MOVS R2,R1 + MOVS R1,R0 + MOVS R0,R4 + BL __aeabi_memset + POP {R4,PC} // return + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_add(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_uchar_pointer_add: + ADD R0,R0,R1 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_sub(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_uchar_pointer_sub: + RSBS R1,R1,#+0 + ADD R0,R0,R1 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_uchar_pointer_dif(UCHAR *ptr1, UCHAR *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_uchar_pointer_dif: + SUBS R0,R0,R1 + BX LR // return + + +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ +/** */ +/** This single function serves all of the below prototypes. */ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** VOID _tx_misra_event_flags_group_not_used(TX_EVENT_FLAGS_GROUP *group_ptr); */ +/** VOID _tx_misra_event_flags_set_notify_not_used(VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); */ +/** VOID _tx_misra_queue_not_used(TX_QUEUE *queue_ptr); */ +/** VOID _tx_misra_queue_send_notify_not_used(VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); */ +/** VOID _tx_misra_semaphore_not_used(TX_SEMAPHORE *semaphore_ptr); */ +/** VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); */ +/** VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr); */ +/** VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)); */ +/** */ +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ + .text + .thumb_func +_tx_misra_pointer_to_ulong_convert: +_tx_misra_ulong_to_pointer_convert: +_tx_misra_indirect_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_indirect_uchar_pointer_convert: +_tx_misra_block_pool_to_uchar_pointer_convert: +_tx_misra_void_to_block_pool_pointer_convert: +_tx_misra_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_block_pool_pointer_convert: +_tx_misra_void_to_indirect_uchar_pointer_convert: +_tx_misra_void_to_byte_pool_pointer_convert: +_tx_misra_byte_pool_to_uchar_pointer_convert: +_tx_misra_uchar_to_align_type_pointer_convert: +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: +_tx_misra_void_to_event_flags_pointer_convert: +_tx_misra_void_to_ulong_pointer_convert: +_tx_misra_void_to_mutex_pointer_convert: +_tx_misra_void_to_queue_pointer_convert: +_tx_misra_void_to_semaphore_pointer_convert: +_tx_misra_uchar_to_void_pointer_convert: +_tx_misra_ulong_to_thread_pointer_convert: +_tx_misra_timer_indirect_to_void_pointer_convert: +_tx_misra_const_char_to_char_pointer_convert: +_tx_misra_void_to_thread_pointer_convert: +#ifdef TX_ENABLE_EVENT_TRACE +_tx_misra_object_to_uchar_pointer_convert: +_tx_misra_uchar_to_object_pointer_convert: +_tx_misra_uchar_to_header_pointer_convert: +_tx_misra_uchar_to_entry_pointer_convert: +_tx_misra_entry_to_uchar_pointer_convert: +#endif +_tx_misra_char_to_uchar_pointer_convert: +_tx_misra_event_flags_group_not_used: +_tx_misra_event_flags_set_notify_not_used: +_tx_misra_queue_not_used: +_tx_misra_queue_send_notify_not_used: +_tx_misra_semaphore_not_used: +_tx_misra_semaphore_put_notify_not_used: +_tx_misra_thread_entry_exit_notify_not_used: +_tx_misra_thread_not_used: + + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_add(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_ulong_pointer_add: + ADD R0,R0,R1, LSL #+2 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_sub(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_ulong_pointer_sub: + MVNS R2,#+3 + MULS R1,R2,R1 + ADD R0,R0,R1 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_ulong_pointer_dif(ULONG *ptr1, ULONG *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_ulong_pointer_dif: + SUBS R0,R0,R1 + ASRS R0,R0,#+2 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_message_copy(ULONG **source, ULONG **destination, */ +/** UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_message_copy: + PUSH {R4,R5} + LDR R3,[R0, #+0] + LDR R4,[R1, #+0] + LDR R5,[R3, #+0] + STR R5,[R4, #+0] + ADDS R4,R4,#+4 + ADDS R3,R3,#+4 + CMP R2,#+2 + BCC.N _tx_misra_message_copy_0 + SUBS R2,R2,#+1 + B.N _tx_misra_message_copy_1 +_tx_misra_message_copy_2: + LDR R5,[R3, #+0] + STR R5,[R4, #+0] + ADDS R4,R4,#+4 + ADDS R3,R3,#+4 + SUBS R2,R2,#+1 +_tx_misra_message_copy_1: + CMP R2,#+0 + BNE.N _tx_misra_message_copy_2 +_tx_misra_message_copy_0: + STR R3,[R0, #+0] + STR R4,[R1, #+0] + POP {R4,R5} + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_timer_pointer_dif(TX_TIMER_INTERNAL **ptr1, */ +/** TX_TIMER_INTERNAL **ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_timer_pointer_dif: + SUBS R0,R0,R1 + ASRS R0,R0,#+2 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** TX_TIMER_INTERNAL **_tx_misra_timer_pointer_add(TX_TIMER_INTERNAL */ +/** **ptr1, ULONG size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_timer_pointer_add: + ADD R0,R0,R1, LSL #+2 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL */ +/** *internal_timer, TX_TIMER **user_timer); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_user_timer_pointer_get: + SUBS R0,#8 + STR R0,[R1, #+0] + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, */ +/** VOID **highest_stack); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_thread_stack_check: + PUSH {R3-R5,LR} + MOVS R4,R0 + MOVS R5,R1 + BL _tx_thread_interrupt_disable + CMP R4,#+0 + BEQ.N _tx_misra_thread_stack_check_0 + LDR R1,[R4, #+0] + LDR R2,=0x54485244 + CMP R1,R2 + BNE.N _tx_misra_thread_stack_check_0 + LDR R1,[R4, #+8] + LDR R2,[R5, #+0] + CMP R1,R2 + BCS.N _tx_misra_thread_stack_check_1 + LDR R1,[R4, #+8] + STR R1,[R5, #+0] +_tx_misra_thread_stack_check_1: + LDR R1,[R4, #+12] + LDR R1,[R1, #+0] + CMP R1,#-269488145 + BNE.N _tx_misra_thread_stack_check_2 + LDR R1,[R4, #+16] + LDR R1,[R1, #+1] + CMP R1,#-269488145 + BNE.N _tx_misra_thread_stack_check_2 + LDR R1,[R5, #+0] + LDR R2,[R4, #+12] + CMP R1,R2 + BCS.N _tx_misra_thread_stack_check_3 +_tx_misra_thread_stack_check_2: + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_error_handler + BL _tx_thread_interrupt_disable +_tx_misra_thread_stack_check_3: + LDR R1,[R5, #+0] + LDR R1,[R1, #-4] + CMP R1,#-269488145 + BEQ.N _tx_misra_thread_stack_check_0 + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_analyze + BL _tx_thread_interrupt_disable +_tx_misra_thread_stack_check_0: + BL _tx_thread_interrupt_restore + POP {R0,R4,R5,PC} // return + +#ifdef TX_ENABLE_EVENT_TRACE + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_trace_event_insert(ULONG event_id, */ +/** VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, */ +/** ULONG info_field_4, ULONG filter, ULONG time_stamp); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_trace_event_insert: + PUSH {R3-R7,LR} + LDR.N R4,DataTable2_1 + LDR R4,[R4, #+0] + CMP R4,#+0 + BEQ.N _tx_misra_trace_event_insert_0 + LDR.N R5,DataTable2_2 + LDR R5,[R5, #+0] + LDR R6,[SP, #+28] + TST R5,R6 + BEQ.N _tx_misra_trace_event_insert_0 + LDR.N R5,DataTable2_3 + LDR R5,[R5, #+0] + LDR.N R6,DataTable2_4 + LDR R6,[R6, #+0] + CMP R5,#+0 + BNE.N _tx_misra_trace_event_insert_1 + LDR R5,[R6, #+44] + LDR R7,[R6, #+60] + LSLS R7,R7,#+16 + ORRS R7,R7,#0x80000000 + ORRS R5,R7,R5 + B.N _tx_misra_trace_event_insert_2 +_tx_misra_trace_event_insert_1: + CMP R5,#-252645136 + BCS.N _tx_misra_trace_event_insert_3 + MOVS R5,R6 + MOVS R6,#-1 + B.N _tx_misra_trace_event_insert_2 +_tx_misra_trace_event_insert_3: + MOVS R6,#-252645136 + MOVS R5,#+0 +_tx_misra_trace_event_insert_2: + STR R6,[R4, #+0] + STR R5,[R4, #+4] + STR R0,[R4, #+8] + LDR R0,[SP, #+32] + STR R0,[R4, #+12] + STR R1,[R4, #+16] + STR R2,[R4, #+20] + STR R3,[R4, #+24] + LDR R0,[SP, #+24] + STR R0,[R4, #+28] + ADDS R4,R4,#+32 + LDR.N R0,DataTable2_5 + LDR R0,[R0, #+0] + CMP R4,R0 + BCC.N _tx_misra_trace_event_insert_4 + LDR.N R0,DataTable2_6 + LDR R4,[R0, #+0] + LDR.N R0,DataTable2_1 + STR R4,[R0, #+0] + LDR.N R0,DataTable2_7 + LDR R0,[R0, #+0] + STR R4,[R0, #+32] + LDR.N R0,DataTable2_8 + LDR R0,[R0, #+0] + CMP R0,#+0 + BEQ.N _tx_misra_trace_event_insert_0 + LDR.N R0,DataTable2_7 + LDR R0,[R0, #+0] + LDR.N R1,DataTable2_8 + LDR R1,[R1, #+0] + BLX R1 + B.N _tx_misra_trace_event_insert_0 +_tx_misra_trace_event_insert_4: + LDR.N R0,DataTable2_1 + STR R4,[R0, #+0] + LDR.N R0,DataTable2_7 + LDR R0,[R0, #+0] + STR R4,[R0, #+32] +_tx_misra_trace_event_insert_0: + POP {R0,R4-R7,PC} // return + + + .data +DataTable2_1: + .word _tx_trace_buffer_current_ptr + + .data +DataTable2_2: + .word _tx_trace_event_enable_bits + + .data +DataTable2_5: + .word _tx_trace_buffer_end_ptr + + .data +DataTable2_6: + .word _tx_trace_buffer_start_ptr + + .data +DataTable2_7: + .word _tx_trace_header_ptr + + .data +DataTable2_8: + .word _tx_trace_full_notify_function + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_time_stamp_get(VOID); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_time_stamp_get: + MOVS R0,#+0 + BX LR // return + +#endif + + .data +DataTable2_3: + .word _tx_thread_system_state + + .data +DataTable2_4: + .word _tx_thread_current_ptr + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_always_true(void); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_always_true: + MOVS R0,#+1 + BX LR // return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_status_get(UINT status); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .thumb_func +_tx_misra_status_get: + MOVS R0,#+0 + BX LR // return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_ipsr_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + .text + .thumb_func +_tx_misra_ipsr_get: + MRS R0, IPSR + BX LR // return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_control_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + .text + .thumb_func +_tx_misra_control_get: + MRS R0, CONTROL + BX LR // return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** void _tx_misra_control_set(ULONG value); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + .text + .thumb_func +_tx_misra_control_set: + MSR CONTROL, R0 + BX LR // return + + +#ifdef __ARM_FP + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_fpccr_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + .text + .thumb_func +_tx_misra_fpccr_get: + LDR r0, =0xE000EF34 // Build FPCCR address + LDR r0, [r0] // Load FPCCR value + BX LR // return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** void _tx_misra_vfp_touch(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + .text + .thumb_func +_tx_misra_vfp_touch: + vmov.f32 s0, s0 + BX LR // return + +#endif + + + .data + .word 0 diff --git a/ports/cortex_m33/gnu/src/tx_thread_secure_stack.c b/ports/cortex_m33/gnu/src/tx_thread_secure_stack.c index 0b0640985..13bfc29a1 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_secure_stack.c +++ b/ports/cortex_m33/gnu/src/tx_thread_secure_stack.c @@ -167,7 +167,7 @@ INT index; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_allocate Cortex-M33/GNU */ -/* 6.1.10 */ +/* 6.1.11a */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -207,11 +207,15 @@ INT index; /* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ /* secure stack allocation, */ /* resulting in version 6.1.10 */ +/* 05-02-2022 Scott Larson Modified comment(s), added */ +/* TX_INTERRUPT_SAVE_AREA, */ +/* resulting in version 6.1.11a*/ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; UCHAR *stack_mem; diff --git a/ports/cortex_m33/gnu/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m33/gnu/src/tx_thread_secure_stack_initialize.S index 9e9642fcb..a9f899f66 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m33/gnu/src/tx_thread_secure_stack_initialize.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M33/GNU */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -49,13 +49,17 @@ /* */ /* CALLED BY */ /* */ -/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */ +/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ /* RELEASE HISTORY */ /* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports/cortex_m33/iar/inc/tx_port.h b/ports/cortex_m33/iar/inc/tx_port.h index aaa029954..05fc5a6bd 100644 --- a/ports/cortex_m33/iar/inc/tx_port.h +++ b/ports/cortex_m33/iar/inc/tx_port.h @@ -25,8 +25,8 @@ /* */ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ -/* tx_port.h Cortex-M33 */ -/* 6.1.11 */ +/* tx_port.h Cortex-M33/IAR */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -61,16 +61,21 @@ /* added symbol to enable */ /* stack error handler, */ /* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ +/* 10-15-2021 Scott Larson Modified comment(s), improved */ /* stack check error handling, */ /* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ +/* 01-31-2022 Scott Larson Modified comment(s), unified */ /* this file across compilers, */ /* fixed predefined macro, */ /* resulting in version 6.1.10 */ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -188,6 +193,12 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -524,7 +535,7 @@ ULONG _tx_misra_ipsr_get(VOID); #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) /* Initialize secure stacks for threads calling secure functions. */ extern void _tx_thread_secure_stack_initialize(void); -#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to @@ -637,7 +648,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33 Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/IAR Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m33/iar/src/tx_misra.s b/ports/cortex_m33/iar/src/tx_misra.s index acb85cc9b..c81c3e5cc 100644 --- a/ports/cortex_m33/iar/src/tx_misra.s +++ b/ports/cortex_m33/iar/src/tx_misra.s @@ -96,6 +96,22 @@ PUBLIC _tx_misra_void_to_uchar_pointer_convert PUBLIC _tx_misra_void_to_ulong_pointer_convert PUBLIC _tx_misra_ipsr_get + PUBLIC _tx_misra_control_get + PUBLIC _tx_misra_control_set +#ifdef __ARMVFP__ + PUBLIC _tx_misra_fpccr_get + PUBLIC _tx_misra_vfp_touch +#endif + + PUBLIC _tx_misra_event_flags_group_not_used + PUBLIC _tx_misra_event_flags_set_notify_not_used + PUBLIC _tx_misra_queue_not_used + PUBLIC _tx_misra_queue_send_notify_not_used + PUBLIC _tx_misra_semaphore_not_used + PUBLIC _tx_misra_semaphore_put_notify_not_used + PUBLIC _tx_misra_thread_entry_exit_notify_not_used + PUBLIC _tx_misra_thread_not_used + PUBLIC _tx_version_id @@ -109,7 +125,7 @@ _tx_version_id: DC8 45H, 78H, 70H, 72H, 65H, 73H, 73H, 20H DC8 4CH, 6FH, 67H, 69H, 63H, 20H, 49H, 6EH DC8 63H, 2EH, 20H, 2AH, 20H, 54H, 68H, 72H - DC8 65H, 61H, 64H, 58H, 20H, 36H, 2EH, 30H + DC8 65H, 61H, 64H, 58H, 20H, 36H, 2EH, 31H DC8 20H, 4DH, 49H, 53H, 52H, 41H, 20H, 43H DC8 20H, 43H, 6FH, 6DH, 70H, 6CH, 69H, 61H DC8 6EH, 74H, 20H, 2AH, 0 @@ -133,7 +149,7 @@ _tx_misra_memset: MOVS R1,R0 MOVS R0,R4 BL __aeabi_memset - POP {R4,PC} ;; return + POP {R4,PC} // return /**************************************************************************/ /**************************************************************************/ @@ -147,7 +163,7 @@ _tx_misra_memset: THUMB _tx_misra_uchar_pointer_add: ADD R0,R0,R1 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -163,7 +179,7 @@ _tx_misra_uchar_pointer_add: _tx_misra_uchar_pointer_sub: RSBS R1,R1,#+0 ADD R0,R0,R1 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -178,21 +194,97 @@ _tx_misra_uchar_pointer_sub: THUMB _tx_misra_uchar_pointer_dif: SUBS R0,R0,R1 - BX LR ;; return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - + BX LR // return + + +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ +/** */ +/** This single function serves all of the below prototypes. */ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** VOID _tx_misra_event_flags_group_not_used(TX_EVENT_FLAGS_GROUP *group_ptr); */ +/** VOID _tx_misra_event_flags_set_notify_not_used(VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); */ +/** VOID _tx_misra_queue_not_used(TX_QUEUE *queue_ptr); */ +/** VOID _tx_misra_queue_send_notify_not_used(VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); */ +/** VOID _tx_misra_semaphore_not_used(TX_SEMAPHORE *semaphore_ptr); */ +/** VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); */ +/** VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr); */ +/** VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)); */ +/** */ +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ SECTION `.text`:CODE:NOROOT(1) THUMB _tx_misra_pointer_to_ulong_convert: - BX LR ;; return +_tx_misra_ulong_to_pointer_convert: +_tx_misra_indirect_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_indirect_uchar_pointer_convert: +_tx_misra_block_pool_to_uchar_pointer_convert: +_tx_misra_void_to_block_pool_pointer_convert: +_tx_misra_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_block_pool_pointer_convert: +_tx_misra_void_to_indirect_uchar_pointer_convert: +_tx_misra_void_to_byte_pool_pointer_convert: +_tx_misra_byte_pool_to_uchar_pointer_convert: +_tx_misra_uchar_to_align_type_pointer_convert: +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: +_tx_misra_void_to_event_flags_pointer_convert: +_tx_misra_void_to_ulong_pointer_convert: +_tx_misra_void_to_mutex_pointer_convert: +_tx_misra_void_to_queue_pointer_convert: +_tx_misra_void_to_semaphore_pointer_convert: +_tx_misra_uchar_to_void_pointer_convert: +_tx_misra_ulong_to_thread_pointer_convert: +_tx_misra_timer_indirect_to_void_pointer_convert: +_tx_misra_const_char_to_char_pointer_convert: +_tx_misra_void_to_thread_pointer_convert: +#ifdef TX_ENABLE_EVENT_TRACE +_tx_misra_object_to_uchar_pointer_convert: +_tx_misra_uchar_to_object_pointer_convert: +_tx_misra_uchar_to_header_pointer_convert: +_tx_misra_uchar_to_entry_pointer_convert: +_tx_misra_entry_to_uchar_pointer_convert: +#endif +_tx_misra_char_to_uchar_pointer_convert: +_tx_misra_event_flags_group_not_used: +_tx_misra_event_flags_set_notify_not_used: +_tx_misra_queue_not_used: +_tx_misra_queue_send_notify_not_used: +_tx_misra_semaphore_not_used: +_tx_misra_semaphore_put_notify_not_used: +_tx_misra_thread_entry_exit_notify_not_used: +_tx_misra_thread_not_used: + + BX LR // return /**************************************************************************/ @@ -207,7 +299,7 @@ _tx_misra_pointer_to_ulong_convert: THUMB _tx_misra_ulong_pointer_add: ADD R0,R0,R1, LSL #+2 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -224,7 +316,7 @@ _tx_misra_ulong_pointer_sub: MVNS R2,#+3 MULS R1,R2,R1 ADD R0,R0,R1 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -240,21 +332,7 @@ _tx_misra_ulong_pointer_sub: _tx_misra_ulong_pointer_dif: SUBS R0,R0,R1 ASRS R0,R0,#+2 - BX LR ;; return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_ulong_to_pointer_convert: - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -293,7 +371,7 @@ _tx_misra_message_copy: STR R3,[R0, #+0] STR R4,[R1, #+0] POP {R4,R5} - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -310,7 +388,7 @@ _tx_misra_message_copy: _tx_misra_timer_pointer_dif: SUBS R0,R0,R1 ASRS R0,R0,#+2 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -326,7 +404,7 @@ _tx_misra_timer_pointer_dif: THUMB _tx_misra_timer_pointer_add: ADD R0,R0,R1, LSL #+2 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -341,12 +419,9 @@ _tx_misra_timer_pointer_add: SECTION `.text`:CODE:NOROOT(1) THUMB _tx_misra_user_timer_pointer_get: - ADDS R2,R0,#+8 - SUBS R2,R2,R0 - RSBS R2,R2,#+0 - ADD R0,R0,R2 - STR R0,[R1, #+0] - BX LR ;; return + SUBS R0,#8 + STR R0,[R1, #+0] + BX LR // return /**************************************************************************/ @@ -368,7 +443,7 @@ _tx_misra_thread_stack_check: CMP R4,#+0 BEQ.N ??_tx_misra_thread_stack_check_0 LDR R1,[R4, #+0] - LDR.N R2,??DataTable2 ;; 0x54485244 + LDR.N R2,??DataTable2 // 0x54485244 CMP R1,R2 BNE.N ??_tx_misra_thread_stack_check_0 LDR R1,[R4, #+8] @@ -406,7 +481,7 @@ _tx_misra_thread_stack_check: BL _tx_thread_interrupt_disable ??_tx_misra_thread_stack_check_0: BL _tx_thread_interrupt_restore - POP {R0,R4,R5,PC} ;; return + POP {R0,R4,R5,PC} // return #ifdef TX_ENABLE_EVENT_TRACE @@ -494,7 +569,7 @@ _tx_misra_trace_event_insert: LDR R0,[R0, #+0] STR R4,[R0, #+32] ??_tx_misra_trace_event_insert_0: - POP {R0,R4-R7,PC} ;; return + POP {R0,R4-R7,PC} // return SECTION `.text`:CODE:NOROOT(2) @@ -546,7 +621,7 @@ _tx_misra_trace_event_insert: THUMB _tx_misra_time_stamp_get: MOVS R0,#+0 - BX LR ;; return + BX LR // return #endif @@ -581,203 +656,7 @@ _tx_misra_time_stamp_get: THUMB _tx_misra_always_true: MOVS R0,#+1 - BX LR ;; return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_indirect_void_to_uchar_pointer_convert: - BX LR ;; return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_indirect_uchar_pointer_convert: - BX LR ;; return - - -/***********************************************************************************/ -/***********************************************************************************/ -/** */ -/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ -/** */ -/***********************************************************************************/ -/***********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_block_pool_to_uchar_pointer_convert: - BX LR ;; return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_block_pool_pointer_convert: - BX LR ;; return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_uchar_pointer_convert: - BX LR ;; return - - -/************************************************************************************/ -/************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************/ -/************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_block_pool_pointer_convert: - BX LR ;; return - - -/**************************************************************************************/ -/**************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************/ -/**************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_indirect_uchar_pointer_convert: - BX LR ;; return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_byte_pool_pointer_convert: - BX LR ;; return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_byte_pool_to_uchar_pointer_convert: - BX LR ;; return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_align_type_pointer_convert: - BX LR ;; return - - -/****************************************************************************************************/ -/****************************************************************************************************/ -/** */ -/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/****************************************************************************************************/ -/****************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: - BX LR ;; return - - -/**************************************************************************************************/ -/**************************************************************************************************/ -/** */ -/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************************/ -/**************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_event_flags_pointer_convert: - BX LR ;; return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_ulong_pointer_convert: - BX LR ;; return - - -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_mutex_pointer_convert: - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -792,209 +671,89 @@ _tx_misra_void_to_mutex_pointer_convert: THUMB _tx_misra_status_get: MOVS R0,#+0 - BX LR ;; return - + BX LR // return -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_queue_pointer_convert: - BX LR ;; return - - -/****************************************************************************************/ -/****************************************************************************************/ -/** */ -/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ -/** */ -/****************************************************************************************/ -/****************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_semaphore_pointer_convert: - BX LR ;; return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_void_pointer_convert: - BX LR ;; return - - -/*********************************************************************************/ -/*********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ -/** */ -/*********************************************************************************/ -/*********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_ulong_to_thread_pointer_convert: - BX LR ;; return - - -/***************************************************************************************************/ -/***************************************************************************************************/ -/** */ -/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ -/** */ -/***************************************************************************************************/ -/***************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_timer_indirect_to_void_pointer_convert: - BX LR ;; return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_const_char_to_char_pointer_convert: - BX LR ;; return - - -/**********************************************************************************/ -/**********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ -/** */ -/**********************************************************************************/ -/**********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_thread_pointer_convert: - BX LR ;; return - - -#ifdef TX_ENABLE_EVENT_TRACE - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_object_to_uchar_pointer_convert: - BX LR ;; return - - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_object_pointer_convert: - BX LR ;; return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_ipsr_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ SECTION `.text`:CODE:NOROOT(1) THUMB -_tx_misra_uchar_to_header_pointer_convert: - BX LR ;; return +_tx_misra_ipsr_get: + MRS R0, IPSR + BX LR // return /***********************************************************************************************/ /***********************************************************************************************/ /** */ -/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** ULONG _tx_misra_control_get(void); */ /** */ /***********************************************************************************************/ /***********************************************************************************************/ SECTION `.text`:CODE:NOROOT(1) THUMB -_tx_misra_uchar_to_entry_pointer_convert: - BX LR ;; return - +_tx_misra_control_get: + MRS R0, CONTROL + BX LR // return + /***********************************************************************************************/ /***********************************************************************************************/ /** */ -/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** void _tx_misra_control_set(ULONG value); */ /** */ /***********************************************************************************************/ /***********************************************************************************************/ SECTION `.text`:CODE:NOROOT(1) THUMB -_tx_misra_entry_to_uchar_pointer_convert: - BX LR ;; return -#endif +_tx_misra_control_set: + MSR CONTROL, R0 + BX LR // return + +#ifdef __ARMVFP__ /***********************************************************************************************/ /***********************************************************************************************/ /** */ -/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** ULONG _tx_misra_fpccr_get(void); */ /** */ /***********************************************************************************************/ /***********************************************************************************************/ - SECTION `.text`:CODE:NOROOT(1) + SECTION `.text`:CODE:NOROOT(2) THUMB -_tx_misra_char_to_uchar_pointer_convert: - BX LR ;; return - - -***********************************************************************************************/ +_tx_misra_fpccr_get: + LDR r0, =0xE000EF34 // Build FPCCR address + LDR r0, [r0] // Load FPCCR value + BX LR // return + + +/***********************************************************************************************/ /***********************************************************************************************/ /** */ -/** ULONG _tx_misra_ipsr_get(void); */ +/** void _tx_misra_vfp_touch(void); */ /** */ /***********************************************************************************************/ /***********************************************************************************************/ SECTION `.text`:CODE:NOROOT(1) THUMB -_tx_misra_ipsr_get: - MRS R0, IPSR - BX LR ;; return - - +_tx_misra_vfp_touch: + vmov.f32 s0, s0 + BX LR // return + +#endif + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports/cortex_m33/iar/src/tx_thread_secure_stack.c b/ports/cortex_m33/iar/src/tx_thread_secure_stack.c index 94d41db7e..83e6c37dc 100644 --- a/ports/cortex_m33/iar/src/tx_thread_secure_stack.c +++ b/ports/cortex_m33/iar/src/tx_thread_secure_stack.c @@ -165,7 +165,7 @@ INT index; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_allocate Cortex-M33/IAR */ -/* 6.1.10 */ +/* 6.1.11a */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -209,11 +209,15 @@ INT index; /* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ /* secure stack allocation, */ /* resulting in version 6.1.10 */ +/* 05-02-2022 Scott Larson Modified comment(s), added */ +/* TX_INTERRUPT_SAVE_AREA, */ +/* resulting in version 6.1.11a*/ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; UCHAR *stack_mem; @@ -314,7 +318,7 @@ INT secure_context_index; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_free Cortex-M33/IAR */ -/* 6.1.10 */ +/* 6.1.11a */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -352,11 +356,15 @@ INT secure_context_index; /* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ /* secure stack allocation, */ /* resulting in version 6.1.10 */ +/* 05-02-2022 Scott Larson Modified comment(s), added */ +/* TX_INTERRUPT_SAVE_AREA, */ +/* resulting in version 6.1.11a*/ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; INT secure_context_index; diff --git a/ports/cortex_m33/iar/src/tx_thread_secure_stack_initialize.s b/ports/cortex_m33/iar/src/tx_thread_secure_stack_initialize.s index 69e84264c..4fb1bb3c2 100644 --- a/ports/cortex_m33/iar/src/tx_thread_secure_stack_initialize.s +++ b/ports/cortex_m33/iar/src/tx_thread_secure_stack_initialize.s @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M33/IAR */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -50,13 +50,17 @@ /* */ /* CALLED BY */ /* */ -/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */ +/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ /* RELEASE HISTORY */ /* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports/cortex_m4/ac5/inc/tx_port.h b/ports/cortex_m4/ac5/inc/tx_port.h index 7967a9519..0eec634b4 100644 --- a/ports/cortex_m4/ac5/inc/tx_port.h +++ b/ports/cortex_m4/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/AC5 */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -59,6 +59,9 @@ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -146,6 +149,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -707,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC5 Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC5 Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/ac6/inc/tx_port.h b/ports/cortex_m4/ac6/inc/tx_port.h index e0f408ab3..71b663726 100644 --- a/ports/cortex_m4/ac6/inc/tx_port.h +++ b/ports/cortex_m4/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/AC6 */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -59,6 +59,9 @@ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -146,6 +149,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -707,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC6 Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC6 Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/ac6/src/tx_misra.S b/ports/cortex_m4/ac6/src/tx_misra.S index b03fdcd01..155512be4 100644 --- a/ports/cortex_m4/ac6/src/tx_misra.S +++ b/ports/cortex_m4/ac6/src/tx_misra.S @@ -103,6 +103,14 @@ .global _tx_misra_vfp_touch #endif + .global _tx_misra_event_flags_group_not_used + .global _tx_misra_event_flags_set_notify_not_used + .global _tx_misra_queue_not_used + .global _tx_misra_queue_send_notify_not_used + .global _tx_misra_semaphore_not_used + .global _tx_misra_semaphore_put_notify_not_used + .global _tx_misra_thread_entry_exit_notify_not_used + .global _tx_misra_thread_not_used /**************************************************************************/ /**************************************************************************/ @@ -172,17 +180,93 @@ _tx_misra_uchar_pointer_dif: BX LR // return -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ +/** */ +/** This single function serves all of the below prototypes. */ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** VOID _tx_misra_event_flags_group_not_used(TX_EVENT_FLAGS_GROUP *group_ptr); */ +/** VOID _tx_misra_event_flags_set_notify_not_used(VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); */ +/** VOID _tx_misra_queue_not_used(TX_QUEUE *queue_ptr); */ +/** VOID _tx_misra_queue_send_notify_not_used(VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); */ +/** VOID _tx_misra_semaphore_not_used(TX_SEMAPHORE *semaphore_ptr); */ +/** VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); */ +/** VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr); */ +/** VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)); */ +/** */ +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ .text .thumb_func _tx_misra_pointer_to_ulong_convert: +_tx_misra_ulong_to_pointer_convert: +_tx_misra_indirect_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_indirect_uchar_pointer_convert: +_tx_misra_block_pool_to_uchar_pointer_convert: +_tx_misra_void_to_block_pool_pointer_convert: +_tx_misra_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_block_pool_pointer_convert: +_tx_misra_void_to_indirect_uchar_pointer_convert: +_tx_misra_void_to_byte_pool_pointer_convert: +_tx_misra_byte_pool_to_uchar_pointer_convert: +_tx_misra_uchar_to_align_type_pointer_convert: +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: +_tx_misra_void_to_event_flags_pointer_convert: +_tx_misra_void_to_ulong_pointer_convert: +_tx_misra_void_to_mutex_pointer_convert: +_tx_misra_void_to_queue_pointer_convert: +_tx_misra_void_to_semaphore_pointer_convert: +_tx_misra_uchar_to_void_pointer_convert: +_tx_misra_ulong_to_thread_pointer_convert: +_tx_misra_timer_indirect_to_void_pointer_convert: +_tx_misra_const_char_to_char_pointer_convert: +_tx_misra_void_to_thread_pointer_convert: +#ifdef TX_ENABLE_EVENT_TRACE +_tx_misra_object_to_uchar_pointer_convert: +_tx_misra_uchar_to_object_pointer_convert: +_tx_misra_uchar_to_header_pointer_convert: +_tx_misra_uchar_to_entry_pointer_convert: +_tx_misra_entry_to_uchar_pointer_convert: +#endif +_tx_misra_char_to_uchar_pointer_convert: +_tx_misra_event_flags_group_not_used: +_tx_misra_event_flags_set_notify_not_used: +_tx_misra_queue_not_used: +_tx_misra_queue_send_notify_not_used: +_tx_misra_semaphore_not_used: +_tx_misra_semaphore_put_notify_not_used: +_tx_misra_thread_entry_exit_notify_not_used: +_tx_misra_thread_not_used: + BX LR // return @@ -234,20 +318,6 @@ _tx_misra_ulong_pointer_dif: BX LR // return -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - .text - .thumb_func -_tx_misra_ulong_to_pointer_convert: - BX LR // return - - /**************************************************************************/ /**************************************************************************/ /** */ @@ -332,12 +402,9 @@ _tx_misra_timer_pointer_add: .text .thumb_func _tx_misra_user_timer_pointer_get: - ADDS R2,R0,#+8 - SUBS R2,R2,R0 - RSBS R2,R2,#+0 - ADD R0,R0,R2 - STR R0,[R1, #+0] - BX LR // return + SUBS R0,#8 + STR R0,[R1, #+0] + BX LR // return /**************************************************************************/ @@ -553,202 +620,6 @@ _tx_misra_always_true: BX LR // return -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - .text - .thumb_func -_tx_misra_indirect_void_to_uchar_pointer_convert: - BX LR // return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_indirect_uchar_pointer_convert: - BX LR // return - - -/***********************************************************************************/ -/***********************************************************************************/ -/** */ -/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ -/** */ -/***********************************************************************************/ -/***********************************************************************************/ - - .text - .thumb_func -_tx_misra_block_pool_to_uchar_pointer_convert: - BX LR // return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_block_pool_pointer_convert: - BX LR // return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_uchar_pointer_convert: - BX LR // return - - -/************************************************************************************/ -/************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************/ -/************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_block_pool_pointer_convert: - BX LR // return - - -/**************************************************************************************/ -/**************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************/ -/**************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_indirect_uchar_pointer_convert: - BX LR // return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_byte_pool_pointer_convert: - BX LR // return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - .text - .thumb_func -_tx_misra_byte_pool_to_uchar_pointer_convert: - BX LR // return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_align_type_pointer_convert: - BX LR // return - - -/****************************************************************************************************/ -/****************************************************************************************************/ -/** */ -/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/****************************************************************************************************/ -/****************************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: - BX LR // return - - -/**************************************************************************************************/ -/**************************************************************************************************/ -/** */ -/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************************/ -/**************************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_event_flags_pointer_convert: - BX LR // return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_ulong_pointer_convert: - BX LR // return - - -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_mutex_pointer_convert: - BX LR // return - - /**************************************************************************/ /**************************************************************************/ /** */ @@ -764,191 +635,6 @@ _tx_misra_status_get: BX LR // return -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_queue_pointer_convert: - BX LR // return - - -/****************************************************************************************/ -/****************************************************************************************/ -/** */ -/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ -/** */ -/****************************************************************************************/ -/****************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_semaphore_pointer_convert: - BX LR // return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_void_pointer_convert: - BX LR // return - - -/*********************************************************************************/ -/*********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ -/** */ -/*********************************************************************************/ -/*********************************************************************************/ - - .text - .thumb_func -_tx_misra_ulong_to_thread_pointer_convert: - BX LR // return - - -/***************************************************************************************************/ -/***************************************************************************************************/ -/** */ -/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ -/** */ -/***************************************************************************************************/ -/***************************************************************************************************/ - - .text - .thumb_func -_tx_misra_timer_indirect_to_void_pointer_convert: - BX LR // return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - .text - .thumb_func -_tx_misra_const_char_to_char_pointer_convert: - BX LR // return - - -/**********************************************************************************/ -/**********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ -/** */ -/**********************************************************************************/ -/**********************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_thread_pointer_convert: - BX LR // return - - -#ifdef TX_ENABLE_EVENT_TRACE - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - .text - .thumb_func -_tx_misra_object_to_uchar_pointer_convert: - BX LR // return - - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_object_pointer_convert: - BX LR // return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_header_pointer_convert: - BX LR // return - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_entry_pointer_convert: - BX LR // return - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - .text - .thumb_func -_tx_misra_entry_to_uchar_pointer_convert: - BX LR // return -#endif - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - .text - .thumb_func -_tx_misra_char_to_uchar_pointer_convert: - BX LR // return - - /***********************************************************************************************/ /***********************************************************************************************/ /** */ diff --git a/ports/cortex_m4/gnu/example_build/build_threadx.bat b/ports/cortex_m4/gnu/example_build/build_threadx.bat index 062092d35..a52e9e682 100644 --- a/ports/cortex_m4/gnu/example_build/build_threadx.bat +++ b/ports/cortex_m4/gnu/example_build/build_threadx.bat @@ -1,199 +1,198 @@ del tx.a -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb tx_initialize_low_level.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ../src/tx_thread_stack_build.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ../src/tx_thread_schedule.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ../src/tx_thread_system_return.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ../src/tx_thread_context_save.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ../src/tx_thread_context_restore.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ../src/tx_thread_interrupt_control.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ../src/tx_timer_interrupt.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ../src/tx_thread_interrupt_control.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb ../src/tx_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb ../src/tx_thread_schedule.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb ../src/tx_thread_system_return.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb ../src/tx_thread_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb ../src/tx_thread_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb ../src/tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb ../src/tx_timer_interrupt.S + +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c + arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o -arm-none-eabi-ar -r tx.a tx_thread_interrupt_control.o tx_initialize_low_level.o arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o diff --git a/ports/cortex_m4/gnu/example_build/build_threadx_sample.bat b/ports/cortex_m4/gnu/example_build/build_threadx_sample.bat index fd75f7bdd..b25cd5156 100644 --- a/ports/cortex_m4/gnu/example_build/build_threadx_sample.bat +++ b/ports/cortex_m4/gnu/example_build/build_threadx_sample.bat @@ -1,7 +1,5 @@ -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb tx_simulator_startup.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb cortexm4_crt0.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb tx_initialize_low_level.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc sample_threadx.c -arm-none-eabi-ld -A cortex-m4 -ereset_handler -T sample_threadx.ld tx_simulator_startup.o cortexm4_crt0.o tx_initialize_low_level.o sample_threadx.o tx.a libc.a -o sample_threadx.out -M > sample_threadx.map - - +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb cortexm4_vectors.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb cortexm4_crt0.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I../../../../common/inc -I../inc sample_threadx.c +arm-none-eabi-gcc -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -T sample_threadx.ld -ereset_handler -nostartfiles -o sample_threadx.out -Wl,-Map=sample_threadx.map cortexm4_vectors.o cortexm4_crt0.o tx_initialize_low_level.o sample_threadx.o tx.a diff --git a/ports/cortex_m7/gnu/example_build/cortexm7_crt0.s b/ports/cortex_m4/gnu/example_build/cortexm4_crt0.S similarity index 99% rename from ports/cortex_m7/gnu/example_build/cortexm7_crt0.s rename to ports/cortex_m4/gnu/example_build/cortexm4_crt0.S index d4cb16360..bb530ac5a 100644 --- a/ports/cortex_m7/gnu/example_build/cortexm7_crt0.s +++ b/ports/cortex_m4/gnu/example_build/cortexm4_crt0.S @@ -13,7 +13,6 @@ _start: ldr r1, =__stack_end__ mov sp, r1 - /* Copy initialised sections into RAM if required. */ ldr r0, =__data_load_start__ ldr r1, =__data_start__ @@ -47,7 +46,6 @@ _start: mov r2, #0 bl crt0_memory_set - /* Setup heap - not recommended for Threadx but here for compatibility reasons */ ldr r0, = __heap_start__ ldr r1, = __heap_end__ @@ -57,7 +55,6 @@ _start: add r0, r0, #4 str r1, [r0] - /* constructors in case of using C++ */ ldr r0, =__ctors_start__ ldr r1, =__ctors_end__ @@ -72,13 +69,11 @@ crt0_ctor_loop: b crt0_ctor_loop crt0_ctor_end: - /* Setup call frame for main() */ mov r0, #0 mov lr, r0 mov r12, sp - start: /* Jump to main() */ mov r0, #0 @@ -93,7 +88,6 @@ crt0_exit_loop: /* Startup helper functions. */ - crt0_memory_copy: cmp r0, r1 beq memory_copy_done @@ -109,7 +103,6 @@ memory_copy_loop: memory_copy_done: bx lr - crt0_memory_set: cmp r0, r1 beq memory_set_done @@ -119,7 +112,6 @@ crt0_memory_set: memory_set_done: bx lr - /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */ .section .stack, "wa", %nobits .section .stack_process, "wa", %nobits diff --git a/ports/cortex_m7/gnu/example_build/tx_simulator_startup.s b/ports/cortex_m4/gnu/example_build/cortexm4_vectors.S similarity index 90% rename from ports/cortex_m7/gnu/example_build/tx_simulator_startup.s rename to ports/cortex_m4/gnu/example_build/cortexm4_vectors.S index cf0db9742..6ae558e4d 100644 --- a/ports/cortex_m7/gnu/example_build/tx_simulator_startup.s +++ b/ports/cortex_m4/gnu/example_build/cortexm4_vectors.S @@ -1,5 +1,3 @@ - - .global reset_handler .global __tx_NMIHandler @@ -10,7 +8,6 @@ .global __tx_SysTickHandler .global __tx_BadHandler - .syntax unified .section .vectors, "ax" .code 16 @@ -29,7 +26,7 @@ _vectors: .word 0 // Reserved .word 0 // Reserved .word 0 // Reserved - .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // + .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved .word __tx_PendSVHandler @@ -70,14 +67,10 @@ _vectors: .word __tx_BadHandler .word __tx_BadHandler - - - .section .init, "ax" - .thumb_func + .section .init, "ax" + .thumb_func reset_handler: - -// low level hardware config, such as PLL setup goes here - + // low level hardware config, such as PLL setup goes here b _start diff --git a/ports/cortex_m4/gnu/example_build/sample_threadx.ld b/ports/cortex_m4/gnu/example_build/sample_threadx.ld index 28f203fdf..c65a13464 100644 --- a/ports/cortex_m4/gnu/example_build/sample_threadx.ld +++ b/ports/cortex_m4/gnu/example_build/sample_threadx.ld @@ -1,206 +1,125 @@ MEMORY { - UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0 - CM3_System_Control_Space (wx) : ORIGIN = 0xe000e000, LENGTH = 0x00001000 - AHB_Peripherals (wx) : ORIGIN = 0x50000000, LENGTH = 0x00200000 - APB1_Peripherals (wx) : ORIGIN = 0x40080000, LENGTH = 0x00080000 - APB0_Peripherals (wx) : ORIGIN = 0x40000000, LENGTH = 0x00080000 - GPIO (wx) : ORIGIN = 0x2009c000, LENGTH = 0x00004000 - AHBSRAM1 (wx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 - AHBSRAM0 (wx) : ORIGIN = 0x2007c000, LENGTH = 0x00004000 - RAM (wx) : ORIGIN = 0x10000000, LENGTH = 0x00008000 - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + RAM (wx) : ORIGIN = 0x20000000, LENGTH = 0x00800000 + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00400000 } +__STACKSIZE__ = 1024; +__STACKSIZE_PROCESS__ = 0; +__HEAPSIZE__ = 128; SECTIONS { - __CM3_System_Control_Space_segment_start__ = 0xe000e000; - __CM3_System_Control_Space_segment_end__ = 0xe000f000; - __AHB_Peripherals_segment_start__ = 0x50000000; - __AHB_Peripherals_segment_end__ = 0x50200000; - __APB1_Peripherals_segment_start__ = 0x40080000; - __APB1_Peripherals_segment_end__ = 0x40100000; - __APB0_Peripherals_segment_start__ = 0x40000000; - __APB0_Peripherals_segment_end__ = 0x40080000; - __GPIO_segment_start__ = 0x2009c000; - __GPIO_segment_end__ = 0x200a0000; - __AHBSRAM1_segment_start__ = 0x20080000; - __AHBSRAM1_segment_end__ = 0x20084000; - __AHBSRAM0_segment_start__ = 0x2007c000; - __AHBSRAM0_segment_end__ = 0x20080000; - __RAM_segment_start__ = 0x10000000; - __RAM_segment_end__ = 0x10008000; - __FLASH_segment_start__ = 0x00000000; - __FLASH_segment_end__ = 0x00080000; - - __STACKSIZE__ = 1024; - __STACKSIZE_PROCESS__ = 0; - __STACKSIZE_IRQ__ = 0; - __STACKSIZE_FIQ__ = 0; - __STACKSIZE_SVC__ = 0; - __STACKSIZE_ABT__ = 0; - __STACKSIZE_UND__ = 0; - __HEAPSIZE__ = 128; - - __vectors_load_start__ = __FLASH_segment_start__; - .vectors __FLASH_segment_start__ : AT(__FLASH_segment_start__) + .vectors : { - __vectors_start__ = .; - *(.vectors .vectors.*) - } - __vectors_end__ = __vectors_start__ + SIZEOF(.vectors); - - . = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .vectors is too large to fit in FLASH memory segment"); - - __init_load_start__ = ALIGN(__vectors_end__ , 4); - .init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4)) - { - __init_start__ = .; - *(.init .init.*) - } - __init_end__ = __init_start__ + SIZEOF(.init); - - . = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .init is too large to fit in FLASH memory segment"); - - __text_load_start__ = ALIGN(__init_end__ , 4); - .text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4)) - { - __text_start__ = .; - *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table) - } - __text_end__ = __text_start__ + SIZEOF(.text); - - . = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .text is too large to fit in FLASH memory segment"); - - __dtors_load_start__ = ALIGN(__text_end__ , 4); - .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4)) - { - __dtors_start__ = .; - KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) - } - __dtors_end__ = __dtors_start__ + SIZEOF(.dtors); - - . = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .dtors is too large to fit in FLASH memory segment"); - - __ctors_load_start__ = ALIGN(__dtors_end__ , 4); - .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4)) - { - __ctors_start__ = .; - KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) - } - __ctors_end__ = __ctors_start__ + SIZEOF(.ctors); - - . = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .ctors is too large to fit in FLASH memory segment"); - - __rodata_load_start__ = ALIGN(__ctors_end__ , 4); - .rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4)) - { - __rodata_start__ = .; - *(.rodata .rodata.* .gnu.linkonce.r.*) - } - __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - - . = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .rodata is too large to fit in FLASH memory segment"); - - __fast_load_start__ = ALIGN(__rodata_end__ , 4); - .fast ALIGN(__RAM_segment_start__ , 4) : AT(ALIGN(__rodata_end__ , 4)) - { - __fast_start__ = .; - *(.fast .fast.*) - } - __fast_end__ = __fast_start__ + SIZEOF(.fast); - - __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast); - - . = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00080000) , "error: .fast is too large to fit in FLASH memory segment"); - - .fast_run ALIGN(__RAM_segment_start__ , 4) (NOLOAD) : - { - __fast_run_start__ = .; - . = MAX(__fast_run_start__ + SIZEOF(.fast), .); - } - __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run); - - . = ASSERT(__fast_run_end__ >= __RAM_segment_start__ && __fast_run_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .fast_run is too large to fit in RAM memory segment"); - - __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4); - .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4)) - { - __data_start__ = .; - *(.data .data.* .gnu.linkonce.d.*) - } - __data_end__ = __data_start__ + SIZEOF(.data); - - __data_load_end__ = __data_load_start__ + SIZEOF(.data); - - __FLASH_segment_used_end__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4) + SIZEOF(.data); - - . = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00080000) , "error: .data is too large to fit in FLASH memory segment"); - - .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) : - { - __data_run_start__ = .; - . = MAX(__data_run_start__ + SIZEOF(.data), .); - } - __data_run_end__ = __data_run_start__ + SIZEOF(.data_run); - - . = ASSERT(__data_run_end__ >= __RAM_segment_start__ && __data_run_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .data_run is too large to fit in RAM memory segment"); - - __bss_load_start__ = ALIGN(__data_run_end__ , 4); - .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4)) - { - __bss_start__ = .; - *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) - } - __bss_end__ = __bss_start__ + SIZEOF(.bss); - - . = ASSERT(__bss_end__ >= __RAM_segment_start__ && __bss_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .bss is too large to fit in RAM memory segment"); - - __non_init_load_start__ = ALIGN(__bss_end__ , 4); - .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4)) - { - __non_init_start__ = .; - *(.non_init .non_init.*) - } - __non_init_end__ = __non_init_start__ + SIZEOF(.non_init); - - . = ASSERT(__non_init_end__ >= __RAM_segment_start__ && __non_init_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .non_init is too large to fit in RAM memory segment"); - - __heap_load_start__ = ALIGN(__non_init_end__ , 4); - .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4)) - { - __heap_start__ = .; + KEEP(*(.vectors .vectors.*)) + } > FLASH + + .text : + { + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + __ctors_start__ = ALIGN(4); + *(SORT(.ctors.*)) + *(.ctors) + __ctors_end__ = ALIGN(4); + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + __dtors_start__ = ALIGN(4); + *(SORT(.dtors.*)) + *(.dtors) + __dtors_end__ = ALIGN(4); + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __data_load_start__ = ALIGN (4); + + .data : AT (__data_load_start__) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + + } > RAM + + .heap (COPY): + { + __heap_start__ = ALIGN(4); *(.heap) - . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4); - } - __heap_end__ = __heap_start__ + SIZEOF(.heap); - - . = ASSERT(__heap_end__ >= __RAM_segment_start__ && __heap_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .heap is too large to fit in RAM memory segment"); + . = ALIGN(. + __HEAPSIZE__, 4); + __heap_end__ = ALIGN(4); + } > RAM - __stack_load_start__ = ALIGN(__heap_end__ , 4); - .stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4)) + .stack ALIGN(4) (NOLOAD) : { - __stack_start__ = .; + __stack_start__ = ALIGN(4); *(.stack) - . = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4); - } - __stack_end__ = __stack_start__ + SIZEOF(.stack); - - . = ASSERT(__stack_end__ >= __RAM_segment_start__ && __stack_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .stack is too large to fit in RAM memory segment"); - - __stack_process_load_start__ = ALIGN(__stack_end__ , 4); - .stack_process ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4)) - { - __stack_process_start__ = .; - *(.stack_process) - . = ALIGN(MAX(__stack_process_start__ + __STACKSIZE_PROCESS__ , .), 4); - } - __stack_process_end__ = __stack_process_start__ + SIZEOF(.stack_process); - - __RAM_segment_used_end__ = ALIGN(__stack_end__ , 4) + SIZEOF(.stack_process); - - . = ASSERT(__stack_process_end__ >= __RAM_segment_start__ && __stack_process_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .stack_process is too large to fit in RAM memory segment"); + . = ALIGN(. + __STACKSIZE__, 4); + __stack_end__ = ALIGN(4); + } > RAM + __RAM_segment_used_end__ = .; } - diff --git a/ports/cortex_m4/gnu/inc/tx_port.h b/ports/cortex_m4/gnu/inc/tx_port.h index f1e25ab30..7d3cb2804 100644 --- a/ports/cortex_m4/gnu/inc/tx_port.h +++ b/ports/cortex_m4/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/GNU */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -59,6 +59,9 @@ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -146,6 +149,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -707,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/GNU Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/GNU Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/gnu/src/tx_misra.S b/ports/cortex_m4/gnu/src/tx_misra.S index b03fdcd01..155512be4 100644 --- a/ports/cortex_m4/gnu/src/tx_misra.S +++ b/ports/cortex_m4/gnu/src/tx_misra.S @@ -103,6 +103,14 @@ .global _tx_misra_vfp_touch #endif + .global _tx_misra_event_flags_group_not_used + .global _tx_misra_event_flags_set_notify_not_used + .global _tx_misra_queue_not_used + .global _tx_misra_queue_send_notify_not_used + .global _tx_misra_semaphore_not_used + .global _tx_misra_semaphore_put_notify_not_used + .global _tx_misra_thread_entry_exit_notify_not_used + .global _tx_misra_thread_not_used /**************************************************************************/ /**************************************************************************/ @@ -172,17 +180,93 @@ _tx_misra_uchar_pointer_dif: BX LR // return -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ +/** */ +/** This single function serves all of the below prototypes. */ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** VOID _tx_misra_event_flags_group_not_used(TX_EVENT_FLAGS_GROUP *group_ptr); */ +/** VOID _tx_misra_event_flags_set_notify_not_used(VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); */ +/** VOID _tx_misra_queue_not_used(TX_QUEUE *queue_ptr); */ +/** VOID _tx_misra_queue_send_notify_not_used(VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); */ +/** VOID _tx_misra_semaphore_not_used(TX_SEMAPHORE *semaphore_ptr); */ +/** VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); */ +/** VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr); */ +/** VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)); */ +/** */ +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ .text .thumb_func _tx_misra_pointer_to_ulong_convert: +_tx_misra_ulong_to_pointer_convert: +_tx_misra_indirect_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_indirect_uchar_pointer_convert: +_tx_misra_block_pool_to_uchar_pointer_convert: +_tx_misra_void_to_block_pool_pointer_convert: +_tx_misra_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_block_pool_pointer_convert: +_tx_misra_void_to_indirect_uchar_pointer_convert: +_tx_misra_void_to_byte_pool_pointer_convert: +_tx_misra_byte_pool_to_uchar_pointer_convert: +_tx_misra_uchar_to_align_type_pointer_convert: +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: +_tx_misra_void_to_event_flags_pointer_convert: +_tx_misra_void_to_ulong_pointer_convert: +_tx_misra_void_to_mutex_pointer_convert: +_tx_misra_void_to_queue_pointer_convert: +_tx_misra_void_to_semaphore_pointer_convert: +_tx_misra_uchar_to_void_pointer_convert: +_tx_misra_ulong_to_thread_pointer_convert: +_tx_misra_timer_indirect_to_void_pointer_convert: +_tx_misra_const_char_to_char_pointer_convert: +_tx_misra_void_to_thread_pointer_convert: +#ifdef TX_ENABLE_EVENT_TRACE +_tx_misra_object_to_uchar_pointer_convert: +_tx_misra_uchar_to_object_pointer_convert: +_tx_misra_uchar_to_header_pointer_convert: +_tx_misra_uchar_to_entry_pointer_convert: +_tx_misra_entry_to_uchar_pointer_convert: +#endif +_tx_misra_char_to_uchar_pointer_convert: +_tx_misra_event_flags_group_not_used: +_tx_misra_event_flags_set_notify_not_used: +_tx_misra_queue_not_used: +_tx_misra_queue_send_notify_not_used: +_tx_misra_semaphore_not_used: +_tx_misra_semaphore_put_notify_not_used: +_tx_misra_thread_entry_exit_notify_not_used: +_tx_misra_thread_not_used: + BX LR // return @@ -234,20 +318,6 @@ _tx_misra_ulong_pointer_dif: BX LR // return -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - .text - .thumb_func -_tx_misra_ulong_to_pointer_convert: - BX LR // return - - /**************************************************************************/ /**************************************************************************/ /** */ @@ -332,12 +402,9 @@ _tx_misra_timer_pointer_add: .text .thumb_func _tx_misra_user_timer_pointer_get: - ADDS R2,R0,#+8 - SUBS R2,R2,R0 - RSBS R2,R2,#+0 - ADD R0,R0,R2 - STR R0,[R1, #+0] - BX LR // return + SUBS R0,#8 + STR R0,[R1, #+0] + BX LR // return /**************************************************************************/ @@ -553,202 +620,6 @@ _tx_misra_always_true: BX LR // return -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - .text - .thumb_func -_tx_misra_indirect_void_to_uchar_pointer_convert: - BX LR // return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_indirect_uchar_pointer_convert: - BX LR // return - - -/***********************************************************************************/ -/***********************************************************************************/ -/** */ -/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ -/** */ -/***********************************************************************************/ -/***********************************************************************************/ - - .text - .thumb_func -_tx_misra_block_pool_to_uchar_pointer_convert: - BX LR // return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_block_pool_pointer_convert: - BX LR // return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_uchar_pointer_convert: - BX LR // return - - -/************************************************************************************/ -/************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************/ -/************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_block_pool_pointer_convert: - BX LR // return - - -/**************************************************************************************/ -/**************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************/ -/**************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_indirect_uchar_pointer_convert: - BX LR // return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_byte_pool_pointer_convert: - BX LR // return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - .text - .thumb_func -_tx_misra_byte_pool_to_uchar_pointer_convert: - BX LR // return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_align_type_pointer_convert: - BX LR // return - - -/****************************************************************************************************/ -/****************************************************************************************************/ -/** */ -/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/****************************************************************************************************/ -/****************************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: - BX LR // return - - -/**************************************************************************************************/ -/**************************************************************************************************/ -/** */ -/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************************/ -/**************************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_event_flags_pointer_convert: - BX LR // return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_ulong_pointer_convert: - BX LR // return - - -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_mutex_pointer_convert: - BX LR // return - - /**************************************************************************/ /**************************************************************************/ /** */ @@ -764,191 +635,6 @@ _tx_misra_status_get: BX LR // return -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_queue_pointer_convert: - BX LR // return - - -/****************************************************************************************/ -/****************************************************************************************/ -/** */ -/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ -/** */ -/****************************************************************************************/ -/****************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_semaphore_pointer_convert: - BX LR // return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_void_pointer_convert: - BX LR // return - - -/*********************************************************************************/ -/*********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ -/** */ -/*********************************************************************************/ -/*********************************************************************************/ - - .text - .thumb_func -_tx_misra_ulong_to_thread_pointer_convert: - BX LR // return - - -/***************************************************************************************************/ -/***************************************************************************************************/ -/** */ -/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ -/** */ -/***************************************************************************************************/ -/***************************************************************************************************/ - - .text - .thumb_func -_tx_misra_timer_indirect_to_void_pointer_convert: - BX LR // return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - .text - .thumb_func -_tx_misra_const_char_to_char_pointer_convert: - BX LR // return - - -/**********************************************************************************/ -/**********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ -/** */ -/**********************************************************************************/ -/**********************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_thread_pointer_convert: - BX LR // return - - -#ifdef TX_ENABLE_EVENT_TRACE - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - .text - .thumb_func -_tx_misra_object_to_uchar_pointer_convert: - BX LR // return - - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_object_pointer_convert: - BX LR // return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_header_pointer_convert: - BX LR // return - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_entry_pointer_convert: - BX LR // return - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - .text - .thumb_func -_tx_misra_entry_to_uchar_pointer_convert: - BX LR // return -#endif - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - .text - .thumb_func -_tx_misra_char_to_uchar_pointer_convert: - BX LR // return - - /***********************************************************************************************/ /***********************************************************************************************/ /** */ diff --git a/ports/cortex_m4/iar/CMakeLists.txt b/ports/cortex_m4/iar/CMakeLists.txt new file mode 100644 index 000000000..a524d79f0 --- /dev/null +++ b/ports/cortex_m4/iar/CMakeLists.txt @@ -0,0 +1,21 @@ + +target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} + ${CMAKE_CURRENT_LIST_DIR}/src/tx_iar.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_disable.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S + # {{END_TARGET_SOURCES}} +) + +target_include_directories(${PROJECT_NAME} + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/inc +) diff --git a/ports/cortex_m4/iar/inc/tx_port.h b/ports/cortex_m4/iar/inc/tx_port.h index b27fa00f3..93f0651a6 100644 --- a/ports/cortex_m4/iar/inc/tx_port.h +++ b/ports/cortex_m4/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/IAR */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -59,6 +59,9 @@ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -146,6 +149,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -707,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/IAR Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/IAR Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/iar/src/tx_misra.s b/ports/cortex_m4/iar/src/tx_misra.s index 2add69b34..c81c3e5cc 100644 --- a/ports/cortex_m4/iar/src/tx_misra.s +++ b/ports/cortex_m4/iar/src/tx_misra.s @@ -102,6 +102,16 @@ PUBLIC _tx_misra_fpccr_get PUBLIC _tx_misra_vfp_touch #endif + + PUBLIC _tx_misra_event_flags_group_not_used + PUBLIC _tx_misra_event_flags_set_notify_not_used + PUBLIC _tx_misra_queue_not_used + PUBLIC _tx_misra_queue_send_notify_not_used + PUBLIC _tx_misra_semaphore_not_used + PUBLIC _tx_misra_semaphore_put_notify_not_used + PUBLIC _tx_misra_thread_entry_exit_notify_not_used + PUBLIC _tx_misra_thread_not_used + PUBLIC _tx_version_id @@ -115,7 +125,7 @@ _tx_version_id: DC8 45H, 78H, 70H, 72H, 65H, 73H, 73H, 20H DC8 4CH, 6FH, 67H, 69H, 63H, 20H, 49H, 6EH DC8 63H, 2EH, 20H, 2AH, 20H, 54H, 68H, 72H - DC8 65H, 61H, 64H, 58H, 20H, 35H, 2EH, 38H + DC8 65H, 61H, 64H, 58H, 20H, 36H, 2EH, 31H DC8 20H, 4DH, 49H, 53H, 52H, 41H, 20H, 43H DC8 20H, 43H, 6FH, 6DH, 70H, 6CH, 69H, 61H DC8 6EH, 74H, 20H, 2AH, 0 @@ -139,7 +149,7 @@ _tx_misra_memset: MOVS R1,R0 MOVS R0,R4 BL __aeabi_memset - POP {R4,PC} ;; return + POP {R4,PC} // return /**************************************************************************/ /**************************************************************************/ @@ -153,7 +163,7 @@ _tx_misra_memset: THUMB _tx_misra_uchar_pointer_add: ADD R0,R0,R1 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -169,7 +179,7 @@ _tx_misra_uchar_pointer_add: _tx_misra_uchar_pointer_sub: RSBS R1,R1,#+0 ADD R0,R0,R1 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -184,21 +194,97 @@ _tx_misra_uchar_pointer_sub: THUMB _tx_misra_uchar_pointer_dif: SUBS R0,R0,R1 - BX LR ;; return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - + BX LR // return + + +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ +/** */ +/** This single function serves all of the below prototypes. */ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** VOID _tx_misra_event_flags_group_not_used(TX_EVENT_FLAGS_GROUP *group_ptr); */ +/** VOID _tx_misra_event_flags_set_notify_not_used(VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); */ +/** VOID _tx_misra_queue_not_used(TX_QUEUE *queue_ptr); */ +/** VOID _tx_misra_queue_send_notify_not_used(VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); */ +/** VOID _tx_misra_semaphore_not_used(TX_SEMAPHORE *semaphore_ptr); */ +/** VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); */ +/** VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr); */ +/** VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)); */ +/** */ +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ SECTION `.text`:CODE:NOROOT(1) THUMB _tx_misra_pointer_to_ulong_convert: - BX LR ;; return +_tx_misra_ulong_to_pointer_convert: +_tx_misra_indirect_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_indirect_uchar_pointer_convert: +_tx_misra_block_pool_to_uchar_pointer_convert: +_tx_misra_void_to_block_pool_pointer_convert: +_tx_misra_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_block_pool_pointer_convert: +_tx_misra_void_to_indirect_uchar_pointer_convert: +_tx_misra_void_to_byte_pool_pointer_convert: +_tx_misra_byte_pool_to_uchar_pointer_convert: +_tx_misra_uchar_to_align_type_pointer_convert: +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: +_tx_misra_void_to_event_flags_pointer_convert: +_tx_misra_void_to_ulong_pointer_convert: +_tx_misra_void_to_mutex_pointer_convert: +_tx_misra_void_to_queue_pointer_convert: +_tx_misra_void_to_semaphore_pointer_convert: +_tx_misra_uchar_to_void_pointer_convert: +_tx_misra_ulong_to_thread_pointer_convert: +_tx_misra_timer_indirect_to_void_pointer_convert: +_tx_misra_const_char_to_char_pointer_convert: +_tx_misra_void_to_thread_pointer_convert: +#ifdef TX_ENABLE_EVENT_TRACE +_tx_misra_object_to_uchar_pointer_convert: +_tx_misra_uchar_to_object_pointer_convert: +_tx_misra_uchar_to_header_pointer_convert: +_tx_misra_uchar_to_entry_pointer_convert: +_tx_misra_entry_to_uchar_pointer_convert: +#endif +_tx_misra_char_to_uchar_pointer_convert: +_tx_misra_event_flags_group_not_used: +_tx_misra_event_flags_set_notify_not_used: +_tx_misra_queue_not_used: +_tx_misra_queue_send_notify_not_used: +_tx_misra_semaphore_not_used: +_tx_misra_semaphore_put_notify_not_used: +_tx_misra_thread_entry_exit_notify_not_used: +_tx_misra_thread_not_used: + + BX LR // return /**************************************************************************/ @@ -213,7 +299,7 @@ _tx_misra_pointer_to_ulong_convert: THUMB _tx_misra_ulong_pointer_add: ADD R0,R0,R1, LSL #+2 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -230,7 +316,7 @@ _tx_misra_ulong_pointer_sub: MVNS R2,#+3 MULS R1,R2,R1 ADD R0,R0,R1 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -246,21 +332,7 @@ _tx_misra_ulong_pointer_sub: _tx_misra_ulong_pointer_dif: SUBS R0,R0,R1 ASRS R0,R0,#+2 - BX LR ;; return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_ulong_to_pointer_convert: - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -299,7 +371,7 @@ _tx_misra_message_copy: STR R3,[R0, #+0] STR R4,[R1, #+0] POP {R4,R5} - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -316,7 +388,7 @@ _tx_misra_message_copy: _tx_misra_timer_pointer_dif: SUBS R0,R0,R1 ASRS R0,R0,#+2 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -332,7 +404,7 @@ _tx_misra_timer_pointer_dif: THUMB _tx_misra_timer_pointer_add: ADD R0,R0,R1, LSL #+2 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -347,12 +419,9 @@ _tx_misra_timer_pointer_add: SECTION `.text`:CODE:NOROOT(1) THUMB _tx_misra_user_timer_pointer_get: - ADDS R2,R0,#+8 - SUBS R2,R2,R0 - RSBS R2,R2,#+0 - ADD R0,R0,R2 - STR R0,[R1, #+0] - BX LR ;; return + SUBS R0,#8 + STR R0,[R1, #+0] + BX LR // return /**************************************************************************/ @@ -374,7 +443,7 @@ _tx_misra_thread_stack_check: CMP R4,#+0 BEQ.N ??_tx_misra_thread_stack_check_0 LDR R1,[R4, #+0] - LDR.N R2,??DataTable2 ;; 0x54485244 + LDR.N R2,??DataTable2 // 0x54485244 CMP R1,R2 BNE.N ??_tx_misra_thread_stack_check_0 LDR R1,[R4, #+8] @@ -412,7 +481,7 @@ _tx_misra_thread_stack_check: BL _tx_thread_interrupt_disable ??_tx_misra_thread_stack_check_0: BL _tx_thread_interrupt_restore - POP {R0,R4,R5,PC} ;; return + POP {R0,R4,R5,PC} // return #ifdef TX_ENABLE_EVENT_TRACE @@ -500,7 +569,7 @@ _tx_misra_trace_event_insert: LDR R0,[R0, #+0] STR R4,[R0, #+32] ??_tx_misra_trace_event_insert_0: - POP {R0,R4-R7,PC} ;; return + POP {R0,R4-R7,PC} // return SECTION `.text`:CODE:NOROOT(2) @@ -552,7 +621,7 @@ _tx_misra_trace_event_insert: THUMB _tx_misra_time_stamp_get: MOVS R0,#+0 - BX LR ;; return + BX LR // return #endif @@ -587,203 +656,7 @@ _tx_misra_time_stamp_get: THUMB _tx_misra_always_true: MOVS R0,#+1 - BX LR ;; return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_indirect_void_to_uchar_pointer_convert: - BX LR ;; return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_indirect_uchar_pointer_convert: - BX LR ;; return - - -/***********************************************************************************/ -/***********************************************************************************/ -/** */ -/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ -/** */ -/***********************************************************************************/ -/***********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_block_pool_to_uchar_pointer_convert: - BX LR ;; return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_block_pool_pointer_convert: - BX LR ;; return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_uchar_pointer_convert: - BX LR ;; return - - -/************************************************************************************/ -/************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************/ -/************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_block_pool_pointer_convert: - BX LR ;; return - - -/**************************************************************************************/ -/**************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************/ -/**************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_indirect_uchar_pointer_convert: - BX LR ;; return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_byte_pool_pointer_convert: - BX LR ;; return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_byte_pool_to_uchar_pointer_convert: - BX LR ;; return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_align_type_pointer_convert: - BX LR ;; return - - -/****************************************************************************************************/ -/****************************************************************************************************/ -/** */ -/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/****************************************************************************************************/ -/****************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: - BX LR ;; return - - -/**************************************************************************************************/ -/**************************************************************************************************/ -/** */ -/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************************/ -/**************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_event_flags_pointer_convert: - BX LR ;; return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_ulong_pointer_convert: - BX LR ;; return - - -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_mutex_pointer_convert: - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -798,192 +671,7 @@ _tx_misra_void_to_mutex_pointer_convert: THUMB _tx_misra_status_get: MOVS R0,#+0 - BX LR ;; return - - -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_queue_pointer_convert: - BX LR ;; return - - -/****************************************************************************************/ -/****************************************************************************************/ -/** */ -/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ -/** */ -/****************************************************************************************/ -/****************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_semaphore_pointer_convert: - BX LR ;; return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_void_pointer_convert: - BX LR ;; return - - -/*********************************************************************************/ -/*********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ -/** */ -/*********************************************************************************/ -/*********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_ulong_to_thread_pointer_convert: - BX LR ;; return - - -/***************************************************************************************************/ -/***************************************************************************************************/ -/** */ -/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ -/** */ -/***************************************************************************************************/ -/***************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_timer_indirect_to_void_pointer_convert: - BX LR ;; return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_const_char_to_char_pointer_convert: - BX LR ;; return - - -/**********************************************************************************/ -/**********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ -/** */ -/**********************************************************************************/ -/**********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_thread_pointer_convert: - BX LR ;; return - - -#ifdef TX_ENABLE_EVENT_TRACE - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_object_to_uchar_pointer_convert: - BX LR ;; return - - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_object_pointer_convert: - BX LR ;; return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_header_pointer_convert: - BX LR ;; return - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_entry_pointer_convert: - BX LR ;; return - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_entry_to_uchar_pointer_convert: - BX LR ;; return -#endif - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_char_to_uchar_pointer_convert: - BX LR ;; return + BX LR // return /***********************************************************************************************/ @@ -998,7 +686,7 @@ _tx_misra_char_to_uchar_pointer_convert: THUMB _tx_misra_ipsr_get: MRS R0, IPSR - BX LR ;; return + BX LR // return /***********************************************************************************************/ @@ -1013,7 +701,7 @@ _tx_misra_ipsr_get: THUMB _tx_misra_control_get: MRS R0, CONTROL - BX LR ;; return + BX LR // return /***********************************************************************************************/ @@ -1028,7 +716,7 @@ _tx_misra_control_get: THUMB _tx_misra_control_set: MSR CONTROL, R0 - BX LR ;; return + BX LR // return #ifdef __ARMVFP__ @@ -1044,9 +732,9 @@ _tx_misra_control_set: SECTION `.text`:CODE:NOROOT(2) THUMB _tx_misra_fpccr_get: - LDR r0, =0xE000EF34 ; Build FPCCR address - LDR r0, [r0] ; Load FPCCR value - BX LR ;; return + LDR r0, =0xE000EF34 // Build FPCCR address + LDR r0, [r0] // Load FPCCR value + BX LR // return /***********************************************************************************************/ @@ -1061,7 +749,7 @@ _tx_misra_fpccr_get: THUMB _tx_misra_vfp_touch: vmov.f32 s0, s0 - BX LR ;; return + BX LR // return #endif diff --git a/ports/cortex_m4/keil/inc/tx_port.h b/ports/cortex_m4/keil/inc/tx_port.h index 199c876ae..ae7954aaa 100644 --- a/ports/cortex_m4/keil/inc/tx_port.h +++ b/ports/cortex_m4/keil/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/Keil */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -59,6 +59,9 @@ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -146,6 +149,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -707,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/Keil Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/Keil Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m55/ac6/CMakeLists.txt b/ports/cortex_m55/ac6/CMakeLists.txt new file mode 100644 index 000000000..5ad3b8e75 --- /dev/null +++ b/ports/cortex_m55/ac6/CMakeLists.txt @@ -0,0 +1,21 @@ +target_sources(${PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_allocate.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_free.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_disable.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_secure_stack.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_secure_stack_allocate.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_secure_stack_free.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S +) + +target_include_directories(${PROJECT_NAME} PUBLIC + inc +) diff --git a/ports/cortex_m55/ac6/inc/tx_port.h b/ports/cortex_m55/ac6/inc/tx_port.h index 2217150e6..bda877e6e 100644 --- a/ports/cortex_m55/ac6/inc/tx_port.h +++ b/ports/cortex_m55/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M55/AC6 */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -61,16 +61,21 @@ /* added symbol to enable */ /* stack error handler, */ /* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ +/* 10-15-2021 Scott Larson Modified comment(s), improved */ /* stack check error handling, */ /* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ +/* 01-31-2022 Scott Larson Modified comment(s), unified */ /* this file across compilers, */ /* fixed predefined macro, */ /* resulting in version 6.1.10 */ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -188,6 +193,12 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -524,7 +535,7 @@ ULONG _tx_misra_ipsr_get(VOID); #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) /* Initialize secure stacks for threads calling secure functions. */ extern void _tx_thread_secure_stack_initialize(void); -#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to @@ -637,7 +648,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M55/AC6 Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M55/AC6 Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m55/ac6/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m55/ac6/src/tx_thread_secure_stack_initialize.S index 587547979..18d3f158a 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m55/ac6/src/tx_thread_secure_stack_initialize.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M55/AC6 */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -49,13 +49,17 @@ /* */ /* CALLED BY */ /* */ -/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */ +/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ /* RELEASE HISTORY */ /* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports/cortex_m55/gnu/inc/tx_port.h b/ports/cortex_m55/gnu/inc/tx_port.h index f99373f33..eb709b5ab 100644 --- a/ports/cortex_m55/gnu/inc/tx_port.h +++ b/ports/cortex_m55/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M55/GNU */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -61,16 +61,21 @@ /* added symbol to enable */ /* stack error handler, */ /* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ +/* 10-15-2021 Scott Larson Modified comment(s), improved */ /* stack check error handling, */ /* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ +/* 01-31-2022 Scott Larson Modified comment(s), unified */ /* this file across compilers, */ /* fixed predefined macro, */ /* resulting in version 6.1.10 */ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -188,6 +193,12 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -524,7 +535,7 @@ ULONG _tx_misra_ipsr_get(VOID); #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) /* Initialize secure stacks for threads calling secure functions. */ extern void _tx_thread_secure_stack_initialize(void); -#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to @@ -637,7 +648,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M55/GNU Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M55/GNU Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m55/gnu/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m55/gnu/src/tx_thread_secure_stack_initialize.S index 89e4185a9..e5bb784a8 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m55/gnu/src/tx_thread_secure_stack_initialize.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M55/GNU */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -49,13 +49,17 @@ /* */ /* CALLED BY */ /* */ -/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */ +/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ /* RELEASE HISTORY */ /* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports/cortex_m55/iar/inc/tx_port.h b/ports/cortex_m55/iar/inc/tx_port.h index a2919d9bc..cfafe1b54 100644 --- a/ports/cortex_m55/iar/inc/tx_port.h +++ b/ports/cortex_m55/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M55/IAR */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -61,16 +61,21 @@ /* added symbol to enable */ /* stack error handler, */ /* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ +/* 10-15-2021 Scott Larson Modified comment(s), improved */ /* stack check error handling, */ /* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ +/* 01-31-2022 Scott Larson Modified comment(s), unified */ /* this file across compilers, */ /* fixed predefined macro, */ /* resulting in version 6.1.10 */ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -188,6 +193,12 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -524,7 +535,7 @@ ULONG _tx_misra_ipsr_get(VOID); #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) /* Initialize secure stacks for threads calling secure functions. */ extern void _tx_thread_secure_stack_initialize(void); -#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to @@ -637,7 +648,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M55/IAR Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M55/IAR Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m55/iar/src/tx_thread_secure_stack_initialize.s b/ports/cortex_m55/iar/src/tx_thread_secure_stack_initialize.s index 4ad8c1ed8..cc8e8c7bd 100644 --- a/ports/cortex_m55/iar/src/tx_thread_secure_stack_initialize.s +++ b/ports/cortex_m55/iar/src/tx_thread_secure_stack_initialize.s @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M55/IAR */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -50,13 +50,17 @@ /* */ /* CALLED BY */ /* */ -/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */ +/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ /* RELEASE HISTORY */ /* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports/cortex_m7/ac5/inc/tx_port.h b/ports/cortex_m7/ac5/inc/tx_port.h index a0e3d1943..7de2ee6dc 100644 --- a/ports/cortex_m7/ac5/inc/tx_port.h +++ b/ports/cortex_m7/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M7/AC5 */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -59,6 +59,9 @@ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -146,6 +149,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -707,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC5 Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC5 Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m7/ac6/inc/tx_port.h b/ports/cortex_m7/ac6/inc/tx_port.h index cfd833fae..302bbc7d9 100644 --- a/ports/cortex_m7/ac6/inc/tx_port.h +++ b/ports/cortex_m7/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M7/AC6 */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -59,6 +59,9 @@ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -146,6 +149,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -707,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC6 Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC6 Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m7/ac6/src/tx_misra.S b/ports/cortex_m7/ac6/src/tx_misra.S index b03fdcd01..155512be4 100644 --- a/ports/cortex_m7/ac6/src/tx_misra.S +++ b/ports/cortex_m7/ac6/src/tx_misra.S @@ -103,6 +103,14 @@ .global _tx_misra_vfp_touch #endif + .global _tx_misra_event_flags_group_not_used + .global _tx_misra_event_flags_set_notify_not_used + .global _tx_misra_queue_not_used + .global _tx_misra_queue_send_notify_not_used + .global _tx_misra_semaphore_not_used + .global _tx_misra_semaphore_put_notify_not_used + .global _tx_misra_thread_entry_exit_notify_not_used + .global _tx_misra_thread_not_used /**************************************************************************/ /**************************************************************************/ @@ -172,17 +180,93 @@ _tx_misra_uchar_pointer_dif: BX LR // return -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ +/** */ +/** This single function serves all of the below prototypes. */ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** VOID _tx_misra_event_flags_group_not_used(TX_EVENT_FLAGS_GROUP *group_ptr); */ +/** VOID _tx_misra_event_flags_set_notify_not_used(VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); */ +/** VOID _tx_misra_queue_not_used(TX_QUEUE *queue_ptr); */ +/** VOID _tx_misra_queue_send_notify_not_used(VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); */ +/** VOID _tx_misra_semaphore_not_used(TX_SEMAPHORE *semaphore_ptr); */ +/** VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); */ +/** VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr); */ +/** VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)); */ +/** */ +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ .text .thumb_func _tx_misra_pointer_to_ulong_convert: +_tx_misra_ulong_to_pointer_convert: +_tx_misra_indirect_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_indirect_uchar_pointer_convert: +_tx_misra_block_pool_to_uchar_pointer_convert: +_tx_misra_void_to_block_pool_pointer_convert: +_tx_misra_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_block_pool_pointer_convert: +_tx_misra_void_to_indirect_uchar_pointer_convert: +_tx_misra_void_to_byte_pool_pointer_convert: +_tx_misra_byte_pool_to_uchar_pointer_convert: +_tx_misra_uchar_to_align_type_pointer_convert: +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: +_tx_misra_void_to_event_flags_pointer_convert: +_tx_misra_void_to_ulong_pointer_convert: +_tx_misra_void_to_mutex_pointer_convert: +_tx_misra_void_to_queue_pointer_convert: +_tx_misra_void_to_semaphore_pointer_convert: +_tx_misra_uchar_to_void_pointer_convert: +_tx_misra_ulong_to_thread_pointer_convert: +_tx_misra_timer_indirect_to_void_pointer_convert: +_tx_misra_const_char_to_char_pointer_convert: +_tx_misra_void_to_thread_pointer_convert: +#ifdef TX_ENABLE_EVENT_TRACE +_tx_misra_object_to_uchar_pointer_convert: +_tx_misra_uchar_to_object_pointer_convert: +_tx_misra_uchar_to_header_pointer_convert: +_tx_misra_uchar_to_entry_pointer_convert: +_tx_misra_entry_to_uchar_pointer_convert: +#endif +_tx_misra_char_to_uchar_pointer_convert: +_tx_misra_event_flags_group_not_used: +_tx_misra_event_flags_set_notify_not_used: +_tx_misra_queue_not_used: +_tx_misra_queue_send_notify_not_used: +_tx_misra_semaphore_not_used: +_tx_misra_semaphore_put_notify_not_used: +_tx_misra_thread_entry_exit_notify_not_used: +_tx_misra_thread_not_used: + BX LR // return @@ -234,20 +318,6 @@ _tx_misra_ulong_pointer_dif: BX LR // return -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - .text - .thumb_func -_tx_misra_ulong_to_pointer_convert: - BX LR // return - - /**************************************************************************/ /**************************************************************************/ /** */ @@ -332,12 +402,9 @@ _tx_misra_timer_pointer_add: .text .thumb_func _tx_misra_user_timer_pointer_get: - ADDS R2,R0,#+8 - SUBS R2,R2,R0 - RSBS R2,R2,#+0 - ADD R0,R0,R2 - STR R0,[R1, #+0] - BX LR // return + SUBS R0,#8 + STR R0,[R1, #+0] + BX LR // return /**************************************************************************/ @@ -553,202 +620,6 @@ _tx_misra_always_true: BX LR // return -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - .text - .thumb_func -_tx_misra_indirect_void_to_uchar_pointer_convert: - BX LR // return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_indirect_uchar_pointer_convert: - BX LR // return - - -/***********************************************************************************/ -/***********************************************************************************/ -/** */ -/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ -/** */ -/***********************************************************************************/ -/***********************************************************************************/ - - .text - .thumb_func -_tx_misra_block_pool_to_uchar_pointer_convert: - BX LR // return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_block_pool_pointer_convert: - BX LR // return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_uchar_pointer_convert: - BX LR // return - - -/************************************************************************************/ -/************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************/ -/************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_block_pool_pointer_convert: - BX LR // return - - -/**************************************************************************************/ -/**************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************/ -/**************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_indirect_uchar_pointer_convert: - BX LR // return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_byte_pool_pointer_convert: - BX LR // return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - .text - .thumb_func -_tx_misra_byte_pool_to_uchar_pointer_convert: - BX LR // return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_align_type_pointer_convert: - BX LR // return - - -/****************************************************************************************************/ -/****************************************************************************************************/ -/** */ -/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/****************************************************************************************************/ -/****************************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: - BX LR // return - - -/**************************************************************************************************/ -/**************************************************************************************************/ -/** */ -/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************************/ -/**************************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_event_flags_pointer_convert: - BX LR // return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_ulong_pointer_convert: - BX LR // return - - -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_mutex_pointer_convert: - BX LR // return - - /**************************************************************************/ /**************************************************************************/ /** */ @@ -764,191 +635,6 @@ _tx_misra_status_get: BX LR // return -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_queue_pointer_convert: - BX LR // return - - -/****************************************************************************************/ -/****************************************************************************************/ -/** */ -/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ -/** */ -/****************************************************************************************/ -/****************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_semaphore_pointer_convert: - BX LR // return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_void_pointer_convert: - BX LR // return - - -/*********************************************************************************/ -/*********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ -/** */ -/*********************************************************************************/ -/*********************************************************************************/ - - .text - .thumb_func -_tx_misra_ulong_to_thread_pointer_convert: - BX LR // return - - -/***************************************************************************************************/ -/***************************************************************************************************/ -/** */ -/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ -/** */ -/***************************************************************************************************/ -/***************************************************************************************************/ - - .text - .thumb_func -_tx_misra_timer_indirect_to_void_pointer_convert: - BX LR // return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - .text - .thumb_func -_tx_misra_const_char_to_char_pointer_convert: - BX LR // return - - -/**********************************************************************************/ -/**********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ -/** */ -/**********************************************************************************/ -/**********************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_thread_pointer_convert: - BX LR // return - - -#ifdef TX_ENABLE_EVENT_TRACE - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - .text - .thumb_func -_tx_misra_object_to_uchar_pointer_convert: - BX LR // return - - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_object_pointer_convert: - BX LR // return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_header_pointer_convert: - BX LR // return - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_entry_pointer_convert: - BX LR // return - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - .text - .thumb_func -_tx_misra_entry_to_uchar_pointer_convert: - BX LR // return -#endif - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - .text - .thumb_func -_tx_misra_char_to_uchar_pointer_convert: - BX LR // return - - /***********************************************************************************************/ /***********************************************************************************************/ /** */ diff --git a/ports/cortex_m7/gnu/example_build/build_threadx.bat b/ports/cortex_m7/gnu/example_build/build_threadx.bat index f0c995e77..3d92efd3e 100644 --- a/ports/cortex_m7/gnu/example_build/build_threadx.bat +++ b/ports/cortex_m7/gnu/example_build/build_threadx.bat @@ -1,199 +1,198 @@ del tx.a -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb tx_initialize_low_level.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb ../src/tx_thread_stack_build.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb ../src/tx_thread_schedule.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb ../src/tx_thread_system_return.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb ../src/tx_thread_context_save.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb ../src/tx_thread_context_restore.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb ../src/tx_thread_interrupt_control.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb ../src/tx_timer_interrupt.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb ../src/tx_thread_interrupt_control.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb ../src/tx_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb ../src/tx_thread_schedule.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb ../src/tx_thread_system_return.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb ../src/tx_thread_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb ../src/tx_thread_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb ../src/tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb ../src/tx_timer_interrupt.S + +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c + arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o -arm-none-eabi-ar -r tx.a tx_thread_interrupt_control.o tx_initialize_low_level.o arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o diff --git a/ports/cortex_m7/gnu/example_build/build_threadx_sample.bat b/ports/cortex_m7/gnu/example_build/build_threadx_sample.bat index 0e58e9638..52e836bc2 100644 --- a/ports/cortex_m7/gnu/example_build/build_threadx_sample.bat +++ b/ports/cortex_m7/gnu/example_build/build_threadx_sample.bat @@ -1,7 +1,5 @@ -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb tx_simulator_startup.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb cortexm7_crt0.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb tx_initialize_low_level.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc sample_threadx.c -arm-none-eabi-ld -A cortex-m7 -ereset_handler -T sample_threadx.ld tx_simulator_startup.o cortexm7_crt0.o tx_initialize_low_level.o sample_threadx.o tx.a libc.a -o sample_threadx.out -M > sample_threadx.map - - +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb cortexm7_vectors.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb cortexm7_crt0.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -I../../../../common/inc -I../inc sample_threadx.c +arm-none-eabi-gcc -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -T sample_threadx.ld -ereset_handler -nostartfiles -o sample_threadx.out -Wl,-Map=sample_threadx.map cortexm7_vectors.o cortexm7_crt0.o tx_initialize_low_level.o sample_threadx.o tx.a diff --git a/ports/cortex_m7/gnu/example_build/cortexm7_crt0.S b/ports/cortex_m7/gnu/example_build/cortexm7_crt0.S new file mode 100644 index 000000000..4228fc110 --- /dev/null +++ b/ports/cortex_m7/gnu/example_build/cortexm7_crt0.S @@ -0,0 +1,91 @@ + .syntax unified + .section .init, "ax" + .code 16 + .align 2 + .thumb_func + + .global _start +_start: + CPSID i + ldr r1, =__stack_end__ + mov sp, r1 + + /* Copy initialised sections into RAM if required. */ + ldr r0, =__data_load_start__ + ldr r1, =__data_start__ + ldr r2, =__data_end__ + bl crt0_memory_copy + + /* Zero bss. */ + ldr r0, =__bss_start__ + ldr r1, =__bss_end__ + mov r2, #0 + bl crt0_memory_set + + /* Setup heap - not recommended for Threadx but here for compatibility reasons */ + ldr r0, = __heap_start__ + ldr r1, = __heap_end__ + sub r1, r1, r0 + mov r2, #0 + str r2, [r0] + add r0, r0, #4 + str r1, [r0] + + /* constructors in case of using C++ */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ +crt0_ctor_loop: + cmp r0, r1 + beq crt0_ctor_end + ldr r2, [r0] + add r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b crt0_ctor_loop +crt0_ctor_end: + + /* Setup call frame for main() */ + mov r0, #0 + mov lr, r0 + mov r12, sp + +start: + /* Jump to main() */ + mov r0, #0 + mov r1, #0 + ldr r2, =main + blx r2 + /* when main returns, loop forever. */ +crt0_exit_loop: + b crt0_exit_loop + + /* Startup helper functions. */ + +crt0_memory_copy: + cmp r0, r1 + beq memory_copy_done +memory_copy_loop: + ldrb r3, [r0] + add r0, r0, #1 + strb r3, [r1] + add r1, r1, #1 + cmp r1, r2 + bne memory_copy_loop +memory_copy_done: + bx lr + +crt0_memory_set: + cmp r0, r1 + beq memory_set_done + strb r2, [r0] + add r0, r0, #1 + b crt0_memory_set +memory_set_done: + bx lr + + /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */ + .section .stack, "wa", %nobits + .section .stack_process, "wa", %nobits + .section .heap, "wa", %nobits + \ No newline at end of file diff --git a/ports/cortex_m0/gnu/example_build/tx_vectors.s b/ports/cortex_m7/gnu/example_build/cortexm7_vectors.S similarity index 78% rename from ports/cortex_m0/gnu/example_build/tx_vectors.s rename to ports/cortex_m7/gnu/example_build/cortexm7_vectors.S index 55395cd10..6ae558e4d 100644 --- a/ports/cortex_m0/gnu/example_build/tx_vectors.s +++ b/ports/cortex_m7/gnu/example_build/cortexm7_vectors.S @@ -1,5 +1,3 @@ - - .global reset_handler .global __tx_NMIHandler @@ -9,8 +7,6 @@ .global __tx_PendSVHandler .global __tx_SysTickHandler .global __tx_BadHandler - .global __tx_HardfaultHandler - .syntax unified .section .vectors, "ax" @@ -30,7 +26,7 @@ _vectors: .word 0 // Reserved .word 0 // Reserved .word 0 // Reserved - .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // + .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved .word __tx_PendSVHandler @@ -71,32 +67,11 @@ _vectors: .word __tx_BadHandler .word __tx_BadHandler - - - .section .init, "ax" - .thumb_func + .section .init, "ax" + .thumb_func reset_handler: - -// low level hardware config, such as PLL setup goes here - + // low level hardware config, such as PLL setup goes here b _start - .text 32 - .align 4 - .syntax unified - - -__tx_NMIHandler: - b __tx_NMIHandler - -__tx_BadHandler: - b __tx_BadHandler - -__tx_DBGHandler: - b __tx_DBGHandler - -__tx_HardfaultHandler: - b __tx_HardfaultHandler - diff --git a/ports/cortex_m7/gnu/example_build/sample_threadx.ld b/ports/cortex_m7/gnu/example_build/sample_threadx.ld index 28f203fdf..c65a13464 100644 --- a/ports/cortex_m7/gnu/example_build/sample_threadx.ld +++ b/ports/cortex_m7/gnu/example_build/sample_threadx.ld @@ -1,206 +1,125 @@ MEMORY { - UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0 - CM3_System_Control_Space (wx) : ORIGIN = 0xe000e000, LENGTH = 0x00001000 - AHB_Peripherals (wx) : ORIGIN = 0x50000000, LENGTH = 0x00200000 - APB1_Peripherals (wx) : ORIGIN = 0x40080000, LENGTH = 0x00080000 - APB0_Peripherals (wx) : ORIGIN = 0x40000000, LENGTH = 0x00080000 - GPIO (wx) : ORIGIN = 0x2009c000, LENGTH = 0x00004000 - AHBSRAM1 (wx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 - AHBSRAM0 (wx) : ORIGIN = 0x2007c000, LENGTH = 0x00004000 - RAM (wx) : ORIGIN = 0x10000000, LENGTH = 0x00008000 - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + RAM (wx) : ORIGIN = 0x20000000, LENGTH = 0x00800000 + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00400000 } +__STACKSIZE__ = 1024; +__STACKSIZE_PROCESS__ = 0; +__HEAPSIZE__ = 128; SECTIONS { - __CM3_System_Control_Space_segment_start__ = 0xe000e000; - __CM3_System_Control_Space_segment_end__ = 0xe000f000; - __AHB_Peripherals_segment_start__ = 0x50000000; - __AHB_Peripherals_segment_end__ = 0x50200000; - __APB1_Peripherals_segment_start__ = 0x40080000; - __APB1_Peripherals_segment_end__ = 0x40100000; - __APB0_Peripherals_segment_start__ = 0x40000000; - __APB0_Peripherals_segment_end__ = 0x40080000; - __GPIO_segment_start__ = 0x2009c000; - __GPIO_segment_end__ = 0x200a0000; - __AHBSRAM1_segment_start__ = 0x20080000; - __AHBSRAM1_segment_end__ = 0x20084000; - __AHBSRAM0_segment_start__ = 0x2007c000; - __AHBSRAM0_segment_end__ = 0x20080000; - __RAM_segment_start__ = 0x10000000; - __RAM_segment_end__ = 0x10008000; - __FLASH_segment_start__ = 0x00000000; - __FLASH_segment_end__ = 0x00080000; - - __STACKSIZE__ = 1024; - __STACKSIZE_PROCESS__ = 0; - __STACKSIZE_IRQ__ = 0; - __STACKSIZE_FIQ__ = 0; - __STACKSIZE_SVC__ = 0; - __STACKSIZE_ABT__ = 0; - __STACKSIZE_UND__ = 0; - __HEAPSIZE__ = 128; - - __vectors_load_start__ = __FLASH_segment_start__; - .vectors __FLASH_segment_start__ : AT(__FLASH_segment_start__) + .vectors : { - __vectors_start__ = .; - *(.vectors .vectors.*) - } - __vectors_end__ = __vectors_start__ + SIZEOF(.vectors); - - . = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .vectors is too large to fit in FLASH memory segment"); - - __init_load_start__ = ALIGN(__vectors_end__ , 4); - .init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4)) - { - __init_start__ = .; - *(.init .init.*) - } - __init_end__ = __init_start__ + SIZEOF(.init); - - . = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .init is too large to fit in FLASH memory segment"); - - __text_load_start__ = ALIGN(__init_end__ , 4); - .text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4)) - { - __text_start__ = .; - *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table) - } - __text_end__ = __text_start__ + SIZEOF(.text); - - . = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .text is too large to fit in FLASH memory segment"); - - __dtors_load_start__ = ALIGN(__text_end__ , 4); - .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4)) - { - __dtors_start__ = .; - KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) - } - __dtors_end__ = __dtors_start__ + SIZEOF(.dtors); - - . = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .dtors is too large to fit in FLASH memory segment"); - - __ctors_load_start__ = ALIGN(__dtors_end__ , 4); - .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4)) - { - __ctors_start__ = .; - KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) - } - __ctors_end__ = __ctors_start__ + SIZEOF(.ctors); - - . = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .ctors is too large to fit in FLASH memory segment"); - - __rodata_load_start__ = ALIGN(__ctors_end__ , 4); - .rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4)) - { - __rodata_start__ = .; - *(.rodata .rodata.* .gnu.linkonce.r.*) - } - __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - - . = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .rodata is too large to fit in FLASH memory segment"); - - __fast_load_start__ = ALIGN(__rodata_end__ , 4); - .fast ALIGN(__RAM_segment_start__ , 4) : AT(ALIGN(__rodata_end__ , 4)) - { - __fast_start__ = .; - *(.fast .fast.*) - } - __fast_end__ = __fast_start__ + SIZEOF(.fast); - - __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast); - - . = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00080000) , "error: .fast is too large to fit in FLASH memory segment"); - - .fast_run ALIGN(__RAM_segment_start__ , 4) (NOLOAD) : - { - __fast_run_start__ = .; - . = MAX(__fast_run_start__ + SIZEOF(.fast), .); - } - __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run); - - . = ASSERT(__fast_run_end__ >= __RAM_segment_start__ && __fast_run_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .fast_run is too large to fit in RAM memory segment"); - - __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4); - .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4)) - { - __data_start__ = .; - *(.data .data.* .gnu.linkonce.d.*) - } - __data_end__ = __data_start__ + SIZEOF(.data); - - __data_load_end__ = __data_load_start__ + SIZEOF(.data); - - __FLASH_segment_used_end__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4) + SIZEOF(.data); - - . = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00080000) , "error: .data is too large to fit in FLASH memory segment"); - - .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) : - { - __data_run_start__ = .; - . = MAX(__data_run_start__ + SIZEOF(.data), .); - } - __data_run_end__ = __data_run_start__ + SIZEOF(.data_run); - - . = ASSERT(__data_run_end__ >= __RAM_segment_start__ && __data_run_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .data_run is too large to fit in RAM memory segment"); - - __bss_load_start__ = ALIGN(__data_run_end__ , 4); - .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4)) - { - __bss_start__ = .; - *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) - } - __bss_end__ = __bss_start__ + SIZEOF(.bss); - - . = ASSERT(__bss_end__ >= __RAM_segment_start__ && __bss_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .bss is too large to fit in RAM memory segment"); - - __non_init_load_start__ = ALIGN(__bss_end__ , 4); - .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4)) - { - __non_init_start__ = .; - *(.non_init .non_init.*) - } - __non_init_end__ = __non_init_start__ + SIZEOF(.non_init); - - . = ASSERT(__non_init_end__ >= __RAM_segment_start__ && __non_init_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .non_init is too large to fit in RAM memory segment"); - - __heap_load_start__ = ALIGN(__non_init_end__ , 4); - .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4)) - { - __heap_start__ = .; + KEEP(*(.vectors .vectors.*)) + } > FLASH + + .text : + { + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + __ctors_start__ = ALIGN(4); + *(SORT(.ctors.*)) + *(.ctors) + __ctors_end__ = ALIGN(4); + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + __dtors_start__ = ALIGN(4); + *(SORT(.dtors.*)) + *(.dtors) + __dtors_end__ = ALIGN(4); + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __data_load_start__ = ALIGN (4); + + .data : AT (__data_load_start__) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + + } > RAM + + .heap (COPY): + { + __heap_start__ = ALIGN(4); *(.heap) - . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4); - } - __heap_end__ = __heap_start__ + SIZEOF(.heap); - - . = ASSERT(__heap_end__ >= __RAM_segment_start__ && __heap_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .heap is too large to fit in RAM memory segment"); + . = ALIGN(. + __HEAPSIZE__, 4); + __heap_end__ = ALIGN(4); + } > RAM - __stack_load_start__ = ALIGN(__heap_end__ , 4); - .stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4)) + .stack ALIGN(4) (NOLOAD) : { - __stack_start__ = .; + __stack_start__ = ALIGN(4); *(.stack) - . = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4); - } - __stack_end__ = __stack_start__ + SIZEOF(.stack); - - . = ASSERT(__stack_end__ >= __RAM_segment_start__ && __stack_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .stack is too large to fit in RAM memory segment"); - - __stack_process_load_start__ = ALIGN(__stack_end__ , 4); - .stack_process ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4)) - { - __stack_process_start__ = .; - *(.stack_process) - . = ALIGN(MAX(__stack_process_start__ + __STACKSIZE_PROCESS__ , .), 4); - } - __stack_process_end__ = __stack_process_start__ + SIZEOF(.stack_process); - - __RAM_segment_used_end__ = ALIGN(__stack_end__ , 4) + SIZEOF(.stack_process); - - . = ASSERT(__stack_process_end__ >= __RAM_segment_start__ && __stack_process_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .stack_process is too large to fit in RAM memory segment"); + . = ALIGN(. + __STACKSIZE__, 4); + __stack_end__ = ALIGN(4); + } > RAM + __RAM_segment_used_end__ = .; } - diff --git a/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S index 85e612a67..c84822e6c 100644 --- a/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S @@ -1,226 +1,201 @@ -@/**************************************************************************/ -@/* */ -@/* Copyright (c) Microsoft Corporation. All rights reserved. */ -@/* */ -@/* This software is licensed under the Microsoft Software License */ -@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -@/* and in the root directory of this software. */ -@/* */ -@/**************************************************************************/ -@ -@ -@/**************************************************************************/ -@/**************************************************************************/ -@/** */ -@/** ThreadX Component */ -@/** */ -@/** Initialize */ -@/** */ -@/**************************************************************************/ -@/**************************************************************************/ -@ -@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + .global _tx_thread_system_stack_ptr .global _tx_initialize_unused_memory .global __RAM_segment_used_end__ .global _tx_timer_interrupt .global __main - .global __tx_SVCallHandler - .global __tx_PendSVHandler .global _vectors - .global __tx_NMIHandler @ NMI - .global __tx_BadHandler @ HardFault - .global __tx_SVCallHandler @ SVCall - .global __tx_DBGHandler @ Monitor - .global __tx_PendSVHandler @ PendSV - .global __tx_SysTickHandler @ SysTick - .global __tx_IntHandler @ Int 0 -@ -@ + .global __tx_NMIHandler // NMI + .global __tx_BadHandler // HardFault + .global __tx_SVCallHandler // SVCall + .global __tx_DBGHandler // Monitor + .global __tx_PendSVHandler // PendSV + .global __tx_SysTickHandler // SysTick + .global __tx_IntHandler // Int 0 + SYSTEM_CLOCK = 6000000 SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) .text 32 .align 4 .syntax unified -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_initialize_low_level Cortex-M7/GNU */ -@/* 6.1 */ -@/* AUTHOR */ -@/* */ -@/* William E. Lamie, Microsoft Corporation */ -@/* */ -@/* DESCRIPTION */ -@/* */ -@/* This function is responsible for any low-level processor */ -@/* initialization, including setting up interrupt vectors, setting */ -@/* up a periodic timer interrupt source, saving the system stack */ -@/* pointer for use in ISR processing later, and finding the first */ -@/* available RAM memory address for tx_application_define. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 09-30-2020 William E. Lamie Modified Comment(s), fixed */ -@/* GNU assembly comment, clean */ -@/* up whitespace, resulting */ -@/* in version 6.1 */ -@/* */ -@/**************************************************************************/ -@VOID _tx_initialize_low_level(VOID) -@{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M7/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified Comment(s), fixed */ +/* GNU assembly comment, clean */ +/* up whitespace, resulting */ +/* in version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { .global _tx_initialize_low_level .thumb_func _tx_initialize_low_level: -@ -@ /* Disable interrupts during ThreadX initialization. */ -@ + + /* Disable interrupts during ThreadX initialization. */ CPSID i -@ -@ /* Set base of available memory to end of non-initialised RAM area. */ -@ - LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer - LDR r1, =__RAM_segment_used_end__ @ Build first free address - ADD r1, r1, #4 @ - STR r1, [r0] @ Setup first unused memory pointer -@ -@ /* Setup Vector Table Offset Register. */ -@ - MOV r0, #0xE000E000 @ Build address of NVIC registers - LDR r1, =_vectors @ Pickup address of vector table - STR r1, [r0, #0xD08] @ Set vector table address -@ -@ /* Set system stack pointer from vector value. */ -@ - LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer - LDR r1, =_vectors @ Pickup address of vector table - LDR r1, [r1] @ Pickup reset stack pointer - STR r1, [r0] @ Save system stack pointer -@ -@ /* Enable the cycle count register. */ -@ - LDR r0, =0xE0001000 @ Build address of DWT register - LDR r1, [r0] @ Pickup the current value - ORR r1, r1, #1 @ Set the CYCCNTENA bit - STR r1, [r0] @ Enable the cycle count register -@ -@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ -@ - MOV r0, #0xE000E000 @ Build address of NVIC registers + + /* Set base of available memory to end of non-initialised RAM area. */ + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =__RAM_segment_used_end__ // Build first free address + ADD r1, r1, #4 // + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =_vectors // Pickup address of vector table + STR r1, [r0, #0xD08] // Set vector table address + + /* Set system stack pointer from vector value. */ + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =_vectors // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Enable the cycle count register. */ + LDR r0, =0xE0001000 // Build address of DWT register + LDR r1, [r0] // Pickup the current value + ORR r1, r1, #1 // Set the CYCCNTENA bit + STR r1, [r0] // Enable the cycle count register + + /* Configure SysTick. */ + MOV r0, #0xE000E000 // Build address of NVIC registers LDR r1, =SYSTICK_CYCLES - STR r1, [r0, #0x14] @ Setup SysTick Reload Value - MOV r1, #0x7 @ Build SysTick Control Enable Value - STR r1, [r0, #0x10] @ Setup SysTick Control -@ -@ /* Configure handler priorities. */ -@ - LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM - STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers - - LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv - STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers - @ Note: SVC must be lowest priority, which is 0xFF - - LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM - STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers - @ Note: PnSV must be lowest priority, which is 0xFF -@ -@ /* Return to caller. */ -@ + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOV r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control + + /* Configure handler priorities. */ + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF + + /* Return to caller. */ BX lr -@} -@ +// } -@/* Define shells for each of the unused vectors. */ -@ +/* Define shells for each of the unused vectors. */ .global __tx_BadHandler .thumb_func __tx_BadHandler: B __tx_BadHandler -@ /* added to catch the hardfault */ - +/* added to catch the hardfault */ .global __tx_HardfaultHandler .thumb_func __tx_HardfaultHandler: B __tx_HardfaultHandler - -@ /* added to catch the SVC */ - +/* added to catch the SVC */ .global __tx_SVCallHandler .thumb_func __tx_SVCallHandler: B __tx_SVCallHandler - -@ /* Generic interrupt handler template */ +/* Generic interrupt handler template */ .global __tx_IntHandler .thumb_func __tx_IntHandler: -@ VOID InterruptHandler (VOID) -@ { +// VOID InterruptHandler (VOID) +// { PUSH {r0, lr} #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_enter @ Call the ISR enter function + BL _tx_execution_isr_enter // Call the ISR enter function #endif - -@ /* Do interrupt handler work here */ -@ /* BL .... */ - + /* Do interrupt handler work here */ + /* BL .... */ #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_exit @ Call the ISR exit function + BL _tx_execution_isr_exit // Call the ISR exit function #endif POP {r0, lr} BX LR -@ } +// } -@ /* System Tick timer interrupt handler */ +/* System Tick timer interrupt handler */ .global __tx_SysTickHandler .global SysTick_Handler .thumb_func __tx_SysTickHandler: .thumb_func SysTick_Handler: -@ VOID TimerInterruptHandler (VOID) -@ { -@ +// VOID SysTick_Handler (VOID) +// { PUSH {r0, lr} #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_enter @ Call the ISR enter function + BL _tx_execution_isr_enter // Call the ISR enter function #endif BL _tx_timer_interrupt #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_exit @ Call the ISR exit function + BL _tx_execution_isr_exit // Call the ISR exit function #endif POP {r0, lr} - BX LR -@ } - + BX lr +// } -@ /* NMI, DBG handlers */ +/* NMI, DBG handlers */ .global __tx_NMIHandler .thumb_func __tx_NMIHandler: diff --git a/ports/cortex_m7/gnu/inc/tx_port.h b/ports/cortex_m7/gnu/inc/tx_port.h index 9a88b1d88..7d14ac82d 100644 --- a/ports/cortex_m7/gnu/inc/tx_port.h +++ b/ports/cortex_m7/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M7/GNU */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -59,6 +59,9 @@ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -146,6 +149,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -707,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/GNU Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/GNU Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m7/gnu/src/tx_misra.S b/ports/cortex_m7/gnu/src/tx_misra.S index b03fdcd01..155512be4 100644 --- a/ports/cortex_m7/gnu/src/tx_misra.S +++ b/ports/cortex_m7/gnu/src/tx_misra.S @@ -103,6 +103,14 @@ .global _tx_misra_vfp_touch #endif + .global _tx_misra_event_flags_group_not_used + .global _tx_misra_event_flags_set_notify_not_used + .global _tx_misra_queue_not_used + .global _tx_misra_queue_send_notify_not_used + .global _tx_misra_semaphore_not_used + .global _tx_misra_semaphore_put_notify_not_used + .global _tx_misra_thread_entry_exit_notify_not_used + .global _tx_misra_thread_not_used /**************************************************************************/ /**************************************************************************/ @@ -172,17 +180,93 @@ _tx_misra_uchar_pointer_dif: BX LR // return -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ +/** */ +/** This single function serves all of the below prototypes. */ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** VOID _tx_misra_event_flags_group_not_used(TX_EVENT_FLAGS_GROUP *group_ptr); */ +/** VOID _tx_misra_event_flags_set_notify_not_used(VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); */ +/** VOID _tx_misra_queue_not_used(TX_QUEUE *queue_ptr); */ +/** VOID _tx_misra_queue_send_notify_not_used(VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); */ +/** VOID _tx_misra_semaphore_not_used(TX_SEMAPHORE *semaphore_ptr); */ +/** VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); */ +/** VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr); */ +/** VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)); */ +/** */ +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ .text .thumb_func _tx_misra_pointer_to_ulong_convert: +_tx_misra_ulong_to_pointer_convert: +_tx_misra_indirect_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_indirect_uchar_pointer_convert: +_tx_misra_block_pool_to_uchar_pointer_convert: +_tx_misra_void_to_block_pool_pointer_convert: +_tx_misra_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_block_pool_pointer_convert: +_tx_misra_void_to_indirect_uchar_pointer_convert: +_tx_misra_void_to_byte_pool_pointer_convert: +_tx_misra_byte_pool_to_uchar_pointer_convert: +_tx_misra_uchar_to_align_type_pointer_convert: +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: +_tx_misra_void_to_event_flags_pointer_convert: +_tx_misra_void_to_ulong_pointer_convert: +_tx_misra_void_to_mutex_pointer_convert: +_tx_misra_void_to_queue_pointer_convert: +_tx_misra_void_to_semaphore_pointer_convert: +_tx_misra_uchar_to_void_pointer_convert: +_tx_misra_ulong_to_thread_pointer_convert: +_tx_misra_timer_indirect_to_void_pointer_convert: +_tx_misra_const_char_to_char_pointer_convert: +_tx_misra_void_to_thread_pointer_convert: +#ifdef TX_ENABLE_EVENT_TRACE +_tx_misra_object_to_uchar_pointer_convert: +_tx_misra_uchar_to_object_pointer_convert: +_tx_misra_uchar_to_header_pointer_convert: +_tx_misra_uchar_to_entry_pointer_convert: +_tx_misra_entry_to_uchar_pointer_convert: +#endif +_tx_misra_char_to_uchar_pointer_convert: +_tx_misra_event_flags_group_not_used: +_tx_misra_event_flags_set_notify_not_used: +_tx_misra_queue_not_used: +_tx_misra_queue_send_notify_not_used: +_tx_misra_semaphore_not_used: +_tx_misra_semaphore_put_notify_not_used: +_tx_misra_thread_entry_exit_notify_not_used: +_tx_misra_thread_not_used: + BX LR // return @@ -234,20 +318,6 @@ _tx_misra_ulong_pointer_dif: BX LR // return -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - .text - .thumb_func -_tx_misra_ulong_to_pointer_convert: - BX LR // return - - /**************************************************************************/ /**************************************************************************/ /** */ @@ -332,12 +402,9 @@ _tx_misra_timer_pointer_add: .text .thumb_func _tx_misra_user_timer_pointer_get: - ADDS R2,R0,#+8 - SUBS R2,R2,R0 - RSBS R2,R2,#+0 - ADD R0,R0,R2 - STR R0,[R1, #+0] - BX LR // return + SUBS R0,#8 + STR R0,[R1, #+0] + BX LR // return /**************************************************************************/ @@ -553,202 +620,6 @@ _tx_misra_always_true: BX LR // return -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - .text - .thumb_func -_tx_misra_indirect_void_to_uchar_pointer_convert: - BX LR // return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_indirect_uchar_pointer_convert: - BX LR // return - - -/***********************************************************************************/ -/***********************************************************************************/ -/** */ -/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ -/** */ -/***********************************************************************************/ -/***********************************************************************************/ - - .text - .thumb_func -_tx_misra_block_pool_to_uchar_pointer_convert: - BX LR // return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_block_pool_pointer_convert: - BX LR // return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_uchar_pointer_convert: - BX LR // return - - -/************************************************************************************/ -/************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************/ -/************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_block_pool_pointer_convert: - BX LR // return - - -/**************************************************************************************/ -/**************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************/ -/**************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_indirect_uchar_pointer_convert: - BX LR // return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_byte_pool_pointer_convert: - BX LR // return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - .text - .thumb_func -_tx_misra_byte_pool_to_uchar_pointer_convert: - BX LR // return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_align_type_pointer_convert: - BX LR // return - - -/****************************************************************************************************/ -/****************************************************************************************************/ -/** */ -/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/****************************************************************************************************/ -/****************************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: - BX LR // return - - -/**************************************************************************************************/ -/**************************************************************************************************/ -/** */ -/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************************/ -/**************************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_event_flags_pointer_convert: - BX LR // return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_ulong_pointer_convert: - BX LR // return - - -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_mutex_pointer_convert: - BX LR // return - - /**************************************************************************/ /**************************************************************************/ /** */ @@ -764,191 +635,6 @@ _tx_misra_status_get: BX LR // return -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_queue_pointer_convert: - BX LR // return - - -/****************************************************************************************/ -/****************************************************************************************/ -/** */ -/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ -/** */ -/****************************************************************************************/ -/****************************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_semaphore_pointer_convert: - BX LR // return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_void_pointer_convert: - BX LR // return - - -/*********************************************************************************/ -/*********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ -/** */ -/*********************************************************************************/ -/*********************************************************************************/ - - .text - .thumb_func -_tx_misra_ulong_to_thread_pointer_convert: - BX LR // return - - -/***************************************************************************************************/ -/***************************************************************************************************/ -/** */ -/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ -/** */ -/***************************************************************************************************/ -/***************************************************************************************************/ - - .text - .thumb_func -_tx_misra_timer_indirect_to_void_pointer_convert: - BX LR // return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - .text - .thumb_func -_tx_misra_const_char_to_char_pointer_convert: - BX LR // return - - -/**********************************************************************************/ -/**********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ -/** */ -/**********************************************************************************/ -/**********************************************************************************/ - - .text - .thumb_func -_tx_misra_void_to_thread_pointer_convert: - BX LR // return - - -#ifdef TX_ENABLE_EVENT_TRACE - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - .text - .thumb_func -_tx_misra_object_to_uchar_pointer_convert: - BX LR // return - - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_object_pointer_convert: - BX LR // return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_header_pointer_convert: - BX LR // return - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - .text - .thumb_func -_tx_misra_uchar_to_entry_pointer_convert: - BX LR // return - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - .text - .thumb_func -_tx_misra_entry_to_uchar_pointer_convert: - BX LR // return -#endif - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - .text - .thumb_func -_tx_misra_char_to_uchar_pointer_convert: - BX LR // return - - /***********************************************************************************************/ /***********************************************************************************************/ /** */ diff --git a/ports/cortex_m7/iar/CMakeLists.txt b/ports/cortex_m7/iar/CMakeLists.txt new file mode 100644 index 000000000..a524d79f0 --- /dev/null +++ b/ports/cortex_m7/iar/CMakeLists.txt @@ -0,0 +1,21 @@ + +target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} + ${CMAKE_CURRENT_LIST_DIR}/src/tx_iar.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_disable.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S + # {{END_TARGET_SOURCES}} +) + +target_include_directories(${PROJECT_NAME} + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/inc +) diff --git a/ports/cortex_m7/iar/inc/tx_port.h b/ports/cortex_m7/iar/inc/tx_port.h index f11ff9a9c..191ad569e 100644 --- a/ports/cortex_m7/iar/inc/tx_port.h +++ b/ports/cortex_m7/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M7/IAR */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -59,6 +59,9 @@ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -146,6 +149,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -707,7 +716,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/IAR Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/IAR Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m7/iar/src/tx_misra.s b/ports/cortex_m7/iar/src/tx_misra.s index 2add69b34..c81c3e5cc 100644 --- a/ports/cortex_m7/iar/src/tx_misra.s +++ b/ports/cortex_m7/iar/src/tx_misra.s @@ -102,6 +102,16 @@ PUBLIC _tx_misra_fpccr_get PUBLIC _tx_misra_vfp_touch #endif + + PUBLIC _tx_misra_event_flags_group_not_used + PUBLIC _tx_misra_event_flags_set_notify_not_used + PUBLIC _tx_misra_queue_not_used + PUBLIC _tx_misra_queue_send_notify_not_used + PUBLIC _tx_misra_semaphore_not_used + PUBLIC _tx_misra_semaphore_put_notify_not_used + PUBLIC _tx_misra_thread_entry_exit_notify_not_used + PUBLIC _tx_misra_thread_not_used + PUBLIC _tx_version_id @@ -115,7 +125,7 @@ _tx_version_id: DC8 45H, 78H, 70H, 72H, 65H, 73H, 73H, 20H DC8 4CH, 6FH, 67H, 69H, 63H, 20H, 49H, 6EH DC8 63H, 2EH, 20H, 2AH, 20H, 54H, 68H, 72H - DC8 65H, 61H, 64H, 58H, 20H, 35H, 2EH, 38H + DC8 65H, 61H, 64H, 58H, 20H, 36H, 2EH, 31H DC8 20H, 4DH, 49H, 53H, 52H, 41H, 20H, 43H DC8 20H, 43H, 6FH, 6DH, 70H, 6CH, 69H, 61H DC8 6EH, 74H, 20H, 2AH, 0 @@ -139,7 +149,7 @@ _tx_misra_memset: MOVS R1,R0 MOVS R0,R4 BL __aeabi_memset - POP {R4,PC} ;; return + POP {R4,PC} // return /**************************************************************************/ /**************************************************************************/ @@ -153,7 +163,7 @@ _tx_misra_memset: THUMB _tx_misra_uchar_pointer_add: ADD R0,R0,R1 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -169,7 +179,7 @@ _tx_misra_uchar_pointer_add: _tx_misra_uchar_pointer_sub: RSBS R1,R1,#+0 ADD R0,R0,R1 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -184,21 +194,97 @@ _tx_misra_uchar_pointer_sub: THUMB _tx_misra_uchar_pointer_dif: SUBS R0,R0,R1 - BX LR ;; return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - + BX LR // return + + +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ +/** */ +/** This single function serves all of the below prototypes. */ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** VOID _tx_misra_event_flags_group_not_used(TX_EVENT_FLAGS_GROUP *group_ptr); */ +/** VOID _tx_misra_event_flags_set_notify_not_used(VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); */ +/** VOID _tx_misra_queue_not_used(TX_QUEUE *queue_ptr); */ +/** VOID _tx_misra_queue_send_notify_not_used(VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); */ +/** VOID _tx_misra_semaphore_not_used(TX_SEMAPHORE *semaphore_ptr); */ +/** VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); */ +/** VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr); */ +/** VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)); */ +/** */ +/************************************************************************************************************************************/ +/************************************************************************************************************************************/ SECTION `.text`:CODE:NOROOT(1) THUMB _tx_misra_pointer_to_ulong_convert: - BX LR ;; return +_tx_misra_ulong_to_pointer_convert: +_tx_misra_indirect_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_indirect_uchar_pointer_convert: +_tx_misra_block_pool_to_uchar_pointer_convert: +_tx_misra_void_to_block_pool_pointer_convert: +_tx_misra_void_to_uchar_pointer_convert: +_tx_misra_uchar_to_block_pool_pointer_convert: +_tx_misra_void_to_indirect_uchar_pointer_convert: +_tx_misra_void_to_byte_pool_pointer_convert: +_tx_misra_byte_pool_to_uchar_pointer_convert: +_tx_misra_uchar_to_align_type_pointer_convert: +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: +_tx_misra_void_to_event_flags_pointer_convert: +_tx_misra_void_to_ulong_pointer_convert: +_tx_misra_void_to_mutex_pointer_convert: +_tx_misra_void_to_queue_pointer_convert: +_tx_misra_void_to_semaphore_pointer_convert: +_tx_misra_uchar_to_void_pointer_convert: +_tx_misra_ulong_to_thread_pointer_convert: +_tx_misra_timer_indirect_to_void_pointer_convert: +_tx_misra_const_char_to_char_pointer_convert: +_tx_misra_void_to_thread_pointer_convert: +#ifdef TX_ENABLE_EVENT_TRACE +_tx_misra_object_to_uchar_pointer_convert: +_tx_misra_uchar_to_object_pointer_convert: +_tx_misra_uchar_to_header_pointer_convert: +_tx_misra_uchar_to_entry_pointer_convert: +_tx_misra_entry_to_uchar_pointer_convert: +#endif +_tx_misra_char_to_uchar_pointer_convert: +_tx_misra_event_flags_group_not_used: +_tx_misra_event_flags_set_notify_not_used: +_tx_misra_queue_not_used: +_tx_misra_queue_send_notify_not_used: +_tx_misra_semaphore_not_used: +_tx_misra_semaphore_put_notify_not_used: +_tx_misra_thread_entry_exit_notify_not_used: +_tx_misra_thread_not_used: + + BX LR // return /**************************************************************************/ @@ -213,7 +299,7 @@ _tx_misra_pointer_to_ulong_convert: THUMB _tx_misra_ulong_pointer_add: ADD R0,R0,R1, LSL #+2 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -230,7 +316,7 @@ _tx_misra_ulong_pointer_sub: MVNS R2,#+3 MULS R1,R2,R1 ADD R0,R0,R1 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -246,21 +332,7 @@ _tx_misra_ulong_pointer_sub: _tx_misra_ulong_pointer_dif: SUBS R0,R0,R1 ASRS R0,R0,#+2 - BX LR ;; return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_ulong_to_pointer_convert: - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -299,7 +371,7 @@ _tx_misra_message_copy: STR R3,[R0, #+0] STR R4,[R1, #+0] POP {R4,R5} - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -316,7 +388,7 @@ _tx_misra_message_copy: _tx_misra_timer_pointer_dif: SUBS R0,R0,R1 ASRS R0,R0,#+2 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -332,7 +404,7 @@ _tx_misra_timer_pointer_dif: THUMB _tx_misra_timer_pointer_add: ADD R0,R0,R1, LSL #+2 - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -347,12 +419,9 @@ _tx_misra_timer_pointer_add: SECTION `.text`:CODE:NOROOT(1) THUMB _tx_misra_user_timer_pointer_get: - ADDS R2,R0,#+8 - SUBS R2,R2,R0 - RSBS R2,R2,#+0 - ADD R0,R0,R2 - STR R0,[R1, #+0] - BX LR ;; return + SUBS R0,#8 + STR R0,[R1, #+0] + BX LR // return /**************************************************************************/ @@ -374,7 +443,7 @@ _tx_misra_thread_stack_check: CMP R4,#+0 BEQ.N ??_tx_misra_thread_stack_check_0 LDR R1,[R4, #+0] - LDR.N R2,??DataTable2 ;; 0x54485244 + LDR.N R2,??DataTable2 // 0x54485244 CMP R1,R2 BNE.N ??_tx_misra_thread_stack_check_0 LDR R1,[R4, #+8] @@ -412,7 +481,7 @@ _tx_misra_thread_stack_check: BL _tx_thread_interrupt_disable ??_tx_misra_thread_stack_check_0: BL _tx_thread_interrupt_restore - POP {R0,R4,R5,PC} ;; return + POP {R0,R4,R5,PC} // return #ifdef TX_ENABLE_EVENT_TRACE @@ -500,7 +569,7 @@ _tx_misra_trace_event_insert: LDR R0,[R0, #+0] STR R4,[R0, #+32] ??_tx_misra_trace_event_insert_0: - POP {R0,R4-R7,PC} ;; return + POP {R0,R4-R7,PC} // return SECTION `.text`:CODE:NOROOT(2) @@ -552,7 +621,7 @@ _tx_misra_trace_event_insert: THUMB _tx_misra_time_stamp_get: MOVS R0,#+0 - BX LR ;; return + BX LR // return #endif @@ -587,203 +656,7 @@ _tx_misra_time_stamp_get: THUMB _tx_misra_always_true: MOVS R0,#+1 - BX LR ;; return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_indirect_void_to_uchar_pointer_convert: - BX LR ;; return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_indirect_uchar_pointer_convert: - BX LR ;; return - - -/***********************************************************************************/ -/***********************************************************************************/ -/** */ -/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ -/** */ -/***********************************************************************************/ -/***********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_block_pool_to_uchar_pointer_convert: - BX LR ;; return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_block_pool_pointer_convert: - BX LR ;; return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_uchar_pointer_convert: - BX LR ;; return - - -/************************************************************************************/ -/************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************/ -/************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_block_pool_pointer_convert: - BX LR ;; return - - -/**************************************************************************************/ -/**************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************/ -/**************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_indirect_uchar_pointer_convert: - BX LR ;; return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_byte_pool_pointer_convert: - BX LR ;; return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_byte_pool_to_uchar_pointer_convert: - BX LR ;; return - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_align_type_pointer_convert: - BX LR ;; return - - -/****************************************************************************************************/ -/****************************************************************************************************/ -/** */ -/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/****************************************************************************************************/ -/****************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: - BX LR ;; return - - -/**************************************************************************************************/ -/**************************************************************************************************/ -/** */ -/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************************/ -/**************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_event_flags_pointer_convert: - BX LR ;; return - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_ulong_pointer_convert: - BX LR ;; return - - -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_mutex_pointer_convert: - BX LR ;; return + BX LR // return /**************************************************************************/ @@ -798,192 +671,7 @@ _tx_misra_void_to_mutex_pointer_convert: THUMB _tx_misra_status_get: MOVS R0,#+0 - BX LR ;; return - - -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_queue_pointer_convert: - BX LR ;; return - - -/****************************************************************************************/ -/****************************************************************************************/ -/** */ -/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ -/** */ -/****************************************************************************************/ -/****************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_semaphore_pointer_convert: - BX LR ;; return - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_void_pointer_convert: - BX LR ;; return - - -/*********************************************************************************/ -/*********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ -/** */ -/*********************************************************************************/ -/*********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_ulong_to_thread_pointer_convert: - BX LR ;; return - - -/***************************************************************************************************/ -/***************************************************************************************************/ -/** */ -/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ -/** */ -/***************************************************************************************************/ -/***************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_timer_indirect_to_void_pointer_convert: - BX LR ;; return - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_const_char_to_char_pointer_convert: - BX LR ;; return - - -/**********************************************************************************/ -/**********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ -/** */ -/**********************************************************************************/ -/**********************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_void_to_thread_pointer_convert: - BX LR ;; return - - -#ifdef TX_ENABLE_EVENT_TRACE - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_object_to_uchar_pointer_convert: - BX LR ;; return - - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_object_pointer_convert: - BX LR ;; return - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_header_pointer_convert: - BX LR ;; return - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_uchar_to_entry_pointer_convert: - BX LR ;; return - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_entry_to_uchar_pointer_convert: - BX LR ;; return -#endif - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ - - SECTION `.text`:CODE:NOROOT(1) - THUMB -_tx_misra_char_to_uchar_pointer_convert: - BX LR ;; return + BX LR // return /***********************************************************************************************/ @@ -998,7 +686,7 @@ _tx_misra_char_to_uchar_pointer_convert: THUMB _tx_misra_ipsr_get: MRS R0, IPSR - BX LR ;; return + BX LR // return /***********************************************************************************************/ @@ -1013,7 +701,7 @@ _tx_misra_ipsr_get: THUMB _tx_misra_control_get: MRS R0, CONTROL - BX LR ;; return + BX LR // return /***********************************************************************************************/ @@ -1028,7 +716,7 @@ _tx_misra_control_get: THUMB _tx_misra_control_set: MSR CONTROL, R0 - BX LR ;; return + BX LR // return #ifdef __ARMVFP__ @@ -1044,9 +732,9 @@ _tx_misra_control_set: SECTION `.text`:CODE:NOROOT(2) THUMB _tx_misra_fpccr_get: - LDR r0, =0xE000EF34 ; Build FPCCR address - LDR r0, [r0] ; Load FPCCR value - BX LR ;; return + LDR r0, =0xE000EF34 // Build FPCCR address + LDR r0, [r0] // Load FPCCR value + BX LR // return /***********************************************************************************************/ @@ -1061,7 +749,7 @@ _tx_misra_fpccr_get: THUMB _tx_misra_vfp_touch: vmov.f32 s0, s0 - BX LR ;; return + BX LR // return #endif diff --git a/ports/cortex_m85/ac6/CMakeLists.txt b/ports/cortex_m85/ac6/CMakeLists.txt new file mode 100644 index 000000000..5ad3b8e75 --- /dev/null +++ b/ports/cortex_m85/ac6/CMakeLists.txt @@ -0,0 +1,21 @@ +target_sources(${PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_allocate.c + ${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_free.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_disable.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_secure_stack.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_secure_stack_allocate.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_secure_stack_free.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S +) + +target_include_directories(${PROJECT_NAME} PUBLIC + inc +) diff --git a/ports/cortex_m85/ac6/inc/tx_port.h b/ports/cortex_m85/ac6/inc/tx_port.h index 0a556b701..91348fb4a 100644 --- a/ports/cortex_m85/ac6/inc/tx_port.h +++ b/ports/cortex_m85/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M85/AC6 */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -61,16 +61,21 @@ /* added symbol to enable */ /* stack error handler, */ /* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ +/* 10-15-2021 Scott Larson Modified comment(s), improved */ /* stack check error handling, */ /* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ +/* 01-31-2022 Scott Larson Modified comment(s), unified */ /* this file across compilers, */ /* fixed predefined macro, */ /* resulting in version 6.1.10 */ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -188,6 +193,12 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -524,7 +535,7 @@ ULONG _tx_misra_ipsr_get(VOID); #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) /* Initialize secure stacks for threads calling secure functions. */ extern void _tx_thread_secure_stack_initialize(void); -#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to @@ -637,7 +648,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M85/AC6 Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M85/AC6 Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m85/ac6/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m85/ac6/src/tx_thread_secure_stack_initialize.S index 6a24afac0..0509420c7 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m85/ac6/src/tx_thread_secure_stack_initialize.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M85/AC6 */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -49,13 +49,17 @@ /* */ /* CALLED BY */ /* */ -/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */ +/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ /* RELEASE HISTORY */ /* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports/cortex_m85/gnu/inc/tx_port.h b/ports/cortex_m85/gnu/inc/tx_port.h index 0cf16cd55..69cdc5f65 100644 --- a/ports/cortex_m85/gnu/inc/tx_port.h +++ b/ports/cortex_m85/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M85/GNU */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -61,16 +61,21 @@ /* added symbol to enable */ /* stack error handler, */ /* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ +/* 10-15-2021 Scott Larson Modified comment(s), improved */ /* stack check error handling, */ /* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ +/* 01-31-2022 Scott Larson Modified comment(s), unified */ /* this file across compilers, */ /* fixed predefined macro, */ /* resulting in version 6.1.10 */ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -188,6 +193,12 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -524,7 +535,7 @@ ULONG _tx_misra_ipsr_get(VOID); #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) /* Initialize secure stacks for threads calling secure functions. */ extern void _tx_thread_secure_stack_initialize(void); -#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to @@ -637,7 +648,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M85/GNU Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M85/GNU Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m85/gnu/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m85/gnu/src/tx_thread_secure_stack_initialize.S index f84f6029d..8afc3bcc5 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m85/gnu/src/tx_thread_secure_stack_initialize.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M85/GNU */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -49,13 +49,17 @@ /* */ /* CALLED BY */ /* */ -/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */ +/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ /* RELEASE HISTORY */ /* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports/cortex_m85/iar/inc/tx_port.h b/ports/cortex_m85/iar/inc/tx_port.h index d02272c72..1161d44b7 100644 --- a/ports/cortex_m85/iar/inc/tx_port.h +++ b/ports/cortex_m85/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M85/IAR */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -61,16 +61,21 @@ /* added symbol to enable */ /* stack error handler, */ /* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ +/* 10-15-2021 Scott Larson Modified comment(s), improved */ /* stack check error handling, */ /* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ +/* 01-31-2022 Scott Larson Modified comment(s), unified */ /* this file across compilers, */ /* fixed predefined macro, */ /* resulting in version 6.1.10 */ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -188,6 +193,12 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -524,7 +535,7 @@ ULONG _tx_misra_ipsr_get(VOID); #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) /* Initialize secure stacks for threads calling secure functions. */ extern void _tx_thread_secure_stack_initialize(void); -#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to @@ -637,7 +648,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M85/IAR Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M85/IAR Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m85/iar/src/tx_thread_secure_stack_initialize.s b/ports/cortex_m85/iar/src/tx_thread_secure_stack_initialize.s index de2df1c13..20f51ad62 100644 --- a/ports/cortex_m85/iar/src/tx_thread_secure_stack_initialize.s +++ b/ports/cortex_m85/iar/src/tx_thread_secure_stack_initialize.s @@ -27,7 +27,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M85/IAR */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -50,13 +50,17 @@ /* */ /* CALLED BY */ /* */ -/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */ +/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ /* RELEASE HISTORY */ /* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports/cortex_r4/gnu/inc/tx_port.h b/ports/cortex_r4/gnu/inc/tx_port.h index 8d84beac4..c69fa2989 100644 --- a/ports/cortex_r4/gnu/inc/tx_port.h +++ b/ports/cortex_r4/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R4/GNU */ -/* 6.1.6 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -47,10 +47,13 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ /* macro definition, */ /* resulting in version 6.1.6 */ +/* 07-29-2022 Scott Larson Updated comments, removed */ +/* unneeded temp variable, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -282,7 +285,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #else -#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); diff --git a/ports/cortex_r5/ac6/inc/tx_port.h b/ports/cortex_r5/ac6/inc/tx_port.h index 213773d01..7eccfe75e 100644 --- a/ports/cortex_r5/ac6/inc/tx_port.h +++ b/ports/cortex_r5/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R5/AC6 */ -/* 6.1.6 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -47,10 +47,13 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ /* macro definition, */ /* resulting in version 6.1.6 */ +/* 07-29-2022 Scott Larson Updated comments, removed */ +/* unneeded temp variable, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -282,7 +285,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #else -#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); diff --git a/ports/cortex_r5/gnu/inc/tx_port.h b/ports/cortex_r5/gnu/inc/tx_port.h index 7de3df7a1..d477c1882 100644 --- a/ports/cortex_r5/gnu/inc/tx_port.h +++ b/ports/cortex_r5/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R5/GNU */ -/* 6.1.6 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -47,10 +47,13 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ /* macro definition, */ /* resulting in version 6.1.6 */ +/* 07-29-2022 Scott Larson Updated comments, removed */ +/* unneeded temp variable, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -282,7 +285,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #else -#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); diff --git a/ports_module/cortex_a7/ac5/example_build/build_threadx_demo.bat b/ports_module/cortex_a7/ac5/example_build/build_threadx_demo.bat new file mode 100644 index 000000000..032a2195f --- /dev/null +++ b/ports_module/cortex_a7/ac5/example_build/build_threadx_demo.bat @@ -0,0 +1,3 @@ +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork tx_initialize_low_level.s +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc sample_threadx.c +armlink -d -o sample_threadx_module_manager.axf --elf --ro 0x80000000 --first tx_initialize_low_level.o(VECTORS) --remove --map --symbols --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S index 8ccb9f7a1..0e0c8f671 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M0+/AC6 */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -65,6 +65,9 @@ /* 01-31-2022 Scott Larson Initial Version 6.1.10 */ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -345,17 +348,6 @@ __tx_ts_restore: CMP r2, #0 BEQ skip_mpu_setup // Is protection required for this module? No, skip MPU setup - // Is the MPU already set up for this module? - MOVS r1, #5 // Select region 5 from MPU - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 5 - LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 5 - MOVS r6, #0x10 - BICS r2, r2, r6 // Clear VALID bit - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration - // Initialize loop to configure MPU registers MOVS r3, #0x64 // Index of MPU register settings in thread control block ADD r0, r0, r3 // Build address of MPU register start in thread control block diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S index f1f5872bf..7e613c25e 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M0+/GNU */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -65,6 +65,9 @@ /* 01-31-2022 Scott Larson Initial Version 6.1.10 */ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -345,17 +348,6 @@ __tx_ts_restore: CMP r2, #0 BEQ skip_mpu_setup // Is protection required for this module? No, skip MPU setup - // Is the MPU already set up for this module? - MOVS r1, #5 // Select region 5 from MPU - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 5 - LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 5 - MOVS r6, #0x10 - BICS r2, r2, r6 // Clear VALID bit - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration - // Initialize loop to configure MPU registers MOVS r3, #0x64 // Index of MPU register settings in thread control block ADD r0, r0, r3 // Build address of MPU register start in thread control block diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S index bc4982101..af30dffae 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M0+/IAR */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -72,6 +72,9 @@ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* change handler name, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -330,17 +333,6 @@ __tx_ts_restore: CMP r2, #0 BEQ skip_mpu_setup // Is protection required for this module? No, skip MPU setup - // Is the MPU already set up for this module? - MOVS r1, #5 // Select region 5 from MPU - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 5 - LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 5 - MOVS r6, #0x10 - BICS r2, r2, r6 // Clear VALID bit - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration - // Initialize loop to configure MPU registers MOVS r3, #0x64 // Index of MPU register settings in thread control block ADD r0, r0, r3 // Build address of MPU register start in thread control block diff --git a/ports_module/cortex_m23/ac6/inc/tx_port.h b/ports_module/cortex_m23/ac6/inc/tx_port.h index b3c3d99b7..ae6e2c50f 100644 --- a/ports_module/cortex_m23/ac6/inc/tx_port.h +++ b/ports_module/cortex_m23/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M23/AC6 */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -51,6 +51,10 @@ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -507,7 +511,7 @@ ULONG _tx_misra_ipsr_get(VOID); #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) /* Initialize secure stacks for threads calling secure functions. */ extern void _tx_thread_secure_stack_initialize(void); -#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to @@ -573,7 +577,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/AC6 Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/AC6 Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m23/ac6/inc/txm_module_port.h b/ports_module/cortex_m23/ac6/inc/txm_module_port.h index ec0093277..72bc525b3 100644 --- a/ports_module/cortex_m23/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m23/ac6/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M23/AC6 */ -/* 6.1.10 */ +/* 6.1.10 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ diff --git a/ports_module/cortex_m23/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m23/ac6/module_lib/src/txm_module_thread_shell_entry.c index ca2a267df..6f4451b0a 100644 --- a/ports_module/cortex_m23/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m23/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -58,7 +58,7 @@ extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top); /* FUNCTION RELEASE */ /* */ /* _txm_module_thread_shell_entry Cortex-M23/AC6 */ -/* 6.1.10 */ +/* 6.1.10 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S index 09d4658f9..69e8a192a 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M23/AC6 */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -65,6 +65,9 @@ /* 04-02-2021 Scott Larson Initial Version 6.1.6 */ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -379,15 +382,6 @@ _skip_secure_restore: LDR r2, [r0, r2] // Pickup MPU data region address CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup - // Is the MPU already set up for this module? - MOVS r1, #2 // Select MPU region 2 - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 2 - LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 2 - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration - // Initialize loop to configure MPU registers MOVS r3, #0x64 // Index of MPU register settings in thread control block ADD r0, r0, r3 // Build address of MPU register start in thread control block diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c index 8941a7058..f10967625 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c @@ -23,7 +23,7 @@ #include "tx_api.h" -/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, +/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, no secure stack functionality is needed. */ #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) @@ -45,8 +45,14 @@ #define TX_THREAD_STACK_SEAL_SIZE 8 #define TX_THREAD_STACK_SEAL_VALUE 0xFEF5EDA5 -/* Secure stack info struct to hold stack start, stack limit, - current stack pointer, and pointer to owning thread. +/* max number of Secure context */ +#ifndef TX_MAX_SECURE_CONTEXTS +#define TX_MAX_SECURE_CONTEXTS 32 +#endif +#define TX_INVALID_SECURE_CONTEXT_IDX (-1) + +/* Secure stack info struct to hold stack start, stack limit, + current stack pointer, and pointer to owning thread. This will be allocated for each thread with a secure stack. */ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT { @@ -54,8 +60,14 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */ VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */ TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */ + INT tx_next_free_index; /* Next free index of free secure context */ } TX_THREAD_SECURE_STACK_INFO; +/* Static secure contexts */ +static TX_THREAD_SECURE_STACK_INFO tx_thread_secure_context[TX_MAX_SECURE_CONTEXTS]; +/* Head of free secure context */ +static INT tx_head_free_index = 0U; + /**************************************************************************/ @@ -63,7 +75,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_initialize Cortex-M23/AC6 */ -/* 6.1.8 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -98,16 +110,20 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ -/* 08-02-2021 Scott Larson Modified comment(s), and */ +/* 06-02-2021 Scott Larson Modified comment(s), and */ /* changed name, execute in */ /* handler mode, */ -/* resulting in version 6.1.8 */ +/* resulting in version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) { UINT status; +INT index; /* Make sure function is called from interrupt (threads should not call). */ if (__get_IPSR() == 0) @@ -118,12 +134,26 @@ UINT status; { /* Set secure mode to use PSP. */ __set_CONTROL(__get_CONTROL() | 2); - + /* Set process stack pointer and stack limit to 0 to throw exception when a thread without a secure stack calls a secure function that tries to use secure stack. */ __set_PSPLIM(0); __set_PSP(0); - + + for (index = 0; index < TX_MAX_SECURE_CONTEXTS; index++) + { + + /* Check last index and mark next free to invalid index */ + if(index == (TX_MAX_SECURE_CONTEXTS - 1)) + { + tx_thread_secure_context[index].tx_next_free_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + else + { + tx_thread_secure_context[index].tx_next_free_index = index + 1; + } + } + status = TX_SUCCESS; } return status; @@ -136,7 +166,7 @@ UINT status; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_allocate Cortex-M23/AC6 */ -/* 6.1.1 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -160,9 +190,7 @@ UINT status; /* CALLS */ /* */ /* __get_IPSR Intrinsic to get IPSR */ -/* calloc Compiler's calloc function */ /* malloc Compiler's malloc function */ -/* free Compiler's free() function */ /* __set_PSPLIM Intrinsic to set PSP limit */ /* __set_PSP Intrinsic to set PSP */ /* __TZ_get_PSPLIM_NS Intrinsic to get NS PSP */ @@ -179,18 +207,22 @@ UINT status; /* 10-16-2020 Scott Larson Modified comment(s), */ /* added stack sealing, */ /* resulting in version 6.1.1 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; UCHAR *stack_mem; -ULONG sp; +INT secure_context_index; status = TX_SUCCESS; - + /* Make sure function is called from interrupt (threads should not call). */ if (__get_IPSR() == 0) { @@ -200,23 +232,38 @@ ULONG sp; { status = TX_SIZE_ERROR; } - + /* Check if thread already has secure stack allocated. */ else if (thread_ptr -> tx_thread_secure_stack_context != 0) { status = TX_THREAD_ERROR; } - + else { - /* Allocate space for secure stack info. */ - info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO)); - - if(info_ptr != TX_NULL) + TX_DISABLE + + /* Allocate free index for secure stack info. */ + if(tx_head_free_index != TX_INVALID_SECURE_CONTEXT_IDX) + { + secure_context_index = tx_head_free_index; + tx_head_free_index = tx_thread_secure_context[tx_head_free_index].tx_next_free_index; + tx_thread_secure_context[secure_context_index].tx_next_free_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + else + { + secure_context_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + + TX_RESTORE + + if(secure_context_index != TX_INVALID_SECURE_CONTEXT_IDX) { + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* If stack info allocated, allocate a stack & seal. */ stack_mem = malloc(stack_size + TX_THREAD_STACK_SEAL_SIZE); - + if(stack_mem != TX_NULL) { /* Secure stack has been allocated, save in the stack info struct. */ @@ -224,38 +271,41 @@ ULONG sp; info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size; info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start; info_ptr -> tx_thread_ptr = thread_ptr; - + /* Seal bottom of stack. */ *(ULONG*)info_ptr -> tx_thread_secure_stack_start = TX_THREAD_STACK_SEAL_VALUE; - - /* Save info pointer in thread. */ - thread_ptr -> tx_thread_secure_stack_context = info_ptr; - - /* Check if this thread is running by looking at PSP_NS and seeing if it is within - the stack_start and stack_end range. */ - sp = __TZ_get_PSP_NS(); - if(sp > ((ULONG) thread_ptr -> tx_thread_stack_start) && sp < ((ULONG) thread_ptr -> tx_thread_stack_end)) + + /* Save secure context id (i.e non-zero base index) in thread. */ + thread_ptr -> tx_thread_secure_stack_context = (VOID *)(secure_context_index + 1); + + /* Check if this thread is running by looking at its stack start and PSPLIM_NS */ + if(((ULONG) thread_ptr -> tx_thread_stack_start & 0xFFFFFFF8) == __TZ_get_PSPLIM_NS()) { /* If this thread is running, set Secure PSP and PSPLIM. */ __set_PSPLIM((ULONG)(info_ptr -> tx_thread_secure_stack_limit)); __set_PSP((ULONG)(info_ptr -> tx_thread_secure_stack_ptr)); } } - + else { + TX_DISABLE + /* Stack not allocated, free the info struct. */ - free(info_ptr); + tx_thread_secure_context[secure_context_index].tx_next_free_index = tx_head_free_index; + tx_head_free_index = secure_context_index; + TX_RESTORE + status = TX_NO_MEMORY; } } - + else { status = TX_NO_MEMORY; } } - + return(status); } @@ -266,7 +316,7 @@ ULONG sp; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_free Cortex-M23/AC6 */ -/* 6.1.1 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -301,44 +351,65 @@ ULONG sp; /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; +INT secure_context_index; status = TX_SUCCESS; - - /* Pickup stack info from thread. */ - info_ptr = thread_ptr -> tx_thread_secure_stack_context; - + + /* Pickup stack info id from thread. */ + secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; + /* Make sure function is called from interrupt (threads should not call). */ if (__get_IPSR() == 0) { status = TX_CALLER_ERROR; } - - /* Check that this secure context is for this thread. */ - else if (info_ptr -> tx_thread_ptr != thread_ptr) + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) { status = TX_THREAD_ERROR; } - else { - - /* Free secure stack. */ - free(info_ptr -> tx_thread_secure_stack_limit); - - /* Free info struct. */ - free(info_ptr); - - /* Clear secure context from thread. */ - thread_ptr -> tx_thread_secure_stack_context = 0; + + /* Pickup stack info from static array of secure contexts. */ + info_ptr = &tx_thread_secure_context[secure_context_index]; + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Free secure stack. */ + free(info_ptr -> tx_thread_secure_stack_limit); + + TX_DISABLE + + /* Free info struct. */ + tx_thread_secure_context[secure_context_index].tx_next_free_index = tx_head_free_index; + tx_head_free_index = secure_context_index; + TX_RESTORE + + /* Clear secure context from thread. */ + thread_ptr -> tx_thread_secure_stack_context = 0; + } } - + return(status); } @@ -349,7 +420,7 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_save Cortex-M23/AC6 */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -386,6 +457,9 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr; /* resulting in version 6.1.1 */ /* 06-02-2021 Scott Larson Fix stack pointer save, */ /* resulting in version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) @@ -393,38 +467,45 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; +INT secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { return; } - + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) + { + return; + } + /* Pickup the secure context pointer. */ - info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); - + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* Check that this secure context is for this thread. */ if (info_ptr -> tx_thread_ptr != thread_ptr) { return; } - + /* Check that stack pointer is in range */ sp = __get_PSP(); - if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || + if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start)) { return; } - + /* Save stack pointer. */ info_ptr -> tx_thread_secure_stack_ptr = (VOID *) sp; - + /* Set process stack pointer and stack limit to 0 to throw exception when a thread without a secure stack calls a secure function that tries to use secure stack. */ __set_PSPLIM(0); __set_PSP(0); - + return; } @@ -435,7 +516,7 @@ ULONG sp; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_restore Cortex-M23/AC6 */ -/* 6.1.1 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -469,32 +550,42 @@ ULONG sp; /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; +INT secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { return; } - + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) + { + return; + } + /* Pickup the secure context pointer. */ - info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); - + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* Check that this secure context is for this thread. */ if (info_ptr -> tx_thread_ptr != thread_ptr) { return; } - + /* Set stack pointer and limit. */ __set_PSPLIM((ULONG)info_ptr -> tx_thread_secure_stack_limit); __set_PSP ((ULONG)info_ptr -> tx_thread_secure_stack_ptr); - + return; } diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_initialize.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_initialize.S index c2f9bf319..bada32cee 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_initialize.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_initialize.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M23/AC6 */ -/* 6.1.8 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -49,13 +49,17 @@ /* */ /* CALLED BY */ /* */ -/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */ +/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ /* RELEASE HISTORY */ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_handler.c b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_handler.c deleted file mode 100644 index 8e3cff23e..000000000 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_handler.c +++ /dev/null @@ -1,93 +0,0 @@ -/**************************************************************************/ -/* */ -/* Copyright (c) Microsoft Corporation. All rights reserved. */ -/* */ -/* This software is licensed under the Microsoft Software License */ -/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -/* and in the root directory of this software. */ -/* */ -/**************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Thread */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - -#define TX_SOURCE_CODE - - -/* Include necessary system files. */ - -#include "tx_api.h" -#include "tx_thread.h" - -/* Define the global function pointer for stack error handling. If a stack error is - detected and the application has registered a stack error handler, it will be - called via this function pointer. */ - -VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_stack_error_handler Cortex-M23 */ -/* 6.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function processes stack errors detected during run-time. */ -/* */ -/* */ -/* INPUT */ -/* */ -/* thread_ptr Thread control block pointer */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_terminate */ -/* _tx_thread_application_stack_error_handler */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX internal code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ -/**************************************************************************/ -VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) -{ - #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR - /* Is there a thread? */ - if (thread_ptr) - { - /* Terminate the current thread. */ - _tx_thread_terminate(_tx_thread_current_ptr); - } - #endif - - /* Determine if the application has registered an error handler. */ - if (_tx_thread_application_stack_error_handler != TX_NULL) - { - /* Yes, an error handler is present, simply call the application error handler. */ - (_tx_thread_application_stack_error_handler)(thread_ptr); - } -} diff --git a/ports_module/cortex_m23/gnu/inc/tx_port.h b/ports_module/cortex_m23/gnu/inc/tx_port.h index 42486b174..330d08e27 100644 --- a/ports_module/cortex_m23/gnu/inc/tx_port.h +++ b/ports_module/cortex_m23/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M23/GNU */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -61,6 +61,10 @@ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -385,7 +389,7 @@ ULONG _tx_misra_ipsr_get(VOID); #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) /* Initialize secure stacks for threads calling secure functions. */ extern void _tx_thread_secure_stack_initialize(void); -#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to @@ -484,7 +488,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/GNU Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/GNU Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S index 7b640e6f6..439a96c05 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M23/GNU */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,6 +61,9 @@ /* 04-02-2021 Scott Larson Initial Version 6.1.6 */ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -375,15 +378,6 @@ _skip_secure_restore: LDR r2, [r0, r2] // Pickup MPU data region address CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup - // Is the MPU already set up for this module? - MOVS r1, #2 // Select MPU region 2 - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 2 - LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 2 - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration - // Initialize loop to configure MPU registers MOVS r3, #0x64 // Index of MPU register settings in thread control block ADD r0, r0, r3 // Build address of MPU register start in thread control block diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c index 8f22bb905..ac7c70a56 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c @@ -23,7 +23,7 @@ #include "tx_api.h" -/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, +/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, no secure stack functionality is needed. */ #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) @@ -44,8 +44,14 @@ #define TX_THREAD_STACK_SEAL_SIZE 8 #define TX_THREAD_STACK_SEAL_VALUE 0xFEF5EDA5 -/* Secure stack info struct to hold stack start, stack limit, - current stack pointer, and pointer to owning thread. +/* max number of Secure context */ +#ifndef TX_MAX_SECURE_CONTEXTS +#define TX_MAX_SECURE_CONTEXTS 32 +#endif +#define TX_INVALID_SECURE_CONTEXT_IDX (-1) + +/* Secure stack info struct to hold stack start, stack limit, + current stack pointer, and pointer to owning thread. This will be allocated for each thread with a secure stack. */ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT { @@ -53,8 +59,14 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */ VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */ TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */ + INT tx_next_free_index; /* Next free index of free secure context */ } TX_THREAD_SECURE_STACK_INFO; +/* Static secure contexts */ +static TX_THREAD_SECURE_STACK_INFO tx_thread_secure_context[TX_MAX_SECURE_CONTEXTS]; +/* Head of free secure context */ +static INT tx_head_free_index = 0U; + /**************************************************************************/ @@ -62,7 +74,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_initialize Cortex-M23/GNU */ -/* 6.1.8 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -94,10 +106,13 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ -/* 08-02-2021 Scott Larson Modified comment(s), changed */ +/* 06-02-2021 Scott Larson Modified comment(s), changed */ /* name, execute in handler */ /* mode, disable optimization, */ -/* resulting in version 6.1.8 */ +/* resulting in version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry, optimize(0))) @@ -106,6 +121,7 @@ UINT _tx_thread_secure_mode_stack_initialize(void) UINT status; ULONG control; ULONG ipsr; +INT index; /* Make sure function is called from interrupt (threads should not call). */ asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ @@ -119,12 +135,26 @@ ULONG ipsr; asm volatile("MRS %0, CONTROL" : "=r" (control)); /* Get CONTROL register. */ control |= 2; /* Use PSP. */ asm volatile("MSR CONTROL, %0" :: "r" (control)); /* Set CONTROL register. */ - + /* Set process stack pointer and stack limit to 0 to throw exception when a thread without a secure stack calls a secure function that tries to use secure stack. */ asm volatile("MSR PSPLIM, %0" :: "r" (0)); asm volatile("MSR PSP, %0" :: "r" (0)); - + + for (index = 0; index < TX_MAX_SECURE_CONTEXTS; index++) + { + + /* Check last index and mark next free to invalid index */ + if(index == (TX_MAX_SECURE_CONTEXTS - 1)) + { + tx_thread_secure_context[index].tx_next_free_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + else + { + tx_thread_secure_context[index].tx_next_free_index = index + 1; + } + } + status = TX_SUCCESS; } return status; @@ -137,7 +167,7 @@ ULONG ipsr; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_allocate Cortex-M23/GNU */ -/* 6.1.3 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -160,9 +190,7 @@ ULONG ipsr; /* */ /* CALLS */ /* */ -/* calloc Compiler's calloc function */ /* malloc Compiler's malloc function */ -/* free Compiler's free() function */ /* */ /* CALLED BY */ /* */ @@ -179,20 +207,26 @@ ULONG ipsr; /* 12-31-2020 Scott Larson Modified comment(s), and */ /* fixed M23 GCC build, */ /* resulting in version 6.1.3 */ - +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* added */ +/* TX_INTERRUPT_SAVE_AREA, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; UCHAR *stack_mem; ULONG ipsr; ULONG psplim_ns; +INT secure_context_index; status = TX_SUCCESS; - + /* Make sure function is called from interrupt (threads should not call). */ asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ if (ipsr == 0) @@ -203,23 +237,38 @@ ULONG psplim_ns; { status = TX_SIZE_ERROR; } - + /* Check if thread already has secure stack allocated. */ else if (thread_ptr -> tx_thread_secure_stack_context != 0) { status = TX_THREAD_ERROR; } - + else { - /* Allocate space for secure stack info. */ - info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO)); - - if(info_ptr != TX_NULL) + TX_DISABLE + + /* Allocate free index for secure stack info. */ + if(tx_head_free_index != TX_INVALID_SECURE_CONTEXT_IDX) + { + secure_context_index = tx_head_free_index; + tx_head_free_index = tx_thread_secure_context[tx_head_free_index].tx_next_free_index; + tx_thread_secure_context[secure_context_index].tx_next_free_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + else + { + secure_context_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + + TX_RESTORE + + if(secure_context_index != TX_INVALID_SECURE_CONTEXT_IDX) { + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* If stack info allocated, allocate a stack & seal. */ stack_mem = malloc(stack_size + TX_THREAD_STACK_SEAL_SIZE); - + if(stack_mem != TX_NULL) { /* Secure stack has been allocated, save in the stack info struct. */ @@ -227,13 +276,13 @@ ULONG psplim_ns; info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size; info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start; info_ptr -> tx_thread_ptr = thread_ptr; - + /* Seal bottom of stack. */ *(ULONG*)info_ptr -> tx_thread_secure_stack_start = TX_THREAD_STACK_SEAL_VALUE; - - /* Save info pointer in thread. */ - thread_ptr -> tx_thread_secure_stack_context = info_ptr; - + + /* Save secure context id (i.e non-zero base index) in thread. */ + thread_ptr -> tx_thread_secure_stack_context = (VOID *)(secure_context_index + 1); + /* Check if this thread is running by looking at its stack start and PSPLIM_NS */ asm volatile("MRS %0, PSPLIM_NS" : "=r" (psplim_ns)); /* Get PSPLIM_NS register. */ if(((ULONG) thread_ptr -> tx_thread_stack_start & 0xFFFFFFF8) == psplim_ns) @@ -243,21 +292,26 @@ ULONG psplim_ns; asm volatile("MSR PSP, %0" :: "r" ((ULONG)(info_ptr -> tx_thread_secure_stack_ptr))); } } - + else { + TX_DISABLE + /* Stack not allocated, free the info struct. */ - free(info_ptr); + tx_thread_secure_context[secure_context_index].tx_next_free_index = tx_head_free_index; + tx_head_free_index = secure_context_index; + TX_RESTORE + status = TX_NO_MEMORY; } } - + else { status = TX_NO_MEMORY; } } - + return(status); } @@ -268,7 +322,7 @@ ULONG psplim_ns; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_free Cortex-M23/GNU */ -/* 6.1.3 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -305,46 +359,67 @@ ULONG psplim_ns; /* 12-31-2020 Scott Larson Modified comment(s), and */ /* fixed M23 GCC build, */ /* resulting in version 6.1.3 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG ipsr; +INT secure_context_index; status = TX_SUCCESS; - - /* Pickup stack info from thread. */ - info_ptr = thread_ptr -> tx_thread_secure_stack_context; - + + /* Pickup stack info id from thread. */ + secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; + /* Make sure function is called from interrupt (threads should not call). */ asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ if (ipsr == 0) { status = TX_CALLER_ERROR; } - - /* Check that this secure context is for this thread. */ - else if (info_ptr -> tx_thread_ptr != thread_ptr) + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) { status = TX_THREAD_ERROR; } - else { - - /* Free secure stack. */ - free(info_ptr -> tx_thread_secure_stack_limit); - - /* Free info struct. */ - free(info_ptr); - - /* Clear secure context from thread. */ - thread_ptr -> tx_thread_secure_stack_context = 0; + + /* Pickup stack info from static array of secure contexts. */ + info_ptr = &tx_thread_secure_context[secure_context_index]; + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Free secure stack. */ + free(info_ptr -> tx_thread_secure_stack_limit); + + TX_DISABLE + + /* Free info struct. */ + tx_thread_secure_context[secure_context_index].tx_next_free_index = tx_head_free_index; + tx_head_free_index = secure_context_index; + TX_RESTORE + + /* Clear secure context from thread. */ + thread_ptr -> tx_thread_secure_stack_context = 0; + } } - + return(status); } @@ -355,7 +430,7 @@ ULONG ipsr; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_save Cortex-M23/GNU */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -392,6 +467,9 @@ ULONG ipsr; /* resulting in version 6.1.3 */ /* 06-02-2021 Scott Larson Fix stack pointer save, */ /* resulting in version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) @@ -400,6 +478,7 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; ULONG ipsr; +INT secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; /* This function should be called from scheduler only. */ asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ @@ -407,32 +486,38 @@ ULONG ipsr; { return; } - + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) + { + return; + } + /* Pickup the secure context pointer. */ - info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); - + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* Check that this secure context is for this thread. */ if (info_ptr -> tx_thread_ptr != thread_ptr) { return; } - + /* Check that stack pointer is in range */ asm volatile("MRS %0, PSP" : "=r" (sp)); /* Get PSP register. */ - if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || + if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start)) { return; } - + /* Save stack pointer. */ info_ptr -> tx_thread_secure_stack_ptr = (VOID *) sp; - + /* Set process stack pointer and stack limit to 0 to throw exception when a thread without a secure stack calls a secure function that tries to use secure stack. */ asm volatile("MSR PSPLIM, %0" :: "r" (0)); asm volatile("MSR PSP, %0" :: "r" (0)); - + return; } @@ -443,7 +528,7 @@ ULONG ipsr; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_restore Cortex-M23/GNU */ -/* 6.1.3 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -478,6 +563,9 @@ ULONG ipsr; /* 12-31-2020 Scott Larson Modified comment(s), and */ /* fixed M23 GCC build, */ /* resulting in version 6.1.3 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) @@ -485,6 +573,7 @@ void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG ipsr; +INT secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; /* This function should be called from scheduler only. */ asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ @@ -492,20 +581,26 @@ ULONG ipsr; { return; } - + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) + { + return; + } + /* Pickup the secure context pointer. */ - info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); - + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* Check that this secure context is for this thread. */ if (info_ptr -> tx_thread_ptr != thread_ptr) { return; } - + /* Set stack pointer and limit. */ asm volatile("MSR PSPLIM, %0" :: "r" ((ULONG)info_ptr -> tx_thread_secure_stack_limit)); asm volatile("MSR PSP, %0" :: "r" ((ULONG)info_ptr -> tx_thread_secure_stack_ptr)); - + return; } diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_notify.c b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_initialize.S similarity index 71% rename from ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_notify.c rename to ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_initialize.S index 75ad1f32c..7efcef408 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_notify.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_initialize.S @@ -20,77 +20,64 @@ /**************************************************************************/ /**************************************************************************/ -#define TX_SOURCE_CODE - - -/* Include necessary system files. */ - -#include "tx_api.h" -#include "tx_thread.h" -#include "tx_trace.h" - -extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_error_notify Cortex-M23 */ -/* 6.1 */ +/* _tx_thread_secure_stack_initialize Cortex-M23/GNU */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function registers an application stack error handler. If */ -/* ThreadX detects a stack error, this application handler is called. */ -/* */ +/* This function enters the SVC handler to initialize a secure stack. */ /* */ /* INPUT */ /* */ -/* stack_error_handler Pointer to stack error */ -/* handler, TX_NULL to disable */ +/* none */ /* */ /* OUTPUT */ /* */ -/* status Service return status */ +/* none */ /* */ /* CALLS */ /* */ -/* None */ +/* SVC 3 */ /* */ /* CALLED BY */ /* */ -/* Application Code */ +/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ /* RELEASE HISTORY */ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ -UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) -{ - -TX_INTERRUPT_SAVE_AREA - - /* Disable interrupts. */ - TX_DISABLE - - /* Make entry in event log. */ - TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS) - - /* Make entry in event log. */ - TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT - - /* Setup global thread stack error handler. */ - _tx_thread_application_stack_error_handler = stack_error_handler; - - /* Restore interrupts. */ - TX_RESTORE - - /* Return success to caller. */ - return(TX_SUCCESS); -} +// VOID _tx_thread_secure_stack_initialize(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_secure_stack_initialize + .thumb_func +.type _tx_thread_secure_stack_initialize, function +_tx_thread_secure_stack_initialize: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + CPSIE i // Enable interrupts for SVC call + SVC 3 + CPSID i // Disable interrupts +#else + MOV r0, #0xFF // Feature not enabled +#endif + BX lr + .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_handler.c b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_handler.c deleted file mode 100644 index 8e3cff23e..000000000 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_handler.c +++ /dev/null @@ -1,93 +0,0 @@ -/**************************************************************************/ -/* */ -/* Copyright (c) Microsoft Corporation. All rights reserved. */ -/* */ -/* This software is licensed under the Microsoft Software License */ -/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -/* and in the root directory of this software. */ -/* */ -/**************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Thread */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - -#define TX_SOURCE_CODE - - -/* Include necessary system files. */ - -#include "tx_api.h" -#include "tx_thread.h" - -/* Define the global function pointer for stack error handling. If a stack error is - detected and the application has registered a stack error handler, it will be - called via this function pointer. */ - -VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_stack_error_handler Cortex-M23 */ -/* 6.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function processes stack errors detected during run-time. */ -/* */ -/* */ -/* INPUT */ -/* */ -/* thread_ptr Thread control block pointer */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_terminate */ -/* _tx_thread_application_stack_error_handler */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX internal code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ -/**************************************************************************/ -VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) -{ - #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR - /* Is there a thread? */ - if (thread_ptr) - { - /* Terminate the current thread. */ - _tx_thread_terminate(_tx_thread_current_ptr); - } - #endif - - /* Determine if the application has registered an error handler. */ - if (_tx_thread_application_stack_error_handler != TX_NULL) - { - /* Yes, an error handler is present, simply call the application error handler. */ - (_tx_thread_application_stack_error_handler)(thread_ptr); - } -} diff --git a/ports_module/cortex_m23/iar/inc/tx_port.h b/ports_module/cortex_m23/iar/inc/tx_port.h index 418ffa05e..36016ea51 100644 --- a/ports_module/cortex_m23/iar/inc/tx_port.h +++ b/ports_module/cortex_m23/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M23/IAR */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -51,6 +51,10 @@ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -589,7 +593,7 @@ ULONG _tx_misra_ipsr_get(VOID); #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) /* Initialize secure stacks for threads calling secure functions. */ extern void _tx_thread_secure_stack_initialize(void); -#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to @@ -704,7 +708,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/IAR Version 6.1.11 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/IAR Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s index 9e6d58bb7..00f1189a4 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s @@ -42,7 +42,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M23/IAR */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -77,6 +77,9 @@ /* 04-02-2021 Scott Larson Initial Version 6.1.6 */ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -376,15 +379,6 @@ _skip_secure_restore: LDR r2, [r0, r2] // Pickup MPU data region address CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup - // Is the MPU already set up for this module? - MOVS r1, #2 // Select MPU region 2 - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 2 - LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 2 - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration - // Initialize loop to configure MPU registers MOVS r3, #0x64 // Index of MPU register settings in thread control block ADD r0, r0, r3 // Build address of MPU register start in thread control block diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c index 1bb31a36d..7cb0061ea 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c @@ -23,7 +23,7 @@ #include "tx_api.h" -/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, +/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, no secure stack functionality is needed. */ #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) @@ -45,8 +45,14 @@ #define TX_THREAD_STACK_SEAL_SIZE 8 #define TX_THREAD_STACK_SEAL_VALUE 0xFEF5EDA5 -/* Secure stack info struct to hold stack start, stack limit, - current stack pointer, and pointer to owning thread. +/* max number of Secure context */ +#ifndef TX_MAX_SECURE_CONTEXTS +#define TX_MAX_SECURE_CONTEXTS 32 +#endif +#define TX_INVALID_SECURE_CONTEXT_IDX (-1) + +/* Secure stack info struct to hold stack start, stack limit, + current stack pointer, and pointer to owning thread. This will be allocated for each thread with a secure stack. */ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT { @@ -54,8 +60,14 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */ VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */ TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */ + INT tx_next_free_index; /* Next free index of free secure context */ } TX_THREAD_SECURE_STACK_INFO; +/* Static secure contexts */ +static TX_THREAD_SECURE_STACK_INFO tx_thread_secure_context[TX_MAX_SECURE_CONTEXTS]; +/* Head of free secure context */ +static INT tx_head_free_index = 0U; + /**************************************************************************/ @@ -63,7 +75,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_initialize Cortex-M23/IAR */ -/* 6.1.8 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -98,16 +110,20 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ -/* 08-02-2021 Scott Larson Modified comment(s), changed */ +/* 06-02-2021 Scott Larson Modified comment(s), changed */ /* name, execute in handler */ /* mode, disable optimization, */ -/* resulting in version 6.1.8 */ +/* resulting in version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) { UINT status; +INT index; /* Make sure function is called from interrupt (threads should not call). */ if (__get_IPSR() == 0) @@ -118,12 +134,26 @@ UINT status; { /* Set secure mode to use PSP. */ __set_CONTROL(__get_CONTROL() | 2); - + /* Set process stack pointer and stack limit to 0 to throw exception when a thread without a secure stack calls a secure function that tries to use secure stack. */ __set_PSPLIM(0); __set_PSP(0); - + + for (index = 0; index < TX_MAX_SECURE_CONTEXTS; index++) + { + + /* Check last index and mark next free to invalid index */ + if(index == (TX_MAX_SECURE_CONTEXTS - 1)) + { + tx_thread_secure_context[index].tx_next_free_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + else + { + tx_thread_secure_context[index].tx_next_free_index = index + 1; + } + } + status = TX_SUCCESS; } return status; @@ -136,7 +166,7 @@ UINT status; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_allocate Cortex-M23/IAR */ -/* 6.1.1 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -160,9 +190,7 @@ UINT status; /* CALLS */ /* */ /* __get_IPSR Intrinsic to get IPSR */ -/* calloc Compiler's calloc function */ /* malloc Compiler's malloc function */ -/* free Compiler's free() function */ /* __set_PSPLIM Intrinsic to set PSP limit */ /* __set_PSP Intrinsic to set PSP */ /* __TZ_get_PSPLIM_NS Intrinsic to get NS PSP */ @@ -179,18 +207,24 @@ UINT status; /* 10-16-2020 Scott Larson Modified comment(s), */ /* added stack sealing, */ /* resulting in version 6.1.1 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* added */ +/* TX_INTERRUPT_SAVE_AREA, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; UCHAR *stack_mem; -ULONG sp; +INT secure_context_index; status = TX_SUCCESS; - + /* Make sure function is called from interrupt (threads should not call). */ if (__get_IPSR() == 0) { @@ -200,23 +234,38 @@ ULONG sp; { status = TX_SIZE_ERROR; } - + /* Check if thread already has secure stack allocated. */ else if (thread_ptr -> tx_thread_secure_stack_context != 0) { status = TX_THREAD_ERROR; } - + else { - /* Allocate space for secure stack info. */ - info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO)); - - if(info_ptr != TX_NULL) + TX_DISABLE + + /* Allocate free index for secure stack info. */ + if(tx_head_free_index != TX_INVALID_SECURE_CONTEXT_IDX) + { + secure_context_index = tx_head_free_index; + tx_head_free_index = tx_thread_secure_context[tx_head_free_index].tx_next_free_index; + tx_thread_secure_context[secure_context_index].tx_next_free_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + else + { + secure_context_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + + TX_RESTORE + + if(secure_context_index != TX_INVALID_SECURE_CONTEXT_IDX) { + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* If stack info allocated, allocate a stack & seal. */ stack_mem = malloc(stack_size + TX_THREAD_STACK_SEAL_SIZE); - + if(stack_mem != TX_NULL) { /* Secure stack has been allocated, save in the stack info struct. */ @@ -224,38 +273,41 @@ ULONG sp; info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size; info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start; info_ptr -> tx_thread_ptr = thread_ptr; - + /* Seal bottom of stack. */ *(ULONG*)info_ptr -> tx_thread_secure_stack_start = TX_THREAD_STACK_SEAL_VALUE; - - /* Save info pointer in thread. */ - thread_ptr -> tx_thread_secure_stack_context = info_ptr; - - /* Check if this thread is running by looking at PSP_NS and seeing if it is within - the stack_start and stack_end range. */ - sp = __TZ_get_PSP_NS(); - if(sp > ((ULONG) thread_ptr -> tx_thread_stack_start) && sp < ((ULONG) thread_ptr -> tx_thread_stack_end)) + + /* Save secure context id (i.e non-zero base index) in thread. */ + thread_ptr -> tx_thread_secure_stack_context = (VOID *)(secure_context_index + 1); + + /* Check if this thread is running by looking at its stack start and PSPLIM_NS */ + if(((ULONG) thread_ptr -> tx_thread_stack_start & 0xFFFFFFF8) == __TZ_get_PSPLIM_NS()) { /* If this thread is running, set Secure PSP and PSPLIM. */ __set_PSPLIM((ULONG)(info_ptr -> tx_thread_secure_stack_limit)); __set_PSP((ULONG)(info_ptr -> tx_thread_secure_stack_ptr)); } } - + else { + TX_DISABLE + /* Stack not allocated, free the info struct. */ - free(info_ptr); + tx_thread_secure_context[secure_context_index].tx_next_free_index = tx_head_free_index; + tx_head_free_index = secure_context_index; + TX_RESTORE + status = TX_NO_MEMORY; } } - + else { status = TX_NO_MEMORY; } } - + return(status); } @@ -266,7 +318,7 @@ ULONG sp; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_free Cortex-M23/IAR */ -/* 6.1.1 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -301,44 +353,67 @@ ULONG sp; /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* added */ +/* TX_INTERRUPT_SAVE_AREA, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; +INT secure_context_index; status = TX_SUCCESS; - - /* Pickup stack info from thread. */ - info_ptr = thread_ptr -> tx_thread_secure_stack_context; - + + /* Pickup stack info id from thread. */ + secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; + /* Make sure function is called from interrupt (threads should not call). */ if (__get_IPSR() == 0) { status = TX_CALLER_ERROR; } - - /* Check that this secure context is for this thread. */ - else if (info_ptr -> tx_thread_ptr != thread_ptr) + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) { status = TX_THREAD_ERROR; } - else { - - /* Free secure stack. */ - free(info_ptr -> tx_thread_secure_stack_limit); - - /* Free info struct. */ - free(info_ptr); - - /* Clear secure context from thread. */ - thread_ptr -> tx_thread_secure_stack_context = 0; + + /* Pickup stack info from static array of secure contexts. */ + info_ptr = &tx_thread_secure_context[secure_context_index]; + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Free secure stack. */ + free(info_ptr -> tx_thread_secure_stack_limit); + + TX_DISABLE + + /* Free info struct. */ + tx_thread_secure_context[secure_context_index].tx_next_free_index = tx_head_free_index; + tx_head_free_index = secure_context_index; + TX_RESTORE + + /* Clear secure context from thread. */ + thread_ptr -> tx_thread_secure_stack_context = 0; + } } - + return(status); } @@ -349,7 +424,7 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_save Cortex-M23/IAR */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -386,6 +461,9 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr; /* resulting in version 6.1.1 */ /* 06-02-2021 Scott Larson Fix stack pointer save, */ /* resulting in version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) @@ -393,38 +471,45 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; +INT secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { return; } - + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) + { + return; + } + /* Pickup the secure context pointer. */ - info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); - + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* Check that this secure context is for this thread. */ if (info_ptr -> tx_thread_ptr != thread_ptr) { return; } - + /* Check that stack pointer is in range */ sp = __get_PSP(); - if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || + if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start)) { return; } - + /* Save stack pointer. */ info_ptr -> tx_thread_secure_stack_ptr = (VOID *) sp; - + /* Set process stack pointer and stack limit to 0 to throw exception when a thread without a secure stack calls a secure function that tries to use secure stack. */ __set_PSPLIM(0); __set_PSP(0); - + return; } @@ -435,7 +520,7 @@ ULONG sp; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_restore Cortex-M23/IAR */ -/* 6.1.1 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -469,32 +554,42 @@ ULONG sp; /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 07-29-2022 Scott Larson Modified comments, updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; +INT secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { return; } - + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) + { + return; + } + /* Pickup the secure context pointer. */ - info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); - + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* Check that this secure context is for this thread. */ if (info_ptr -> tx_thread_ptr != thread_ptr) { return; } - + /* Set stack pointer and limit. */ __set_PSPLIM((ULONG)info_ptr -> tx_thread_secure_stack_limit); __set_PSP ((ULONG)info_ptr -> tx_thread_secure_stack_ptr); - + return; } diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_notify.c b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_initialize.s similarity index 71% rename from ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_notify.c rename to ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_initialize.s index 75ad1f32c..26ec4fb57 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_notify.c +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_initialize.s @@ -20,77 +20,59 @@ /**************************************************************************/ /**************************************************************************/ -#define TX_SOURCE_CODE - - -/* Include necessary system files. */ - -#include "tx_api.h" -#include "tx_thread.h" -#include "tx_trace.h" - -extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); - + SECTION `.text`:CODE:NOROOT(2) + THUMB /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_error_notify Cortex-M23 */ -/* 6.1 */ +/* _tx_thread_secure_stack_initialize Cortex-M23/IAR */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function registers an application stack error handler. If */ -/* ThreadX detects a stack error, this application handler is called. */ -/* */ +/* This function enters the SVC handler to initialize a secure stack. */ /* */ /* INPUT */ /* */ -/* stack_error_handler Pointer to stack error */ -/* handler, TX_NULL to disable */ +/* none */ /* */ /* OUTPUT */ /* */ -/* status Service return status */ +/* none */ /* */ /* CALLS */ /* */ -/* None */ +/* SVC 3 */ /* */ /* CALLED BY */ /* */ -/* Application Code */ +/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ /* RELEASE HISTORY */ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ -UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) -{ - -TX_INTERRUPT_SAVE_AREA - - /* Disable interrupts. */ - TX_DISABLE - - /* Make entry in event log. */ - TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS) - - /* Make entry in event log. */ - TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT - - /* Setup global thread stack error handler. */ - _tx_thread_application_stack_error_handler = stack_error_handler; - - /* Restore interrupts. */ - TX_RESTORE - - /* Return success to caller. */ - return(TX_SUCCESS); -} +// VOID _tx_thread_secure_stack_initialize(VOID) +// { + EXPORT _tx_thread_secure_stack_initialize +_tx_thread_secure_stack_initialize: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + CPSIE i // Enable interrupts for SVC call + SVC 3 + CPSID i // Disable interrupts +#else + MOV r0, #0xFF // Feature not enabled +#endif + BX lr + END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_handler.c b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_handler.c deleted file mode 100644 index 8e3cff23e..000000000 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_handler.c +++ /dev/null @@ -1,93 +0,0 @@ -/**************************************************************************/ -/* */ -/* Copyright (c) Microsoft Corporation. All rights reserved. */ -/* */ -/* This software is licensed under the Microsoft Software License */ -/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -/* and in the root directory of this software. */ -/* */ -/**************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Thread */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - -#define TX_SOURCE_CODE - - -/* Include necessary system files. */ - -#include "tx_api.h" -#include "tx_thread.h" - -/* Define the global function pointer for stack error handling. If a stack error is - detected and the application has registered a stack error handler, it will be - called via this function pointer. */ - -VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_stack_error_handler Cortex-M23 */ -/* 6.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function processes stack errors detected during run-time. */ -/* */ -/* */ -/* INPUT */ -/* */ -/* thread_ptr Thread control block pointer */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_terminate */ -/* _tx_thread_application_stack_error_handler */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX internal code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ -/**************************************************************************/ -VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) -{ - #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR - /* Is there a thread? */ - if (thread_ptr) - { - /* Terminate the current thread. */ - _tx_thread_terminate(_tx_thread_current_ptr); - } - #endif - - /* Determine if the application has registered an error handler. */ - if (_tx_thread_application_stack_error_handler != TX_NULL) - { - /* Yes, an error handler is present, simply call the application error handler. */ - (_tx_thread_application_stack_error_handler)(thread_ptr); - } -} diff --git a/ports_module/cortex_m3/ac5/inc/txm_module_port.h b/ports_module/cortex_m3/ac5/inc/txm_module_port.h index d3bcdee89..523c787ab 100644 --- a/ports_module/cortex_m3/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_m3/ac5/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M3/AC5 */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,6 +41,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enabled user-defined and */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -111,6 +114,60 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 #endif +/* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) + are not used by ThreadX. These may be defined by the user. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 + + +/* Users can define these default MPU configuration values. + + If TXM_MODULE_MPU_DEFAULT is *not* defined, the MPU is disabled + when a thread that is not owned by a module is running + and the defines below are not used. + + If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the + below values when a thread that is not owned by a module is running. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_15 0 + + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.s index 6f0f91df7..118384707 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.s @@ -40,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M3/AC5 */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,6 +76,10 @@ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, optional */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -385,26 +389,33 @@ __tx_ts_restore LDR r0, =0xE000ED94 // Build MPU control reg address MOV r3, #0 // Build disable value + CPSID i // Disable interrupts STR r3, [r0] // Disable MPU LDR r0, [r1, #0x90] // Pickup the module instance pointer +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r0, default_mpu // Is this thread owned by a module? No, default MPU setup +#else CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup - +#endif + LDR r2, [r0, #0x8C] // Pickup MPU region 5 address +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r2, default_mpu // Is protection required for this module? No, default MPU setup +#else CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup - - // Is the MPU already set up for this module? - MOV r1, #5 // Select region 5 from MPU - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 5 +#endif LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 5 - BIC r2, r2, #0x10 // Clear VALID bit - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block +#ifdef TXM_MODULE_MPU_DEFAULT + B config_mpu // configure MPU for module +default_mpu: + LDR r0, =txm_module_default_mpu_registers // default MPU configuration +#endif + +config_mpu: LDM r0!,{r2-r9} // Load MPU regions 0-3 STM r1,{r2-r9} // Store MPU regions 0-3 LDM r0!,{r2-r9} // Load MPU regions 4-7 @@ -412,6 +423,7 @@ __tx_ts_restore #ifdef TXM_MODULE_MANAGER_16_MPU LDM r0!,{r2-r9} // Load MPU regions 8-11 STM r1,{r2-r9} // Store MPU regions 8-11 + // Regions 12-15 are reserved for the user to define. LDM r0,{r2-r9} // Load MPU regions 12-15 STM r1,{r2-r9} // Store MPU regions 12-15 #endif @@ -420,6 +432,7 @@ _tx_enable_mpu MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU skip_mpu_setup + CPSIE i // Enable interrupts LDMIA r12!, {LR} // Pickup LR #ifdef __TARGET_FPU_VFP TST LR, #0x10 // Determine if the VFP extended frame is present @@ -573,14 +586,14 @@ _tx_no_lazy_clear: #endif /* Copy kernel hardware stack to module thread stack. */ - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} + LDM r3!, {r1-r2} // Get r0, r1 from kernel stack + STM r0!, {r1-r2} // Insert r0, r1 into thread stack + LDM r3!, {r1-r2} // Get r2, r3 from kernel stack + STM r0!, {r1-r2} // Insert r2, r3 into thread stack + LDM r3!, {r1-r2} // Get r12, lr from kernel stack + STM r0!, {r1-r2} // Insert r12, lr into thread stack + LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack + STM r0!, {r1-r2} // Insert pc, xpsr into thread stack SUB r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index 48a14571b..4a00404f0 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -25,6 +25,43 @@ #include "tx_api.h" #include "txm_module.h" +#ifdef TXM_MODULE_MPU_DEFAULT +const ULONG txm_module_default_mpu_registers[32] = + { + TXM_MODULE_MPU_DEFAULT_RBAR_0, + TXM_MODULE_MPU_DEFAULT_RASR_0, + TXM_MODULE_MPU_DEFAULT_RBAR_1, + TXM_MODULE_MPU_DEFAULT_RASR_1, + TXM_MODULE_MPU_DEFAULT_RBAR_2, + TXM_MODULE_MPU_DEFAULT_RASR_2, + TXM_MODULE_MPU_DEFAULT_RBAR_3, + TXM_MODULE_MPU_DEFAULT_RASR_3, + TXM_MODULE_MPU_DEFAULT_RBAR_4, + TXM_MODULE_MPU_DEFAULT_RASR_4, + TXM_MODULE_MPU_DEFAULT_RBAR_5, + TXM_MODULE_MPU_DEFAULT_RASR_5, + TXM_MODULE_MPU_DEFAULT_RBAR_6, + TXM_MODULE_MPU_DEFAULT_RASR_6, + TXM_MODULE_MPU_DEFAULT_RBAR_7, + TXM_MODULE_MPU_DEFAULT_RASR_7, + TXM_MODULE_MPU_DEFAULT_RBAR_8, + TXM_MODULE_MPU_DEFAULT_RASR_8, + TXM_MODULE_MPU_DEFAULT_RBAR_9, + TXM_MODULE_MPU_DEFAULT_RASR_9, + TXM_MODULE_MPU_DEFAULT_RBAR_10, + TXM_MODULE_MPU_DEFAULT_RASR_10, + TXM_MODULE_MPU_DEFAULT_RBAR_11, + TXM_MODULE_MPU_DEFAULT_RASR_11, + TXM_MODULE_MPU_DEFAULT_RBAR_12, + TXM_MODULE_MPU_DEFAULT_RASR_12, + TXM_MODULE_MPU_DEFAULT_RBAR_13, + TXM_MODULE_MPU_DEFAULT_RASR_13, + TXM_MODULE_MPU_DEFAULT_RBAR_14, + TXM_MODULE_MPU_DEFAULT_RASR_14, + TXM_MODULE_MPU_DEFAULT_RBAR_15, + TXM_MODULE_MPU_DEFAULT_RASR_15 + }; +#endif /**************************************************************************/ /* */ @@ -231,7 +268,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M3 */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -267,10 +304,10 @@ UINT srd_bit_index; /* 9 Module shared memory region */ /* 10 Module shared memory region */ /* 11 Module shared memory region */ -/* 12 Unused region */ -/* 13 Unused region */ -/* 14 Unused region */ -/* 15 Unused region */ +/* 12 User-defined region */ +/* 13 User-defined region */ +/* 14 User-defined region */ +/* 15 User-defined region */ /* */ /* */ /* INPUT */ @@ -294,6 +331,8 @@ UINT srd_bit_index; /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enable user defined regions, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -456,18 +495,18 @@ UINT i; /* Increment MPU table index. */ mpu_table_index++; } - - /* Setup MPU for the remaining regions. */ - while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) - { - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - - /* Increment MPU table index. */ - mpu_table_index++; - } -#else + /* Setup user-defined regions (12-15). */ + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_12; + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_12; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_13; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_13; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_14; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_14; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_15; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_15; + +#else /* TXM_MODULE_MANAGER_16_MPU is not defined, only 8 MPU regions. */ ULONG code_address; ULONG code_size; diff --git a/ports_module/cortex_m3/ac6/inc/txm_module_port.h b/ports_module/cortex_m3/ac6/inc/txm_module_port.h index 756217573..235aca2c1 100644 --- a/ports_module/cortex_m3/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m3/ac6/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M3/AC6 */ -/* 6.1.10 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -44,6 +44,9 @@ /* 01-31-2022 Scott Larson Modified comments and made */ /* heap user-configurable, */ /* resulting in version 6.1.10 */ +/* 07-29-2022 Scott Larson Enabled user-defined and */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -119,6 +122,60 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 #endif +/* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) + are not used by ThreadX. These may be defined by the user. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 + + +/* Users can define these default MPU configuration values. + + If TXM_MODULE_MPU_DEFAULT is *not* defined, the MPU is disabled + when a thread that is not owned by a module is running + and the defines below are not used. + + If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the + below values when a thread that is not owned by a module is running. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_15 0 + + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -384,6 +441,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/AC6 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/AC6 Version 6.1.12 *"; #endif diff --git a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c index efe4d9b05..750afe31b 100644 --- a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -57,7 +57,7 @@ extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top); /* FUNCTION RELEASE */ /* */ /* _txm_module_thread_shell_entry Cortex-M3/AC6 */ -/* 6.1.10 */ +/* 6.1.10 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S index 4cf1df38a..00ab90534 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S @@ -42,7 +42,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M3/AC6 */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -78,6 +78,10 @@ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, optional */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -398,26 +402,33 @@ __tx_ts_restore: LDR r0, =0xE000ED94 // Build MPU control reg address MOV r3, #0 // Build disable value + CPSID i // Disable interrupts STR r3, [r0] // Disable MPU LDR r0, [r1, #0x90] // Pickup the module instance pointer +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r0, default_mpu // Is this thread owned by a module? No, default MPU setup +#else CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup - +#endif + LDR r2, [r0, #0x8C] // Pickup MPU region 5 address +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r2, default_mpu // Is protection required for this module? No, default MPU setup +#else CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup - - // Is the MPU already set up for this module? - MOV r1, #5 // Select region 5 from MPU - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 5 +#endif LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 5 - BIC r2, r2, #0x10 // Clear VALID bit - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block +#ifdef TXM_MODULE_MPU_DEFAULT + B config_mpu // configure MPU for module +default_mpu: + LDR r0, =txm_module_default_mpu_registers // default MPU configuration +#endif + +config_mpu: LDM r0!,{r2-r9} // Load MPU regions 0-3 STM r1,{r2-r9} // Store MPU regions 0-3 LDM r0!,{r2-r9} // Load MPU regions 4-7 @@ -425,14 +436,17 @@ __tx_ts_restore: #ifdef TXM_MODULE_MANAGER_16_MPU LDM r0!,{r2-r9} // Load MPU regions 8-11 STM r1,{r2-r9} // Store MPU regions 8-11 + // Regions 12-15 are reserved for the user to define. LDM r0,{r2-r9} // Load MPU regions 12-15 STM r1,{r2-r9} // Store MPU regions 12-15 #endif + _tx_enable_mpu: LDR r0, =0xE000ED94 // Build MPU control reg address MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU skip_mpu_setup: + CPSIE i // Enable interrupts LDMIA r12!, {LR} // Pickup LR #ifdef __ARM_FP TST LR, #0x10 // Determine if the VFP extended frame is present diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 48a14571b..4a00404f0 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -25,6 +25,43 @@ #include "tx_api.h" #include "txm_module.h" +#ifdef TXM_MODULE_MPU_DEFAULT +const ULONG txm_module_default_mpu_registers[32] = + { + TXM_MODULE_MPU_DEFAULT_RBAR_0, + TXM_MODULE_MPU_DEFAULT_RASR_0, + TXM_MODULE_MPU_DEFAULT_RBAR_1, + TXM_MODULE_MPU_DEFAULT_RASR_1, + TXM_MODULE_MPU_DEFAULT_RBAR_2, + TXM_MODULE_MPU_DEFAULT_RASR_2, + TXM_MODULE_MPU_DEFAULT_RBAR_3, + TXM_MODULE_MPU_DEFAULT_RASR_3, + TXM_MODULE_MPU_DEFAULT_RBAR_4, + TXM_MODULE_MPU_DEFAULT_RASR_4, + TXM_MODULE_MPU_DEFAULT_RBAR_5, + TXM_MODULE_MPU_DEFAULT_RASR_5, + TXM_MODULE_MPU_DEFAULT_RBAR_6, + TXM_MODULE_MPU_DEFAULT_RASR_6, + TXM_MODULE_MPU_DEFAULT_RBAR_7, + TXM_MODULE_MPU_DEFAULT_RASR_7, + TXM_MODULE_MPU_DEFAULT_RBAR_8, + TXM_MODULE_MPU_DEFAULT_RASR_8, + TXM_MODULE_MPU_DEFAULT_RBAR_9, + TXM_MODULE_MPU_DEFAULT_RASR_9, + TXM_MODULE_MPU_DEFAULT_RBAR_10, + TXM_MODULE_MPU_DEFAULT_RASR_10, + TXM_MODULE_MPU_DEFAULT_RBAR_11, + TXM_MODULE_MPU_DEFAULT_RASR_11, + TXM_MODULE_MPU_DEFAULT_RBAR_12, + TXM_MODULE_MPU_DEFAULT_RASR_12, + TXM_MODULE_MPU_DEFAULT_RBAR_13, + TXM_MODULE_MPU_DEFAULT_RASR_13, + TXM_MODULE_MPU_DEFAULT_RBAR_14, + TXM_MODULE_MPU_DEFAULT_RASR_14, + TXM_MODULE_MPU_DEFAULT_RBAR_15, + TXM_MODULE_MPU_DEFAULT_RASR_15 + }; +#endif /**************************************************************************/ /* */ @@ -231,7 +268,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M3 */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -267,10 +304,10 @@ UINT srd_bit_index; /* 9 Module shared memory region */ /* 10 Module shared memory region */ /* 11 Module shared memory region */ -/* 12 Unused region */ -/* 13 Unused region */ -/* 14 Unused region */ -/* 15 Unused region */ +/* 12 User-defined region */ +/* 13 User-defined region */ +/* 14 User-defined region */ +/* 15 User-defined region */ /* */ /* */ /* INPUT */ @@ -294,6 +331,8 @@ UINT srd_bit_index; /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enable user defined regions, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -456,18 +495,18 @@ UINT i; /* Increment MPU table index. */ mpu_table_index++; } - - /* Setup MPU for the remaining regions. */ - while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) - { - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - - /* Increment MPU table index. */ - mpu_table_index++; - } -#else + /* Setup user-defined regions (12-15). */ + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_12; + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_12; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_13; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_13; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_14; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_14; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_15; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_15; + +#else /* TXM_MODULE_MANAGER_16_MPU is not defined, only 8 MPU regions. */ ULONG code_address; ULONG code_size; diff --git a/ports_module/cortex_m3/gnu/example_build/build_threadx_sample.bat b/ports_module/cortex_m3/gnu/example_build/build_threadx_sample.bat new file mode 100644 index 000000000..af3156de6 --- /dev/null +++ b/ports_module/cortex_m3/gnu/example_build/build_threadx_sample.bat @@ -0,0 +1,4 @@ +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc sample_threadx.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb tx_simulator_startup.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb cortexm_crt0.S +arm-none-eabi-ld -A cortex-m3 -ereset_handler -T sample_threadx.ld tx_simulator_startup.o cortexm_crt0.o sample_threadx.o tx.a libc.a -o sample_threadx.axf -M > sample_threadx.map diff --git a/ports_module/cortex_m3/gnu/inc/txm_module_port.h b/ports_module/cortex_m3/gnu/inc/txm_module_port.h index 58ed96144..c77eb2f0d 100644 --- a/ports_module/cortex_m3/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m3/gnu/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M3/GNU */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,6 +41,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enabled user-defined and */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -111,6 +114,60 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 #endif +/* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) + are not used by ThreadX. These may be defined by the user. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 + + +/* Users can define these default MPU configuration values. + + If TXM_MODULE_MPU_DEFAULT is *not* defined, the MPU is disabled + when a thread that is not owned by a module is running + and the defines below are not used. + + If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the + below values when a thread that is not owned by a module is running. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_15 0 + + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -376,6 +433,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/GNU Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/GNU Version 6.1.12 *"; #endif diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S index e5d101b53..a8b3894fa 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S @@ -40,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M3/GNU */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -78,6 +78,10 @@ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, optional */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -398,26 +402,33 @@ __tx_ts_restore: LDR r0, =0xE000ED94 // Build MPU control reg address MOV r3, #0 // Build disable value + CPSID i // Disable interrupts STR r3, [r0] // Disable MPU LDR r0, [r1, #0x90] // Pickup the module instance pointer +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r0, default_mpu // Is this thread owned by a module? No, default MPU setup +#else CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup - +#endif + LDR r2, [r0, #0x8C] // Pickup MPU region 5 address +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r2, default_mpu // Is protection required for this module? No, default MPU setup +#else CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup - - // Is the MPU already set up for this module? - MOV r1, #5 // Select region 5 from MPU - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 5 +#endif LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 5 - BIC r2, r2, #0x10 // Clear VALID bit - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block +#ifdef TXM_MODULE_MPU_DEFAULT + B config_mpu // configure MPU for module +default_mpu: + LDR r0, =txm_module_default_mpu_registers // default MPU configuration +#endif + +config_mpu: LDM r0!,{r2-r9} // Load MPU regions 0-3 STM r1,{r2-r9} // Store MPU regions 0-3 LDM r0!,{r2-r9} // Load MPU regions 4-7 @@ -425,14 +436,17 @@ __tx_ts_restore: #ifdef TXM_MODULE_MANAGER_16_MPU LDM r0!,{r2-r9} // Load MPU regions 8-11 STM r1,{r2-r9} // Store MPU regions 8-11 + // Regions 12-15 are reserved for the user to define. LDM r0,{r2-r9} // Load MPU regions 12-15 STM r1,{r2-r9} // Store MPU regions 12-15 #endif + _tx_enable_mpu: LDR r0, =0xE000ED94 // Build MPU control reg address MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU skip_mpu_setup: + CPSIE i // Enable interrupts LDMIA r12!, {LR} // Pickup LR #ifdef __ARM_FP TST LR, #0x10 // Determine if the VFP extended frame is present @@ -588,14 +602,14 @@ _tx_no_lazy_clear: #endif /* Copy kernel hardware stack to module thread stack. */ - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} + LDM r3!, {r1-r2} // Get r0, r1 from kernel stack + STM r0!, {r1-r2} // Insert r0, r1 into thread stack + LDM r3!, {r1-r2} // Get r2, r3 from kernel stack + STM r0!, {r1-r2} // Insert r2, r3 into thread stack + LDM r3!, {r1-r2} // Get r12, lr from kernel stack + STM r0!, {r1-r2} // Insert r12, lr into thread stack + LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack + STM r0!, {r1-r2} // Insert pc, xpsr into thread stack SUB r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index 48a14571b..4a00404f0 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -25,6 +25,43 @@ #include "tx_api.h" #include "txm_module.h" +#ifdef TXM_MODULE_MPU_DEFAULT +const ULONG txm_module_default_mpu_registers[32] = + { + TXM_MODULE_MPU_DEFAULT_RBAR_0, + TXM_MODULE_MPU_DEFAULT_RASR_0, + TXM_MODULE_MPU_DEFAULT_RBAR_1, + TXM_MODULE_MPU_DEFAULT_RASR_1, + TXM_MODULE_MPU_DEFAULT_RBAR_2, + TXM_MODULE_MPU_DEFAULT_RASR_2, + TXM_MODULE_MPU_DEFAULT_RBAR_3, + TXM_MODULE_MPU_DEFAULT_RASR_3, + TXM_MODULE_MPU_DEFAULT_RBAR_4, + TXM_MODULE_MPU_DEFAULT_RASR_4, + TXM_MODULE_MPU_DEFAULT_RBAR_5, + TXM_MODULE_MPU_DEFAULT_RASR_5, + TXM_MODULE_MPU_DEFAULT_RBAR_6, + TXM_MODULE_MPU_DEFAULT_RASR_6, + TXM_MODULE_MPU_DEFAULT_RBAR_7, + TXM_MODULE_MPU_DEFAULT_RASR_7, + TXM_MODULE_MPU_DEFAULT_RBAR_8, + TXM_MODULE_MPU_DEFAULT_RASR_8, + TXM_MODULE_MPU_DEFAULT_RBAR_9, + TXM_MODULE_MPU_DEFAULT_RASR_9, + TXM_MODULE_MPU_DEFAULT_RBAR_10, + TXM_MODULE_MPU_DEFAULT_RASR_10, + TXM_MODULE_MPU_DEFAULT_RBAR_11, + TXM_MODULE_MPU_DEFAULT_RASR_11, + TXM_MODULE_MPU_DEFAULT_RBAR_12, + TXM_MODULE_MPU_DEFAULT_RASR_12, + TXM_MODULE_MPU_DEFAULT_RBAR_13, + TXM_MODULE_MPU_DEFAULT_RASR_13, + TXM_MODULE_MPU_DEFAULT_RBAR_14, + TXM_MODULE_MPU_DEFAULT_RASR_14, + TXM_MODULE_MPU_DEFAULT_RBAR_15, + TXM_MODULE_MPU_DEFAULT_RASR_15 + }; +#endif /**************************************************************************/ /* */ @@ -231,7 +268,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M3 */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -267,10 +304,10 @@ UINT srd_bit_index; /* 9 Module shared memory region */ /* 10 Module shared memory region */ /* 11 Module shared memory region */ -/* 12 Unused region */ -/* 13 Unused region */ -/* 14 Unused region */ -/* 15 Unused region */ +/* 12 User-defined region */ +/* 13 User-defined region */ +/* 14 User-defined region */ +/* 15 User-defined region */ /* */ /* */ /* INPUT */ @@ -294,6 +331,8 @@ UINT srd_bit_index; /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enable user defined regions, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -456,18 +495,18 @@ UINT i; /* Increment MPU table index. */ mpu_table_index++; } - - /* Setup MPU for the remaining regions. */ - while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) - { - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - - /* Increment MPU table index. */ - mpu_table_index++; - } -#else + /* Setup user-defined regions (12-15). */ + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_12; + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_12; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_13; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_13; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_14; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_14; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_15; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_15; + +#else /* TXM_MODULE_MANAGER_16_MPU is not defined, only 8 MPU regions. */ ULONG code_address; ULONG code_size; diff --git a/ports_module/cortex_m3/iar/inc/txm_module_port.h b/ports_module/cortex_m3/iar/inc/txm_module_port.h index d3f38fec5..5c8aa17e0 100644 --- a/ports_module/cortex_m3/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m3/iar/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M3/IAR */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,6 +41,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enabled user-defined and */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -112,6 +115,60 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 #endif +/* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) + are not used by ThreadX. These may be defined by the user. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 + + +/* Users can define these default MPU configuration values. + + If TXM_MODULE_MPU_DEFAULT is *not* defined, the MPU is disabled + when a thread that is not owned by a module is running + and the defines below are not used. + + If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the + below values when a thread that is not owned by a module is running. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_15 0 + + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -377,6 +434,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/IAR Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/IAR Version 6.1.12 *"; #endif diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s index 6326b8007..b83ec5278 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s @@ -28,6 +28,7 @@ EXTERN _tx_thread_preempt_disable EXTERN _txm_module_manager_memory_fault_handler EXTERN _txm_module_manager_memory_fault_info + EXTERN txm_module_default_mpu_registers SECTION `.text`:CODE:NOROOT(2) THUMB @@ -36,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M3/IAR */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -72,6 +73,10 @@ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, optional */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -385,26 +390,33 @@ __tx_ts_restore: LDR r0, =0xE000ED94 // Build MPU control reg address MOV r3, #0 // Build disable value + CPSID i // Disable interrupts STR r3, [r0] // Disable MPU LDR r0, [r1, #0x90] // Pickup the module instance pointer +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r0, default_mpu // Is this thread owned by a module? No, default MPU setup +#else CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup - +#endif + LDR r2, [r0, #0x8C] // Pickup MPU region 5 address +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r2, default_mpu // Is protection required for this module? No, default MPU setup +#else CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup - - // Is the MPU already set up for this module? - MOV r1, #5 // Select region 5 from MPU - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 5 +#endif LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 5 - BIC r2, r2, #0x10 // Clear VALID bit - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block +#ifdef TXM_MODULE_MPU_DEFAULT + B config_mpu // configure MPU for module +default_mpu: + LDR r0, =txm_module_default_mpu_registers // default MPU configuration +#endif + +config_mpu: LDM r0!,{r2-r9} // Load MPU regions 0-3 STM r1,{r2-r9} // Store MPU regions 0-3 LDM r0!,{r2-r9} // Load MPU regions 4-7 @@ -412,14 +424,17 @@ __tx_ts_restore: #ifdef TXM_MODULE_MANAGER_16_MPU LDM r0!,{r2-r9} // Load MPU regions 8-11 STM r1,{r2-r9} // Store MPU regions 8-11 + // Regions 12-15 are reserved for the user to define. LDM r0,{r2-r9} // Load MPU regions 12-15 STM r1,{r2-r9} // Store MPU regions 12-15 #endif + _tx_enable_mpu: LDR r0, =0xE000ED94 // Build MPU control reg address MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU skip_mpu_setup: + CPSIE i // Enable interrupts LDMIA r12!, {LR} // Pickup LR #ifdef __ARMVFP__ TST LR, #0x10 // Determine if the VFP extended frame is present @@ -574,14 +589,14 @@ _tx_no_lazy_clear: #endif /* Copy kernel hardware stack to module thread stack. */ - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} + LDM r3!, {r1-r2} // Get r0, r1 from kernel stack + STM r0!, {r1-r2} // Insert r0, r1 into thread stack + LDM r3!, {r1-r2} // Get r2, r3 from kernel stack + STM r0!, {r1-r2} // Insert r2, r3 into thread stack + LDM r3!, {r1-r2} // Get r12, lr from kernel stack + STM r0!, {r1-r2} // Insert r12, lr into thread stack + LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack + STM r0!, {r1-r2} // Insert pc, xpsr into thread stack SUB r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 48a14571b..4a00404f0 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -25,6 +25,43 @@ #include "tx_api.h" #include "txm_module.h" +#ifdef TXM_MODULE_MPU_DEFAULT +const ULONG txm_module_default_mpu_registers[32] = + { + TXM_MODULE_MPU_DEFAULT_RBAR_0, + TXM_MODULE_MPU_DEFAULT_RASR_0, + TXM_MODULE_MPU_DEFAULT_RBAR_1, + TXM_MODULE_MPU_DEFAULT_RASR_1, + TXM_MODULE_MPU_DEFAULT_RBAR_2, + TXM_MODULE_MPU_DEFAULT_RASR_2, + TXM_MODULE_MPU_DEFAULT_RBAR_3, + TXM_MODULE_MPU_DEFAULT_RASR_3, + TXM_MODULE_MPU_DEFAULT_RBAR_4, + TXM_MODULE_MPU_DEFAULT_RASR_4, + TXM_MODULE_MPU_DEFAULT_RBAR_5, + TXM_MODULE_MPU_DEFAULT_RASR_5, + TXM_MODULE_MPU_DEFAULT_RBAR_6, + TXM_MODULE_MPU_DEFAULT_RASR_6, + TXM_MODULE_MPU_DEFAULT_RBAR_7, + TXM_MODULE_MPU_DEFAULT_RASR_7, + TXM_MODULE_MPU_DEFAULT_RBAR_8, + TXM_MODULE_MPU_DEFAULT_RASR_8, + TXM_MODULE_MPU_DEFAULT_RBAR_9, + TXM_MODULE_MPU_DEFAULT_RASR_9, + TXM_MODULE_MPU_DEFAULT_RBAR_10, + TXM_MODULE_MPU_DEFAULT_RASR_10, + TXM_MODULE_MPU_DEFAULT_RBAR_11, + TXM_MODULE_MPU_DEFAULT_RASR_11, + TXM_MODULE_MPU_DEFAULT_RBAR_12, + TXM_MODULE_MPU_DEFAULT_RASR_12, + TXM_MODULE_MPU_DEFAULT_RBAR_13, + TXM_MODULE_MPU_DEFAULT_RASR_13, + TXM_MODULE_MPU_DEFAULT_RBAR_14, + TXM_MODULE_MPU_DEFAULT_RASR_14, + TXM_MODULE_MPU_DEFAULT_RBAR_15, + TXM_MODULE_MPU_DEFAULT_RASR_15 + }; +#endif /**************************************************************************/ /* */ @@ -231,7 +268,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M3 */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -267,10 +304,10 @@ UINT srd_bit_index; /* 9 Module shared memory region */ /* 10 Module shared memory region */ /* 11 Module shared memory region */ -/* 12 Unused region */ -/* 13 Unused region */ -/* 14 Unused region */ -/* 15 Unused region */ +/* 12 User-defined region */ +/* 13 User-defined region */ +/* 14 User-defined region */ +/* 15 User-defined region */ /* */ /* */ /* INPUT */ @@ -294,6 +331,8 @@ UINT srd_bit_index; /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enable user defined regions, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -456,18 +495,18 @@ UINT i; /* Increment MPU table index. */ mpu_table_index++; } - - /* Setup MPU for the remaining regions. */ - while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) - { - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - - /* Increment MPU table index. */ - mpu_table_index++; - } -#else + /* Setup user-defined regions (12-15). */ + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_12; + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_12; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_13; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_13; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_14; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_14; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_15; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_15; + +#else /* TXM_MODULE_MANAGER_16_MPU is not defined, only 8 MPU regions. */ ULONG code_address; ULONG code_size; diff --git a/ports_module/cortex_m33/ac6/inc/tx_port.h b/ports_module/cortex_m33/ac6/inc/tx_port.h index e35476022..0b44956c9 100644 --- a/ports_module/cortex_m33/ac6/inc/tx_port.h +++ b/ports_module/cortex_m33/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M33 */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -64,13 +64,18 @@ /* 10-15-2021 Scott Larson Modified comment(s), improved */ /* stack check error handling, */ /* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ +/* 01-31-2022 Scott Larson Modified comment(s), unified */ /* this file across compilers, */ /* fixed predefined macro, */ /* resulting in version 6.1.10 */ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -188,6 +193,12 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -582,7 +593,7 @@ ULONG _tx_misra_ipsr_get(VOID); #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) /* Initialize secure stacks for threads calling secure functions. */ extern void _tx_thread_secure_stack_initialize(void); -#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to @@ -695,7 +706,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33 Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33 Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m33/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m33/ac6/module_lib/src/txm_module_thread_shell_entry.c index ad2c62051..da78d6ae8 100644 --- a/ports_module/cortex_m33/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m33/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -58,7 +58,7 @@ extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top); /* FUNCTION RELEASE */ /* */ /* _txm_module_thread_shell_entry Cortex-M33/AC6 */ -/* 6.1.10 */ +/* 6.1.10 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S index c196f75a5..417d14046 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M33/AC6 */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -72,6 +72,9 @@ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -424,14 +427,7 @@ _skip_secure_restore: LDR r2, [r0, #0x74] // Pickup MPU address of data region CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup - // Is the MPU already set up for this module? - MOV r1, #2 // Select MPU region 2 - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 2 LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 2 - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration // Use alias registers to quickly load MPU LDR r2, =0xE000ED98 // Get region register diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack.c index 5089f39bb..099ae737e 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack.c @@ -23,7 +23,7 @@ #include "tx_api.h" -/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, +/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, no secure stack functionality is needed. */ #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) @@ -45,8 +45,14 @@ #define TX_THREAD_STACK_SEAL_SIZE 8 #define TX_THREAD_STACK_SEAL_VALUE 0xFEF5EDA5 -/* Secure stack info struct to hold stack start, stack limit, - current stack pointer, and pointer to owning thread. +/* max number of Secure context */ +#ifndef TX_MAX_SECURE_CONTEXTS +#define TX_MAX_SECURE_CONTEXTS 32 +#endif +#define TX_INVALID_SECURE_CONTEXT_IDX (-1) + +/* Secure stack info struct to hold stack start, stack limit, + current stack pointer, and pointer to owning thread. This will be allocated for each thread with a secure stack. */ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT { @@ -54,8 +60,14 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */ VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */ TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */ + INT tx_next_free_index; /* Next free index of free secure context */ } TX_THREAD_SECURE_STACK_INFO; +/* Static secure contexts */ +static TX_THREAD_SECURE_STACK_INFO tx_thread_secure_context[TX_MAX_SECURE_CONTEXTS]; +/* Head of free secure context */ +static INT tx_head_free_index = 0U; + /**************************************************************************/ @@ -63,7 +75,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_initialize Cortex-M33/AC6 */ -/* 6.1.8 */ +/* 6.1.10 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -98,16 +110,20 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ -/* 08-02-2021 Scott Larson Modified comment(s), and */ +/* 06-02-2021 Scott Larson Modified comment(s), and */ /* changed name, execute in */ /* handler mode, */ -/* resulting in version 6.1.8 */ +/* resulting in version 6.1.7 */ +/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.10 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) { UINT status; +INT index; /* Make sure function is called from interrupt (threads should not call). */ if (__get_IPSR() == 0) @@ -118,12 +134,26 @@ UINT status; { /* Set secure mode to use PSP. */ __set_CONTROL(__get_CONTROL() | 2); - + /* Set process stack pointer and stack limit to 0 to throw exception when a thread without a secure stack calls a secure function that tries to use secure stack. */ __set_PSPLIM(0); __set_PSP(0); - + + for (index = 0; index < TX_MAX_SECURE_CONTEXTS; index++) + { + + /* Check last index and mark next free to invalid index */ + if(index == (TX_MAX_SECURE_CONTEXTS - 1)) + { + tx_thread_secure_context[index].tx_next_free_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + else + { + tx_thread_secure_context[index].tx_next_free_index = index + 1; + } + } + status = TX_SUCCESS; } return status; @@ -136,7 +166,7 @@ UINT status; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_allocate Cortex-M33/AC6 */ -/* 6.1.1 */ +/* 6.1.10 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -160,9 +190,7 @@ UINT status; /* CALLS */ /* */ /* __get_IPSR Intrinsic to get IPSR */ -/* calloc Compiler's calloc function */ /* malloc Compiler's malloc function */ -/* free Compiler's free() function */ /* __set_PSPLIM Intrinsic to set PSP limit */ /* __set_PSP Intrinsic to set PSP */ /* __TZ_get_PSPLIM_NS Intrinsic to get NS PSP */ @@ -179,17 +207,22 @@ UINT status; /* 10-16-2020 Scott Larson Modified comment(s), */ /* added stack sealing, */ /* resulting in version 6.1.1 */ +/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.10 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; UCHAR *stack_mem; +INT secure_context_index; status = TX_SUCCESS; - + /* Make sure function is called from interrupt (threads should not call). */ if (__get_IPSR() == 0) { @@ -199,23 +232,38 @@ UCHAR *stack_mem; { status = TX_SIZE_ERROR; } - + /* Check if thread already has secure stack allocated. */ else if (thread_ptr -> tx_thread_secure_stack_context != 0) { status = TX_THREAD_ERROR; } - + else { - /* Allocate space for secure stack info. */ - info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO)); - - if(info_ptr != TX_NULL) + TX_DISABLE + + /* Allocate free index for secure stack info. */ + if(tx_head_free_index != TX_INVALID_SECURE_CONTEXT_IDX) + { + secure_context_index = tx_head_free_index; + tx_head_free_index = tx_thread_secure_context[tx_head_free_index].tx_next_free_index; + tx_thread_secure_context[secure_context_index].tx_next_free_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + else + { + secure_context_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + + TX_RESTORE + + if(secure_context_index != TX_INVALID_SECURE_CONTEXT_IDX) { + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* If stack info allocated, allocate a stack & seal. */ stack_mem = malloc(stack_size + TX_THREAD_STACK_SEAL_SIZE); - + if(stack_mem != TX_NULL) { /* Secure stack has been allocated, save in the stack info struct. */ @@ -223,13 +271,13 @@ UCHAR *stack_mem; info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size; info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start; info_ptr -> tx_thread_ptr = thread_ptr; - + /* Seal bottom of stack. */ *(ULONG*)info_ptr -> tx_thread_secure_stack_start = TX_THREAD_STACK_SEAL_VALUE; - - /* Save info pointer in thread. */ - thread_ptr -> tx_thread_secure_stack_context = info_ptr; - + + /* Save secure context id (i.e non-zero base index) in thread. */ + thread_ptr -> tx_thread_secure_stack_context = (VOID *)(secure_context_index + 1); + /* Check if this thread is running by looking at its stack start and PSPLIM_NS */ if(((ULONG) thread_ptr -> tx_thread_stack_start & 0xFFFFFFF8) == __TZ_get_PSPLIM_NS()) { @@ -238,21 +286,26 @@ UCHAR *stack_mem; __set_PSP((ULONG)(info_ptr -> tx_thread_secure_stack_ptr)); } } - + else { + TX_DISABLE + /* Stack not allocated, free the info struct. */ - free(info_ptr); + tx_thread_secure_context[secure_context_index].tx_next_free_index = tx_head_free_index; + tx_head_free_index = secure_context_index; + TX_RESTORE + status = TX_NO_MEMORY; } } - + else { status = TX_NO_MEMORY; } } - + return(status); } @@ -263,7 +316,7 @@ UCHAR *stack_mem; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_free Cortex-M33/AC6 */ -/* 6.1.1 */ +/* 6.1.10 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -298,44 +351,65 @@ UCHAR *stack_mem; /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.10 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; +INT secure_context_index; status = TX_SUCCESS; - - /* Pickup stack info from thread. */ - info_ptr = thread_ptr -> tx_thread_secure_stack_context; - + + /* Pickup stack info id from thread. */ + secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; + /* Make sure function is called from interrupt (threads should not call). */ if (__get_IPSR() == 0) { status = TX_CALLER_ERROR; } - - /* Check that this secure context is for this thread. */ - else if (info_ptr -> tx_thread_ptr != thread_ptr) + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) { status = TX_THREAD_ERROR; } - else { - - /* Free secure stack. */ - free(info_ptr -> tx_thread_secure_stack_limit); - - /* Free info struct. */ - free(info_ptr); - - /* Clear secure context from thread. */ - thread_ptr -> tx_thread_secure_stack_context = 0; + + /* Pickup stack info from static array of secure contexts. */ + info_ptr = &tx_thread_secure_context[secure_context_index]; + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Free secure stack. */ + free(info_ptr -> tx_thread_secure_stack_limit); + + TX_DISABLE + + /* Free info struct. */ + tx_thread_secure_context[secure_context_index].tx_next_free_index = tx_head_free_index; + tx_head_free_index = secure_context_index; + TX_RESTORE + + /* Clear secure context from thread. */ + thread_ptr -> tx_thread_secure_stack_context = 0; + } } - + return(status); } @@ -346,7 +420,7 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_save Cortex-M33/AC6 */ -/* 6.1.7 */ +/* 6.1.10 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -383,6 +457,9 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr; /* resulting in version 6.1.1 */ /* 06-02-2021 Scott Larson Fix stack pointer save, */ /* resulting in version 6.1.7 */ +/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.10 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) @@ -390,38 +467,45 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; +INT secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { return; } - + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) + { + return; + } + /* Pickup the secure context pointer. */ - info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); - + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* Check that this secure context is for this thread. */ if (info_ptr -> tx_thread_ptr != thread_ptr) { return; } - + /* Check that stack pointer is in range */ sp = __get_PSP(); - if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || + if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start)) { return; } - + /* Save stack pointer. */ info_ptr -> tx_thread_secure_stack_ptr = (VOID *) sp; - + /* Set process stack pointer and stack limit to 0 to throw exception when a thread without a secure stack calls a secure function that tries to use secure stack. */ __set_PSPLIM(0); __set_PSP(0); - + return; } @@ -432,7 +516,7 @@ ULONG sp; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_restore Cortex-M33/AC6 */ -/* 6.1.1 */ +/* 6.1.10 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -466,32 +550,42 @@ ULONG sp; /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.10 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; +INT secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { return; } - + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) + { + return; + } + /* Pickup the secure context pointer. */ - info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); - + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* Check that this secure context is for this thread. */ if (info_ptr -> tx_thread_ptr != thread_ptr) { return; } - + /* Set stack pointer and limit. */ __set_PSPLIM((ULONG)info_ptr -> tx_thread_secure_stack_limit); __set_PSP ((ULONG)info_ptr -> tx_thread_secure_stack_ptr); - + return; } diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_initialize.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_initialize.S index e7cd43e8a..a96e30abb 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_initialize.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_initialize.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M33/AC6 */ -/* 6.1.8 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -49,13 +49,17 @@ /* */ /* CALLED BY */ /* */ -/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */ +/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ /* RELEASE HISTORY */ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_handler.c b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_handler.c deleted file mode 100644 index 4d3bbee70..000000000 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_handler.c +++ /dev/null @@ -1,93 +0,0 @@ -/**************************************************************************/ -/* */ -/* Copyright (c) Microsoft Corporation. All rights reserved. */ -/* */ -/* This software is licensed under the Microsoft Software License */ -/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -/* and in the root directory of this software. */ -/* */ -/**************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Thread */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - -#define TX_SOURCE_CODE - - -/* Include necessary system files. */ - -#include "tx_api.h" -#include "tx_thread.h" - -/* Define the global function pointer for stack error handling. If a stack error is - detected and the application has registered a stack error handler, it will be - called via this function pointer. */ - -VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_stack_error_handler Cortex-M33 */ -/* 6.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function processes stack errors detected during run-time. */ -/* */ -/* */ -/* INPUT */ -/* */ -/* thread_ptr Thread control block pointer */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_terminate */ -/* _tx_thread_application_stack_error_handler */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX internal code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ -/**************************************************************************/ -VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) -{ - #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR - /* Is there a thread? */ - if (thread_ptr) - { - /* Terminate the current thread. */ - _tx_thread_terminate(_tx_thread_current_ptr); - } - #endif - - /* Determine if the application has registered an error handler. */ - if (_tx_thread_application_stack_error_handler != TX_NULL) - { - /* Yes, an error handler is present, simply call the application error handler. */ - (_tx_thread_application_stack_error_handler)(thread_ptr); - } -} diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_notify.c b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_notify.c deleted file mode 100644 index d61a27b3c..000000000 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_notify.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************/ -/* */ -/* Copyright (c) Microsoft Corporation. All rights reserved. */ -/* */ -/* This software is licensed under the Microsoft Software License */ -/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -/* and in the root directory of this software. */ -/* */ -/**************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Thread */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - -#define TX_SOURCE_CODE - - -/* Include necessary system files. */ - -#include "tx_api.h" -#include "tx_thread.h" -#include "tx_trace.h" - -extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_stack_error_notify Cortex-M33 */ -/* 6.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function registers an application stack error handler. If */ -/* ThreadX detects a stack error, this application handler is called. */ -/* */ -/* */ -/* INPUT */ -/* */ -/* stack_error_handler Pointer to stack error */ -/* handler, TX_NULL to disable */ -/* */ -/* OUTPUT */ -/* */ -/* status Service return status */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ -/**************************************************************************/ -UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) -{ - -TX_INTERRUPT_SAVE_AREA - - /* Disable interrupts. */ - TX_DISABLE - - /* Make entry in event log. */ - TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS) - - /* Make entry in event log. */ - TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT - - /* Setup global thread stack error handler. */ - _tx_thread_application_stack_error_handler = stack_error_handler; - - /* Restore interrupts. */ - TX_RESTORE - - /* Return success to caller. */ - return(TX_SUCCESS); -} diff --git a/ports_module/cortex_m33/gnu/inc/tx_port.h b/ports_module/cortex_m33/gnu/inc/tx_port.h index e35476022..0b44956c9 100644 --- a/ports_module/cortex_m33/gnu/inc/tx_port.h +++ b/ports_module/cortex_m33/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M33 */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -64,13 +64,18 @@ /* 10-15-2021 Scott Larson Modified comment(s), improved */ /* stack check error handling, */ /* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ +/* 01-31-2022 Scott Larson Modified comment(s), unified */ /* this file across compilers, */ /* fixed predefined macro, */ /* resulting in version 6.1.10 */ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -188,6 +193,12 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -582,7 +593,7 @@ ULONG _tx_misra_ipsr_get(VOID); #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) /* Initialize secure stacks for threads calling secure functions. */ extern void _tx_thread_secure_stack_initialize(void); -#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to @@ -695,7 +706,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33 Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33 Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S index ff454e9c6..af8be2baf 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S @@ -29,7 +29,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M33/GNU */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -73,6 +73,9 @@ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -425,14 +428,7 @@ _skip_secure_restore: LDR r2, [r0, #0x74] // Pickup MPU address of data region CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup - // Is the MPU already set up for this module? - MOV r1, #2 // Select MPU region 2 - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 2 LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 2 - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration // Use alias registers to quickly load MPU LDR r2, =0xE000ED98 // Get region register diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack.c index 9375062c6..13bfc29a1 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack.c @@ -23,7 +23,7 @@ #include "tx_api.h" -/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, +/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, no secure stack functionality is needed. */ #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) @@ -44,8 +44,14 @@ #define TX_THREAD_STACK_SEAL_SIZE 8 #define TX_THREAD_STACK_SEAL_VALUE 0xFEF5EDA5 -/* Secure stack info struct to hold stack start, stack limit, - current stack pointer, and pointer to owning thread. +/* max number of Secure context */ +#ifndef TX_MAX_SECURE_CONTEXTS +#define TX_MAX_SECURE_CONTEXTS 32 +#endif +#define TX_INVALID_SECURE_CONTEXT_IDX (-1) + +/* Secure stack info struct to hold stack start, stack limit, + current stack pointer, and pointer to owning thread. This will be allocated for each thread with a secure stack. */ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT { @@ -53,8 +59,14 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */ VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */ TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */ + INT tx_next_free_index; /* Next free index of free secure context */ } TX_THREAD_SECURE_STACK_INFO; +/* Static secure contexts */ +static TX_THREAD_SECURE_STACK_INFO tx_thread_secure_context[TX_MAX_SECURE_CONTEXTS]; +/* Head of free secure context */ +static INT tx_head_free_index = 0U; + /**************************************************************************/ @@ -62,7 +74,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_initialize Cortex-M33/GNU */ -/* 6.1.8 */ +/* 6.1.10 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -94,10 +106,13 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ -/* 08-02-2021 Scott Larson Change name, execute in */ +/* 06-02-2021 Scott Larson Change name, execute in */ /* handler mode, */ /* disable optimizations, */ -/* resulting in version 6.1.8 */ +/* resulting in version 6.1.7 */ +/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.10 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry, optimize(0))) @@ -106,6 +121,7 @@ UINT _tx_thread_secure_mode_stack_initialize(void) UINT status; ULONG control; ULONG ipsr; +INT index; /* Make sure function is called from interrupt (threads should not call). */ asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ @@ -119,12 +135,26 @@ ULONG ipsr; asm volatile("MRS %0, CONTROL" : "=r" (control)); /* Get CONTROL register. */ control |= 2; /* Use PSP. */ asm volatile("MSR CONTROL, %0" :: "r" (control)); /* Set CONTROL register. */ - + /* Set process stack pointer and stack limit to 0 to throw exception when a thread without a secure stack calls a secure function that tries to use secure stack. */ asm volatile("MSR PSPLIM, %0" :: "r" (0)); asm volatile("MSR PSP, %0" :: "r" (0)); - + + for (index = 0; index < TX_MAX_SECURE_CONTEXTS; index++) + { + + /* Check last index and mark next free to invalid index */ + if(index == (TX_MAX_SECURE_CONTEXTS - 1)) + { + tx_thread_secure_context[index].tx_next_free_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + else + { + tx_thread_secure_context[index].tx_next_free_index = index + 1; + } + } + status = TX_SUCCESS; } return status; @@ -137,7 +167,7 @@ ULONG ipsr; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_allocate Cortex-M33/GNU */ -/* 6.1.1 */ +/* 6.1.11a */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -160,9 +190,7 @@ ULONG ipsr; /* */ /* CALLS */ /* */ -/* calloc Compiler's calloc function */ /* malloc Compiler's malloc function */ -/* free Compiler's free() function */ /* */ /* CALLED BY */ /* */ @@ -176,19 +204,27 @@ ULONG ipsr; /* 10-16-2020 Scott Larson Modified comment(s), */ /* added stack sealing, */ /* resulting in version 6.1.1 */ +/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.10 */ +/* 05-02-2022 Scott Larson Modified comment(s), added */ +/* TX_INTERRUPT_SAVE_AREA, */ +/* resulting in version 6.1.11a*/ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; UCHAR *stack_mem; ULONG ipsr; ULONG psplim_ns; +INT secure_context_index; status = TX_SUCCESS; - + /* Make sure function is called from interrupt (threads should not call). */ asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ if (ipsr == 0) @@ -199,23 +235,38 @@ ULONG psplim_ns; { status = TX_SIZE_ERROR; } - + /* Check if thread already has secure stack allocated. */ else if (thread_ptr -> tx_thread_secure_stack_context != 0) { status = TX_THREAD_ERROR; } - + else { - /* Allocate space for secure stack info. */ - info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO)); - - if(info_ptr != TX_NULL) + TX_DISABLE + + /* Allocate free index for secure stack info. */ + if(tx_head_free_index != TX_INVALID_SECURE_CONTEXT_IDX) + { + secure_context_index = tx_head_free_index; + tx_head_free_index = tx_thread_secure_context[tx_head_free_index].tx_next_free_index; + tx_thread_secure_context[secure_context_index].tx_next_free_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + else + { + secure_context_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + + TX_RESTORE + + if(secure_context_index != TX_INVALID_SECURE_CONTEXT_IDX) { + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* If stack info allocated, allocate a stack & seal. */ stack_mem = malloc(stack_size + TX_THREAD_STACK_SEAL_SIZE); - + if(stack_mem != TX_NULL) { /* Secure stack has been allocated, save in the stack info struct. */ @@ -223,13 +274,13 @@ ULONG psplim_ns; info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size; info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start; info_ptr -> tx_thread_ptr = thread_ptr; - + /* Seal bottom of stack. */ *(ULONG*)info_ptr -> tx_thread_secure_stack_start = TX_THREAD_STACK_SEAL_VALUE; - - /* Save info pointer in thread. */ - thread_ptr -> tx_thread_secure_stack_context = info_ptr; - + + /* Save secure context id (i.e non-zero base index) in thread. */ + thread_ptr -> tx_thread_secure_stack_context = (VOID *)(secure_context_index + 1); + /* Check if this thread is running by looking at its stack start and PSPLIM_NS */ asm volatile("MRS %0, PSPLIM_NS" : "=r" (psplim_ns)); /* Get PSPLIM_NS register. */ if(((ULONG) thread_ptr -> tx_thread_stack_start & 0xFFFFFFF8) == psplim_ns) @@ -239,21 +290,26 @@ ULONG psplim_ns; asm volatile("MSR PSP, %0" :: "r" ((ULONG)(info_ptr -> tx_thread_secure_stack_ptr))); } } - + else { + TX_DISABLE + /* Stack not allocated, free the info struct. */ - free(info_ptr); + tx_thread_secure_context[secure_context_index].tx_next_free_index = tx_head_free_index; + tx_head_free_index = secure_context_index; + TX_RESTORE + status = TX_NO_MEMORY; } } - + else { status = TX_NO_MEMORY; } } - + return(status); } @@ -264,7 +320,7 @@ ULONG psplim_ns; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_free Cortex-M33/GNU */ -/* 6.1.1 */ +/* 6.1.10 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -298,46 +354,67 @@ ULONG psplim_ns; /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.10 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG ipsr; +INT secure_context_index; status = TX_SUCCESS; - - /* Pickup stack info from thread. */ - info_ptr = thread_ptr -> tx_thread_secure_stack_context; - + + /* Pickup stack info id from thread. */ + secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; + /* Make sure function is called from interrupt (threads should not call). */ asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ if (ipsr == 0) { status = TX_CALLER_ERROR; } - - /* Check that this secure context is for this thread. */ - else if (info_ptr -> tx_thread_ptr != thread_ptr) + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) { status = TX_THREAD_ERROR; } - else { - - /* Free secure stack. */ - free(info_ptr -> tx_thread_secure_stack_limit); - - /* Free info struct. */ - free(info_ptr); - - /* Clear secure context from thread. */ - thread_ptr -> tx_thread_secure_stack_context = 0; + + /* Pickup stack info from static array of secure contexts. */ + info_ptr = &tx_thread_secure_context[secure_context_index]; + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Free secure stack. */ + free(info_ptr -> tx_thread_secure_stack_limit); + + TX_DISABLE + + /* Free info struct. */ + tx_thread_secure_context[secure_context_index].tx_next_free_index = tx_head_free_index; + tx_head_free_index = secure_context_index; + TX_RESTORE + + /* Clear secure context from thread. */ + thread_ptr -> tx_thread_secure_stack_context = 0; + } } - + return(status); } @@ -348,7 +425,7 @@ ULONG ipsr; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_save Cortex-M33/GNU */ -/* 6.1.7 */ +/* 6.1.10 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -382,6 +459,9 @@ ULONG ipsr; /* resulting in version 6.1.1 */ /* 06-02-2021 Scott Larson Fix stack pointer save, */ /* resulting in version 6.1.7 */ +/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.10 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) @@ -390,6 +470,7 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; ULONG ipsr; +INT secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; /* This function should be called from scheduler only. */ asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ @@ -397,32 +478,38 @@ ULONG ipsr; { return; } - + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) + { + return; + } + /* Pickup the secure context pointer. */ - info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); - + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* Check that this secure context is for this thread. */ if (info_ptr -> tx_thread_ptr != thread_ptr) { return; } - + /* Check that stack pointer is in range */ asm volatile("MRS %0, PSP" : "=r" (sp)); /* Get PSP register. */ - if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || + if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start)) { return; } - + /* Save stack pointer. */ info_ptr -> tx_thread_secure_stack_ptr = (VOID *) sp; - + /* Set process stack pointer and stack limit to 0 to throw exception when a thread without a secure stack calls a secure function that tries to use secure stack. */ asm volatile("MSR PSPLIM, %0" :: "r" (0)); asm volatile("MSR PSP, %0" :: "r" (0)); - + return; } @@ -433,7 +520,7 @@ ULONG ipsr; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_restore Cortex-M33/GNU */ -/* 6.1.1 */ +/* 6.1.10 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -465,6 +552,9 @@ ULONG ipsr; /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.10 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) @@ -472,6 +562,7 @@ void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG ipsr; +INT secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; /* This function should be called from scheduler only. */ asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ @@ -479,20 +570,26 @@ ULONG ipsr; { return; } - + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) + { + return; + } + /* Pickup the secure context pointer. */ - info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); - + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* Check that this secure context is for this thread. */ if (info_ptr -> tx_thread_ptr != thread_ptr) { return; } - + /* Set stack pointer and limit. */ asm volatile("MSR PSPLIM, %0" :: "r" ((ULONG)info_ptr -> tx_thread_secure_stack_limit)); asm volatile("MSR PSP, %0" :: "r" ((ULONG)info_ptr -> tx_thread_secure_stack_ptr)); - + return; } diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_initialize.S b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_initialize.S index 9e9642fcb..a9f899f66 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_initialize.S +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_initialize.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M33/GNU */ -/* 6.1.7 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -49,13 +49,17 @@ /* */ /* CALLED BY */ /* */ -/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */ +/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ /* RELEASE HISTORY */ /* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_error_handler.c b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_error_handler.c deleted file mode 100644 index 4d3bbee70..000000000 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_error_handler.c +++ /dev/null @@ -1,93 +0,0 @@ -/**************************************************************************/ -/* */ -/* Copyright (c) Microsoft Corporation. All rights reserved. */ -/* */ -/* This software is licensed under the Microsoft Software License */ -/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -/* and in the root directory of this software. */ -/* */ -/**************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Thread */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - -#define TX_SOURCE_CODE - - -/* Include necessary system files. */ - -#include "tx_api.h" -#include "tx_thread.h" - -/* Define the global function pointer for stack error handling. If a stack error is - detected and the application has registered a stack error handler, it will be - called via this function pointer. */ - -VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_stack_error_handler Cortex-M33 */ -/* 6.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function processes stack errors detected during run-time. */ -/* */ -/* */ -/* INPUT */ -/* */ -/* thread_ptr Thread control block pointer */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_terminate */ -/* _tx_thread_application_stack_error_handler */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX internal code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ -/**************************************************************************/ -VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) -{ - #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR - /* Is there a thread? */ - if (thread_ptr) - { - /* Terminate the current thread. */ - _tx_thread_terminate(_tx_thread_current_ptr); - } - #endif - - /* Determine if the application has registered an error handler. */ - if (_tx_thread_application_stack_error_handler != TX_NULL) - { - /* Yes, an error handler is present, simply call the application error handler. */ - (_tx_thread_application_stack_error_handler)(thread_ptr); - } -} diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_error_notify.c b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_error_notify.c deleted file mode 100644 index d61a27b3c..000000000 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_error_notify.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************/ -/* */ -/* Copyright (c) Microsoft Corporation. All rights reserved. */ -/* */ -/* This software is licensed under the Microsoft Software License */ -/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -/* and in the root directory of this software. */ -/* */ -/**************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Thread */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - -#define TX_SOURCE_CODE - - -/* Include necessary system files. */ - -#include "tx_api.h" -#include "tx_thread.h" -#include "tx_trace.h" - -extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_stack_error_notify Cortex-M33 */ -/* 6.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function registers an application stack error handler. If */ -/* ThreadX detects a stack error, this application handler is called. */ -/* */ -/* */ -/* INPUT */ -/* */ -/* stack_error_handler Pointer to stack error */ -/* handler, TX_NULL to disable */ -/* */ -/* OUTPUT */ -/* */ -/* status Service return status */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ -/**************************************************************************/ -UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) -{ - -TX_INTERRUPT_SAVE_AREA - - /* Disable interrupts. */ - TX_DISABLE - - /* Make entry in event log. */ - TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS) - - /* Make entry in event log. */ - TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT - - /* Setup global thread stack error handler. */ - _tx_thread_application_stack_error_handler = stack_error_handler; - - /* Restore interrupts. */ - TX_RESTORE - - /* Return success to caller. */ - return(TX_SUCCESS); -} diff --git a/ports_module/cortex_m33/iar/inc/tx_port.h b/ports_module/cortex_m33/iar/inc/tx_port.h index e35476022..0b44956c9 100644 --- a/ports_module/cortex_m33/iar/inc/tx_port.h +++ b/ports_module/cortex_m33/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M33 */ -/* 6.1.11 */ +/* 6.1.12 */ /* */ /* AUTHOR */ /* */ @@ -64,13 +64,18 @@ /* 10-15-2021 Scott Larson Modified comment(s), improved */ /* stack check error handling, */ /* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ +/* 01-31-2022 Scott Larson Modified comment(s), unified */ /* this file across compilers, */ /* fixed predefined macro, */ /* resulting in version 6.1.10 */ /* 04-25-2022 Scott Larson Modified comments and added */ /* volatile to registers, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* described BASEPRI usage, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -188,6 +193,12 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif +/* By default, ThreadX for Cortex-M uses the PRIMASK register to enable/disable interrupts. +If using BASEPRI is desired, define the following two symbols for both c and assembly files: +TX_PORT_USE_BASEPRI - This tells ThreadX to use BASEPRI instead of PRIMASK. +TX_PORT_BASEPRI = (priority_mask << (8 - number_priority_bits)) - this defines the maximum priority level to mask. +Any interrupt with a higher priority than priority_mask will not be masked, thus the interrupt will run. +*/ /* Define various constants for the ThreadX Cortex-M port. */ @@ -582,7 +593,7 @@ ULONG _tx_misra_ipsr_get(VOID); #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) /* Initialize secure stacks for threads calling secure functions. */ extern void _tx_thread_secure_stack_initialize(void); -#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif /* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to @@ -695,7 +706,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33 Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33 Version 6.1.12 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s index e4d4bfd36..3242fac26 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s @@ -42,7 +42,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M33/IAR */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -84,6 +84,9 @@ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -421,14 +424,7 @@ _skip_secure_restore: LDR r2, [r0, #0x74] // Pickup MPU address of data region CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup - // Is the MPU already set up for this module? - MOV r1, #2 // Select MPU region 2 - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 2 LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 2 - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration // Use alias registers to quickly load MPU LDR r2, =0xE000ED98 // Get region register diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack.c index 64006f59f..83e6c37dc 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack.c @@ -23,7 +23,7 @@ #include "tx_api.h" -/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, +/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, no secure stack functionality is needed. */ #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) @@ -45,8 +45,14 @@ #define TX_THREAD_STACK_SEAL_SIZE 8 #define TX_THREAD_STACK_SEAL_VALUE 0xFEF5EDA5 -/* Secure stack info struct to hold stack start, stack limit, - current stack pointer, and pointer to owning thread. +/* max number of Secure context */ +#ifndef TX_MAX_SECURE_CONTEXTS +#define TX_MAX_SECURE_CONTEXTS 32 +#endif +#define TX_INVALID_SECURE_CONTEXT_IDX (-1) + +/* Secure stack info struct to hold stack start, stack limit, + current stack pointer, and pointer to owning thread. This will be allocated for each thread with a secure stack. */ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT { @@ -54,8 +60,14 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */ VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */ TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */ + INT tx_next_free_index; /* Next free index of free secure context */ } TX_THREAD_SECURE_STACK_INFO; +/* Static secure contexts */ +static TX_THREAD_SECURE_STACK_INFO tx_thread_secure_context[TX_MAX_SECURE_CONTEXTS]; +/* Head of free secure context */ +static INT tx_head_free_index = 0U; + /**************************************************************************/ @@ -63,7 +75,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_initialize Cortex-M33/IAR */ -/* 6.1.8 */ +/* 6.1.10 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -98,15 +110,19 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ -/* 08-02-2021 Scott Larson Change name, execute in */ +/* 06-02-2021 Scott Larson Change name, execute in */ /* handler mode, */ -/* resulting in version 6.1.8 */ +/* resulting in version 6.1.7 */ +/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.10 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) { UINT status; +INT index; /* Make sure function is called from interrupt (threads should not call). */ if (__get_IPSR() == 0) @@ -117,12 +133,26 @@ UINT status; { /* Set secure mode to use PSP. */ __set_CONTROL(__get_CONTROL() | 2); - + /* Set process stack pointer and stack limit to 0 to throw exception when a thread without a secure stack calls a secure function that tries to use secure stack. */ __set_PSPLIM(0); __set_PSP(0); - + + for (index = 0; index < TX_MAX_SECURE_CONTEXTS; index++) + { + + /* Check last index and mark next free to invalid index */ + if(index == (TX_MAX_SECURE_CONTEXTS - 1)) + { + tx_thread_secure_context[index].tx_next_free_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + else + { + tx_thread_secure_context[index].tx_next_free_index = index + 1; + } + } + status = TX_SUCCESS; } return status; @@ -135,7 +165,7 @@ UINT status; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_allocate Cortex-M33/IAR */ -/* 6.1.1 */ +/* 6.1.11a */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -159,9 +189,7 @@ UINT status; /* CALLS */ /* */ /* __get_IPSR Intrinsic to get IPSR */ -/* calloc Compiler's calloc function */ /* malloc Compiler's malloc function */ -/* free Compiler's free() function */ /* __set_PSPLIM Intrinsic to set PSP limit */ /* __set_PSP Intrinsic to set PSP */ /* __TZ_get_PSPLIM_NS Intrinsic to get NS PSP */ @@ -178,17 +206,25 @@ UINT status; /* 10-16-2020 Scott Larson Modified comment(s), */ /* added stack sealing, */ /* resulting in version 6.1.1 */ +/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.10 */ +/* 05-02-2022 Scott Larson Modified comment(s), added */ +/* TX_INTERRUPT_SAVE_AREA, */ +/* resulting in version 6.1.11a*/ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; UCHAR *stack_mem; +INT secure_context_index; status = TX_SUCCESS; - + /* Make sure function is called from interrupt (threads should not call). */ if (__get_IPSR() == 0) { @@ -198,23 +234,38 @@ UCHAR *stack_mem; { status = TX_SIZE_ERROR; } - + /* Check if thread already has secure stack allocated. */ else if (thread_ptr -> tx_thread_secure_stack_context != 0) { status = TX_THREAD_ERROR; } - + else { - /* Allocate space for secure stack info. */ - info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO)); - - if(info_ptr != TX_NULL) + TX_DISABLE + + /* Allocate free index for secure stack info. */ + if(tx_head_free_index != TX_INVALID_SECURE_CONTEXT_IDX) + { + secure_context_index = tx_head_free_index; + tx_head_free_index = tx_thread_secure_context[tx_head_free_index].tx_next_free_index; + tx_thread_secure_context[secure_context_index].tx_next_free_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + else + { + secure_context_index = TX_INVALID_SECURE_CONTEXT_IDX; + } + + TX_RESTORE + + if(secure_context_index != TX_INVALID_SECURE_CONTEXT_IDX) { + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* If stack info allocated, allocate a stack & seal. */ stack_mem = malloc(stack_size + TX_THREAD_STACK_SEAL_SIZE); - + if(stack_mem != TX_NULL) { /* Secure stack has been allocated, save in the stack info struct. */ @@ -222,13 +273,13 @@ UCHAR *stack_mem; info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size; info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start; info_ptr -> tx_thread_ptr = thread_ptr; - + /* Seal bottom of stack. */ *(ULONG*)info_ptr -> tx_thread_secure_stack_start = TX_THREAD_STACK_SEAL_VALUE; - - /* Save info pointer in thread. */ - thread_ptr -> tx_thread_secure_stack_context = info_ptr; - + + /* Save secure context id (i.e non-zero base index) in thread. */ + thread_ptr -> tx_thread_secure_stack_context = (VOID *)(secure_context_index + 1); + /* Check if this thread is running by looking at its stack start and PSPLIM_NS */ if(((ULONG) thread_ptr -> tx_thread_stack_start & 0xFFFFFFF8) == __TZ_get_PSPLIM_NS()) { @@ -237,21 +288,26 @@ UCHAR *stack_mem; __set_PSP((ULONG)(info_ptr -> tx_thread_secure_stack_ptr)); } } - + else { + TX_DISABLE + /* Stack not allocated, free the info struct. */ - free(info_ptr); + tx_thread_secure_context[secure_context_index].tx_next_free_index = tx_head_free_index; + tx_head_free_index = secure_context_index; + TX_RESTORE + status = TX_NO_MEMORY; } } - + else { status = TX_NO_MEMORY; } } - + return(status); } @@ -262,7 +318,7 @@ UCHAR *stack_mem; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_free Cortex-M33/IAR */ -/* 6.1.1 */ +/* 6.1.11a */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -297,44 +353,68 @@ UCHAR *stack_mem; /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.10 */ +/* 05-02-2022 Scott Larson Modified comment(s), added */ +/* TX_INTERRUPT_SAVE_AREA, */ +/* resulting in version 6.1.11a*/ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { +TX_INTERRUPT_SAVE_AREA UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; +INT secure_context_index; status = TX_SUCCESS; - - /* Pickup stack info from thread. */ - info_ptr = thread_ptr -> tx_thread_secure_stack_context; - + + /* Pickup stack info id from thread. */ + secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; + /* Make sure function is called from interrupt (threads should not call). */ if (__get_IPSR() == 0) { status = TX_CALLER_ERROR; } - - /* Check that this secure context is for this thread. */ - else if (info_ptr -> tx_thread_ptr != thread_ptr) + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) { status = TX_THREAD_ERROR; } - else { - - /* Free secure stack. */ - free(info_ptr -> tx_thread_secure_stack_limit); - - /* Free info struct. */ - free(info_ptr); - - /* Clear secure context from thread. */ - thread_ptr -> tx_thread_secure_stack_context = 0; + + /* Pickup stack info from static array of secure contexts. */ + info_ptr = &tx_thread_secure_context[secure_context_index]; + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Free secure stack. */ + free(info_ptr -> tx_thread_secure_stack_limit); + + TX_DISABLE + + /* Free info struct. */ + tx_thread_secure_context[secure_context_index].tx_next_free_index = tx_head_free_index; + tx_head_free_index = secure_context_index; + TX_RESTORE + + /* Clear secure context from thread. */ + thread_ptr -> tx_thread_secure_stack_context = 0; + } } - + return(status); } @@ -345,7 +425,7 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_save Cortex-M33/IAR */ -/* 6.1.7 */ +/* 6.1.10 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -382,6 +462,9 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr; /* resulting in version 6.1.1 */ /* 06-02-2021 Scott Larson Fix stack pointer save, */ /* resulting in version 6.1.7 */ +/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.10 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) @@ -389,38 +472,45 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; +INT secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { return; } - + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) + { + return; + } + /* Pickup the secure context pointer. */ - info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); - + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* Check that this secure context is for this thread. */ if (info_ptr -> tx_thread_ptr != thread_ptr) { return; } - + /* Check that stack pointer is in range */ sp = __get_PSP(); - if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || + if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start)) { return; } - + /* Save stack pointer. */ info_ptr -> tx_thread_secure_stack_ptr = (VOID *) sp; - + /* Set process stack pointer and stack limit to 0 to throw exception when a thread without a secure stack calls a secure function that tries to use secure stack. */ __set_PSPLIM(0); __set_PSP(0); - + return; } @@ -431,7 +521,7 @@ ULONG sp; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_restore Cortex-M33/IAR */ -/* 6.1.1 */ +/* 6.1.10 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -465,32 +555,42 @@ ULONG sp; /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ +/* secure stack allocation, */ +/* resulting in version 6.1.10 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; +INT secure_context_index = (INT)thread_ptr -> tx_thread_secure_stack_context - 1; /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { return; } - + + /* Check if secure context index is in valid range. */ + else if (secure_context_index < 0 || secure_context_index >= TX_MAX_SECURE_CONTEXTS) + { + return; + } + /* Pickup the secure context pointer. */ - info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); - + info_ptr = &tx_thread_secure_context[secure_context_index]; + /* Check that this secure context is for this thread. */ if (info_ptr -> tx_thread_ptr != thread_ptr) { return; } - + /* Set stack pointer and limit. */ __set_PSPLIM((ULONG)info_ptr -> tx_thread_secure_stack_limit); __set_PSP ((ULONG)info_ptr -> tx_thread_secure_stack_ptr); - + return; } diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_notify.c b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_initialize.s similarity index 71% rename from ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_notify.c rename to ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_initialize.s index 75ad1f32c..4fb1bb3c2 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_notify.c +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_initialize.s @@ -20,77 +20,59 @@ /**************************************************************************/ /**************************************************************************/ -#define TX_SOURCE_CODE - - -/* Include necessary system files. */ - -#include "tx_api.h" -#include "tx_thread.h" -#include "tx_trace.h" - -extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); - + SECTION `.text`:CODE:NOROOT(2) + THUMB /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_error_notify Cortex-M23 */ -/* 6.1 */ +/* _tx_thread_secure_stack_initialize Cortex-M33/IAR */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function registers an application stack error handler. If */ -/* ThreadX detects a stack error, this application handler is called. */ -/* */ +/* This function enters the SVC handler to initialize a secure stack. */ /* */ /* INPUT */ /* */ -/* stack_error_handler Pointer to stack error */ -/* handler, TX_NULL to disable */ +/* none */ /* */ /* OUTPUT */ /* */ -/* status Service return status */ +/* none */ /* */ /* CALLS */ /* */ -/* None */ +/* SVC 3 */ /* */ /* CALLED BY */ /* */ -/* Application Code */ +/* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ /* RELEASE HISTORY */ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 07-29-2022 Scott Larson Modified comments and changed */ +/* secure stack initialization */ +/* macro to port-specific, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ -UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) -{ - -TX_INTERRUPT_SAVE_AREA - - /* Disable interrupts. */ - TX_DISABLE - - /* Make entry in event log. */ - TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS) - - /* Make entry in event log. */ - TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT - - /* Setup global thread stack error handler. */ - _tx_thread_application_stack_error_handler = stack_error_handler; - - /* Restore interrupts. */ - TX_RESTORE - - /* Return success to caller. */ - return(TX_SUCCESS); -} +// VOID _tx_thread_secure_stack_initialize(VOID) +// { + EXPORT _tx_thread_secure_stack_initialize +_tx_thread_secure_stack_initialize: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + CPSIE i // Enable interrupts for SVC call + SVC 3 + CPSID i // Disable interrupts +#else + MOV r0, #0xFF // Feature not enabled +#endif + BX lr + END diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_handler.c b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_handler.c deleted file mode 100644 index 4d3bbee70..000000000 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_handler.c +++ /dev/null @@ -1,93 +0,0 @@ -/**************************************************************************/ -/* */ -/* Copyright (c) Microsoft Corporation. All rights reserved. */ -/* */ -/* This software is licensed under the Microsoft Software License */ -/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -/* and in the root directory of this software. */ -/* */ -/**************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Thread */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - -#define TX_SOURCE_CODE - - -/* Include necessary system files. */ - -#include "tx_api.h" -#include "tx_thread.h" - -/* Define the global function pointer for stack error handling. If a stack error is - detected and the application has registered a stack error handler, it will be - called via this function pointer. */ - -VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_stack_error_handler Cortex-M33 */ -/* 6.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function processes stack errors detected during run-time. */ -/* */ -/* */ -/* INPUT */ -/* */ -/* thread_ptr Thread control block pointer */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_terminate */ -/* _tx_thread_application_stack_error_handler */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX internal code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ -/**************************************************************************/ -VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) -{ - #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR - /* Is there a thread? */ - if (thread_ptr) - { - /* Terminate the current thread. */ - _tx_thread_terminate(_tx_thread_current_ptr); - } - #endif - - /* Determine if the application has registered an error handler. */ - if (_tx_thread_application_stack_error_handler != TX_NULL) - { - /* Yes, an error handler is present, simply call the application error handler. */ - (_tx_thread_application_stack_error_handler)(thread_ptr); - } -} diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_notify.c b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_notify.c deleted file mode 100644 index d61a27b3c..000000000 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_notify.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************/ -/* */ -/* Copyright (c) Microsoft Corporation. All rights reserved. */ -/* */ -/* This software is licensed under the Microsoft Software License */ -/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -/* and in the root directory of this software. */ -/* */ -/**************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Thread */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - -#define TX_SOURCE_CODE - - -/* Include necessary system files. */ - -#include "tx_api.h" -#include "tx_thread.h" -#include "tx_trace.h" - -extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_stack_error_notify Cortex-M33 */ -/* 6.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function registers an application stack error handler. If */ -/* ThreadX detects a stack error, this application handler is called. */ -/* */ -/* */ -/* INPUT */ -/* */ -/* stack_error_handler Pointer to stack error */ -/* handler, TX_NULL to disable */ -/* */ -/* OUTPUT */ -/* */ -/* status Service return status */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ -/**************************************************************************/ -UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) -{ - -TX_INTERRUPT_SAVE_AREA - - /* Disable interrupts. */ - TX_DISABLE - - /* Make entry in event log. */ - TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS) - - /* Make entry in event log. */ - TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT - - /* Setup global thread stack error handler. */ - _tx_thread_application_stack_error_handler = stack_error_handler; - - /* Restore interrupts. */ - TX_RESTORE - - /* Return success to caller. */ - return(TX_SUCCESS); -} diff --git a/ports_module/cortex_m4/ac5/inc/txm_module_port.h b/ports_module/cortex_m4/ac5/inc/txm_module_port.h index d4eeb6505..f375107e7 100644 --- a/ports_module/cortex_m4/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_m4/ac5/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M4/AC5 */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,6 +41,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enabled user-defined and */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -111,6 +114,60 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 #endif +/* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) + are not used by ThreadX. These may be defined by the user. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 + + +/* Users can define these default MPU configuration values. + + If TXM_MODULE_MPU_DEFAULT is *not* defined, the MPU is disabled + when a thread that is not owned by a module is running + and the defines below are not used. + + If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the + below values when a thread that is not owned by a module is running. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_15 0 + + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.s index 11943fcfc..6067dd44d 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.s @@ -40,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M4/AC5 */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,6 +76,10 @@ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, optional */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -385,26 +389,33 @@ __tx_ts_restore LDR r0, =0xE000ED94 // Build MPU control reg address MOV r3, #0 // Build disable value + CPSID i // Disable interrupts STR r3, [r0] // Disable MPU LDR r0, [r1, #0x90] // Pickup the module instance pointer +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r0, default_mpu // Is this thread owned by a module? No, default MPU setup +#else CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup - +#endif + LDR r2, [r0, #0x8C] // Pickup MPU region 5 address +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r2, default_mpu // Is protection required for this module? No, default MPU setup +#else CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup - - // Is the MPU already set up for this module? - MOV r1, #5 // Select region 5 from MPU - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 5 +#endif LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 5 - BIC r2, r2, #0x10 // Clear VALID bit - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block +#ifdef TXM_MODULE_MPU_DEFAULT + B config_mpu // configure MPU for module +default_mpu: + LDR r0, =txm_module_default_mpu_registers // default MPU configuration +#endif + +config_mpu: LDM r0!,{r2-r9} // Load MPU regions 0-3 STM r1,{r2-r9} // Store MPU regions 0-3 LDM r0!,{r2-r9} // Load MPU regions 4-7 @@ -412,6 +423,7 @@ __tx_ts_restore #ifdef TXM_MODULE_MANAGER_16_MPU LDM r0!,{r2-r9} // Load MPU regions 8-11 STM r1,{r2-r9} // Store MPU regions 8-11 + // Regions 12-15 are reserved for the user to define. LDM r0,{r2-r9} // Load MPU regions 12-15 STM r1,{r2-r9} // Store MPU regions 12-15 #endif @@ -420,6 +432,7 @@ _tx_enable_mpu MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU skip_mpu_setup + CPSIE i // Enable interrupts LDMIA r12!, {LR} // Pickup LR #ifdef __TARGET_FPU_VFP TST LR, #0x10 // Determine if the VFP extended frame is present @@ -573,14 +586,14 @@ _tx_no_lazy_clear: #endif /* Copy kernel hardware stack to module thread stack. */ - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} + LDM r3!, {r1-r2} // Get r0, r1 from kernel stack + STM r0!, {r1-r2} // Insert r0, r1 into thread stack + LDM r3!, {r1-r2} // Get r2, r3 from kernel stack + STM r0!, {r1-r2} // Insert r2, r3 into thread stack + LDM r3!, {r1-r2} // Get r12, lr from kernel stack + STM r0!, {r1-r2} // Insert r12, lr into thread stack + LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack + STM r0!, {r1-r2} // Insert pc, xpsr into thread stack SUB r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index dcc8d2aa0..36127034f 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -25,6 +25,43 @@ #include "tx_api.h" #include "txm_module.h" +#ifdef TXM_MODULE_MPU_DEFAULT +const ULONG txm_module_default_mpu_registers[32] = + { + TXM_MODULE_MPU_DEFAULT_RBAR_0, + TXM_MODULE_MPU_DEFAULT_RASR_0, + TXM_MODULE_MPU_DEFAULT_RBAR_1, + TXM_MODULE_MPU_DEFAULT_RASR_1, + TXM_MODULE_MPU_DEFAULT_RBAR_2, + TXM_MODULE_MPU_DEFAULT_RASR_2, + TXM_MODULE_MPU_DEFAULT_RBAR_3, + TXM_MODULE_MPU_DEFAULT_RASR_3, + TXM_MODULE_MPU_DEFAULT_RBAR_4, + TXM_MODULE_MPU_DEFAULT_RASR_4, + TXM_MODULE_MPU_DEFAULT_RBAR_5, + TXM_MODULE_MPU_DEFAULT_RASR_5, + TXM_MODULE_MPU_DEFAULT_RBAR_6, + TXM_MODULE_MPU_DEFAULT_RASR_6, + TXM_MODULE_MPU_DEFAULT_RBAR_7, + TXM_MODULE_MPU_DEFAULT_RASR_7, + TXM_MODULE_MPU_DEFAULT_RBAR_8, + TXM_MODULE_MPU_DEFAULT_RASR_8, + TXM_MODULE_MPU_DEFAULT_RBAR_9, + TXM_MODULE_MPU_DEFAULT_RASR_9, + TXM_MODULE_MPU_DEFAULT_RBAR_10, + TXM_MODULE_MPU_DEFAULT_RASR_10, + TXM_MODULE_MPU_DEFAULT_RBAR_11, + TXM_MODULE_MPU_DEFAULT_RASR_11, + TXM_MODULE_MPU_DEFAULT_RBAR_12, + TXM_MODULE_MPU_DEFAULT_RASR_12, + TXM_MODULE_MPU_DEFAULT_RBAR_13, + TXM_MODULE_MPU_DEFAULT_RASR_13, + TXM_MODULE_MPU_DEFAULT_RBAR_14, + TXM_MODULE_MPU_DEFAULT_RASR_14, + TXM_MODULE_MPU_DEFAULT_RBAR_15, + TXM_MODULE_MPU_DEFAULT_RASR_15 + }; +#endif /**************************************************************************/ /* */ @@ -231,7 +268,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M4 */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -267,10 +304,10 @@ UINT srd_bit_index; /* 9 Module shared memory region */ /* 10 Module shared memory region */ /* 11 Module shared memory region */ -/* 12 Unused region */ -/* 13 Unused region */ -/* 14 Unused region */ -/* 15 Unused region */ +/* 12 User-defined region */ +/* 13 User-defined region */ +/* 14 User-defined region */ +/* 15 User-defined region */ /* */ /* */ /* INPUT */ @@ -294,6 +331,8 @@ UINT srd_bit_index; /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enable user defined regions, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -456,18 +495,18 @@ UINT i; /* Increment MPU table index. */ mpu_table_index++; } - - /* Setup MPU for the remaining regions. */ - while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) - { - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - - /* Increment MPU table index. */ - mpu_table_index++; - } -#else + /* Setup user-defined regions (12-15). */ + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_12; + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_12; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_13; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_13; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_14; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_14; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_15; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_15; + +#else /* TXM_MODULE_MANAGER_16_MPU is not defined, only 8 MPU regions. */ ULONG code_address; ULONG code_size; diff --git a/ports_module/cortex_m4/ac6/inc/txm_module_port.h b/ports_module/cortex_m4/ac6/inc/txm_module_port.h index 5542fe835..27488cda7 100644 --- a/ports_module/cortex_m4/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m4/ac6/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M4/AC6 */ -/* 6.1.10 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -44,6 +44,9 @@ /* 01-31-2022 Scott Larson Modified comments and made */ /* heap user-configurable, */ /* resulting in version 6.1.10 */ +/* 07-29-2022 Scott Larson Enabled user-defined and */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -119,6 +122,60 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 #endif +/* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) + are not used by ThreadX. These may be defined by the user. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 + + +/* Users can define these default MPU configuration values. + + If TXM_MODULE_MPU_DEFAULT is *not* defined, the MPU is disabled + when a thread that is not owned by a module is running + and the defines below are not used. + + If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the + below values when a thread that is not owned by a module is running. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_15 0 + + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -384,6 +441,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/AC6 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/AC6 Version 6.1.12 *"; #endif diff --git a/ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c index 5359f19bc..82b333843 100644 --- a/ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -57,7 +57,7 @@ extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top); /* FUNCTION RELEASE */ /* */ /* _txm_module_thread_shell_entry Cortex-M4/AC6 */ -/* 6.1.10 */ +/* 6.1.10 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S index d56fa3989..cb50426c9 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S @@ -42,7 +42,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M4/AC6 */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -78,6 +78,10 @@ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, optional */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -398,26 +402,33 @@ __tx_ts_restore: LDR r0, =0xE000ED94 // Build MPU control reg address MOV r3, #0 // Build disable value + CPSID i // Disable interrupts STR r3, [r0] // Disable MPU LDR r0, [r1, #0x90] // Pickup the module instance pointer +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r0, default_mpu // Is this thread owned by a module? No, default MPU setup +#else CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup - +#endif + LDR r2, [r0, #0x8C] // Pickup MPU region 5 address +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r2, default_mpu // Is protection required for this module? No, default MPU setup +#else CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup - - // Is the MPU already set up for this module? - MOV r1, #5 // Select region 5 from MPU - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 5 +#endif LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 5 - BIC r2, r2, #0x10 // Clear VALID bit - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block +#ifdef TXM_MODULE_MPU_DEFAULT + B config_mpu // configure MPU for module +default_mpu: + LDR r0, =txm_module_default_mpu_registers // default MPU configuration +#endif + +config_mpu: LDM r0!,{r2-r9} // Load MPU regions 0-3 STM r1,{r2-r9} // Store MPU regions 0-3 LDM r0!,{r2-r9} // Load MPU regions 4-7 @@ -425,14 +436,17 @@ __tx_ts_restore: #ifdef TXM_MODULE_MANAGER_16_MPU LDM r0!,{r2-r9} // Load MPU regions 8-11 STM r1,{r2-r9} // Store MPU regions 8-11 + // Regions 12-15 are reserved for the user to define. LDM r0,{r2-r9} // Load MPU regions 12-15 STM r1,{r2-r9} // Store MPU regions 12-15 #endif + _tx_enable_mpu: LDR r0, =0xE000ED94 // Build MPU control reg address MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU skip_mpu_setup: + CPSIE i // Enable interrupts LDMIA r12!, {LR} // Pickup LR #ifdef __ARM_FP TST LR, #0x10 // Determine if the VFP extended frame is present diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index dcc8d2aa0..36127034f 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -25,6 +25,43 @@ #include "tx_api.h" #include "txm_module.h" +#ifdef TXM_MODULE_MPU_DEFAULT +const ULONG txm_module_default_mpu_registers[32] = + { + TXM_MODULE_MPU_DEFAULT_RBAR_0, + TXM_MODULE_MPU_DEFAULT_RASR_0, + TXM_MODULE_MPU_DEFAULT_RBAR_1, + TXM_MODULE_MPU_DEFAULT_RASR_1, + TXM_MODULE_MPU_DEFAULT_RBAR_2, + TXM_MODULE_MPU_DEFAULT_RASR_2, + TXM_MODULE_MPU_DEFAULT_RBAR_3, + TXM_MODULE_MPU_DEFAULT_RASR_3, + TXM_MODULE_MPU_DEFAULT_RBAR_4, + TXM_MODULE_MPU_DEFAULT_RASR_4, + TXM_MODULE_MPU_DEFAULT_RBAR_5, + TXM_MODULE_MPU_DEFAULT_RASR_5, + TXM_MODULE_MPU_DEFAULT_RBAR_6, + TXM_MODULE_MPU_DEFAULT_RASR_6, + TXM_MODULE_MPU_DEFAULT_RBAR_7, + TXM_MODULE_MPU_DEFAULT_RASR_7, + TXM_MODULE_MPU_DEFAULT_RBAR_8, + TXM_MODULE_MPU_DEFAULT_RASR_8, + TXM_MODULE_MPU_DEFAULT_RBAR_9, + TXM_MODULE_MPU_DEFAULT_RASR_9, + TXM_MODULE_MPU_DEFAULT_RBAR_10, + TXM_MODULE_MPU_DEFAULT_RASR_10, + TXM_MODULE_MPU_DEFAULT_RBAR_11, + TXM_MODULE_MPU_DEFAULT_RASR_11, + TXM_MODULE_MPU_DEFAULT_RBAR_12, + TXM_MODULE_MPU_DEFAULT_RASR_12, + TXM_MODULE_MPU_DEFAULT_RBAR_13, + TXM_MODULE_MPU_DEFAULT_RASR_13, + TXM_MODULE_MPU_DEFAULT_RBAR_14, + TXM_MODULE_MPU_DEFAULT_RASR_14, + TXM_MODULE_MPU_DEFAULT_RBAR_15, + TXM_MODULE_MPU_DEFAULT_RASR_15 + }; +#endif /**************************************************************************/ /* */ @@ -231,7 +268,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M4 */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -267,10 +304,10 @@ UINT srd_bit_index; /* 9 Module shared memory region */ /* 10 Module shared memory region */ /* 11 Module shared memory region */ -/* 12 Unused region */ -/* 13 Unused region */ -/* 14 Unused region */ -/* 15 Unused region */ +/* 12 User-defined region */ +/* 13 User-defined region */ +/* 14 User-defined region */ +/* 15 User-defined region */ /* */ /* */ /* INPUT */ @@ -294,6 +331,8 @@ UINT srd_bit_index; /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enable user defined regions, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -456,18 +495,18 @@ UINT i; /* Increment MPU table index. */ mpu_table_index++; } - - /* Setup MPU for the remaining regions. */ - while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) - { - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - - /* Increment MPU table index. */ - mpu_table_index++; - } -#else + /* Setup user-defined regions (12-15). */ + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_12; + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_12; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_13; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_13; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_14; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_14; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_15; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_15; + +#else /* TXM_MODULE_MANAGER_16_MPU is not defined, only 8 MPU regions. */ ULONG code_address; ULONG code_size; diff --git a/ports_module/cortex_m4/gnu/example_build/build_threadx_sample.bat b/ports_module/cortex_m4/gnu/example_build/build_threadx_sample.bat new file mode 100644 index 000000000..21b6671c9 --- /dev/null +++ b/ports_module/cortex_m4/gnu/example_build/build_threadx_sample.bat @@ -0,0 +1,5 @@ +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb cortexm_vectors.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb cortexm_crt0.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I..\inc -I..\..\..\..\common\inc sample_threadx.c +arm-none-eabi-gcc -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -T sample_threadx.ld -ereset_handler -nostartfiles -o sample_threadx.out -Wl,-Map=sample_threadx.map cortexm_vectors.o cortexm_crt0.o tx_initialize_low_level.o sample_threadx.o tx.a diff --git a/ports/cortex_m0/gnu/example_build/cortexm0_crt0.s b/ports_module/cortex_m4/gnu/example_build/cortexm_crt0.S similarity index 100% rename from ports/cortex_m0/gnu/example_build/cortexm0_crt0.s rename to ports_module/cortex_m4/gnu/example_build/cortexm_crt0.S diff --git a/ports_module/cortex_m4/gnu/example_build/cortexm_vectors.S b/ports_module/cortex_m4/gnu/example_build/cortexm_vectors.S new file mode 100644 index 000000000..6ae558e4d --- /dev/null +++ b/ports_module/cortex_m4/gnu/example_build/cortexm_vectors.S @@ -0,0 +1,77 @@ + .global reset_handler + + .global __tx_NMIHandler + .global __tx_BadHandler + .global __tx_SVCallHandler + .global __tx_DBGHandler + .global __tx_PendSVHandler + .global __tx_SysTickHandler + .global __tx_BadHandler + + .syntax unified + .section .vectors, "ax" + .code 16 + .align 0 + .global _vectors + +_vectors: + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler + .word __tx_HardfaultHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // + .word __tx_DBGHandler + .word 0 // Reserved + .word __tx_PendSVHandler + .word __tx_SysTickHandler // Used by Threadx timer functionality + .word __tx_BadHandler // Populate with user Interrupt handler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + + .section .init, "ax" + .thumb_func +reset_handler: + // low level hardware config, such as PLL setup goes here + b _start + + + diff --git a/ports_module/cortex_m4/gnu/inc/txm_module_port.h b/ports_module/cortex_m4/gnu/inc/txm_module_port.h index f48c9620b..3cb14d4fa 100644 --- a/ports_module/cortex_m4/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m4/gnu/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M4/GNU */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,6 +41,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enabled user-defined and */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -111,6 +114,60 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 #endif +/* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) + are not used by ThreadX. These may be defined by the user. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 + + +/* Users can define these default MPU configuration values. + + If TXM_MODULE_MPU_DEFAULT is *not* defined, the MPU is disabled + when a thread that is not owned by a module is running + and the defines below are not used. + + If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the + below values when a thread that is not owned by a module is running. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_15 0 + + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -376,6 +433,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/GNU Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/GNU Version 6.1.12 *"; #endif diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S index 948b153c3..4d5e99470 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S @@ -40,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M4/GNU */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -78,6 +78,10 @@ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, optional */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -398,26 +402,33 @@ __tx_ts_restore: LDR r0, =0xE000ED94 // Build MPU control reg address MOV r3, #0 // Build disable value + CPSID i // Disable interrupts STR r3, [r0] // Disable MPU LDR r0, [r1, #0x90] // Pickup the module instance pointer +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r0, default_mpu // Is this thread owned by a module? No, default MPU setup +#else CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup - +#endif + LDR r2, [r0, #0x8C] // Pickup MPU region 5 address +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r2, default_mpu // Is protection required for this module? No, default MPU setup +#else CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup - - // Is the MPU already set up for this module? - MOV r1, #5 // Select region 5 from MPU - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 5 +#endif LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 5 - BIC r2, r2, #0x10 // Clear VALID bit - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block +#ifdef TXM_MODULE_MPU_DEFAULT + B config_mpu // configure MPU for module +default_mpu: + LDR r0, =txm_module_default_mpu_registers // default MPU configuration +#endif + +config_mpu: LDM r0!,{r2-r9} // Load MPU regions 0-3 STM r1,{r2-r9} // Store MPU regions 0-3 LDM r0!,{r2-r9} // Load MPU regions 4-7 @@ -425,14 +436,17 @@ __tx_ts_restore: #ifdef TXM_MODULE_MANAGER_16_MPU LDM r0!,{r2-r9} // Load MPU regions 8-11 STM r1,{r2-r9} // Store MPU regions 8-11 + // Regions 12-15 are reserved for the user to define. LDM r0,{r2-r9} // Load MPU regions 12-15 STM r1,{r2-r9} // Store MPU regions 12-15 #endif + _tx_enable_mpu: LDR r0, =0xE000ED94 // Build MPU control reg address MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU skip_mpu_setup: + CPSIE i // Enable interrupts LDMIA r12!, {LR} // Pickup LR #ifdef __ARM_FP TST LR, #0x10 // Determine if the VFP extended frame is present @@ -588,14 +602,14 @@ _tx_no_lazy_clear: #endif /* Copy kernel hardware stack to module thread stack. */ - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} + LDM r3!, {r1-r2} // Get r0, r1 from kernel stack + STM r0!, {r1-r2} // Insert r0, r1 into thread stack + LDM r3!, {r1-r2} // Get r2, r3 from kernel stack + STM r0!, {r1-r2} // Insert r2, r3 into thread stack + LDM r3!, {r1-r2} // Get r12, lr from kernel stack + STM r0!, {r1-r2} // Insert r12, lr into thread stack + LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack + STM r0!, {r1-r2} // Insert pc, xpsr into thread stack SUB r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index dcc8d2aa0..36127034f 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -25,6 +25,43 @@ #include "tx_api.h" #include "txm_module.h" +#ifdef TXM_MODULE_MPU_DEFAULT +const ULONG txm_module_default_mpu_registers[32] = + { + TXM_MODULE_MPU_DEFAULT_RBAR_0, + TXM_MODULE_MPU_DEFAULT_RASR_0, + TXM_MODULE_MPU_DEFAULT_RBAR_1, + TXM_MODULE_MPU_DEFAULT_RASR_1, + TXM_MODULE_MPU_DEFAULT_RBAR_2, + TXM_MODULE_MPU_DEFAULT_RASR_2, + TXM_MODULE_MPU_DEFAULT_RBAR_3, + TXM_MODULE_MPU_DEFAULT_RASR_3, + TXM_MODULE_MPU_DEFAULT_RBAR_4, + TXM_MODULE_MPU_DEFAULT_RASR_4, + TXM_MODULE_MPU_DEFAULT_RBAR_5, + TXM_MODULE_MPU_DEFAULT_RASR_5, + TXM_MODULE_MPU_DEFAULT_RBAR_6, + TXM_MODULE_MPU_DEFAULT_RASR_6, + TXM_MODULE_MPU_DEFAULT_RBAR_7, + TXM_MODULE_MPU_DEFAULT_RASR_7, + TXM_MODULE_MPU_DEFAULT_RBAR_8, + TXM_MODULE_MPU_DEFAULT_RASR_8, + TXM_MODULE_MPU_DEFAULT_RBAR_9, + TXM_MODULE_MPU_DEFAULT_RASR_9, + TXM_MODULE_MPU_DEFAULT_RBAR_10, + TXM_MODULE_MPU_DEFAULT_RASR_10, + TXM_MODULE_MPU_DEFAULT_RBAR_11, + TXM_MODULE_MPU_DEFAULT_RASR_11, + TXM_MODULE_MPU_DEFAULT_RBAR_12, + TXM_MODULE_MPU_DEFAULT_RASR_12, + TXM_MODULE_MPU_DEFAULT_RBAR_13, + TXM_MODULE_MPU_DEFAULT_RASR_13, + TXM_MODULE_MPU_DEFAULT_RBAR_14, + TXM_MODULE_MPU_DEFAULT_RASR_14, + TXM_MODULE_MPU_DEFAULT_RBAR_15, + TXM_MODULE_MPU_DEFAULT_RASR_15 + }; +#endif /**************************************************************************/ /* */ @@ -231,7 +268,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M4 */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -267,10 +304,10 @@ UINT srd_bit_index; /* 9 Module shared memory region */ /* 10 Module shared memory region */ /* 11 Module shared memory region */ -/* 12 Unused region */ -/* 13 Unused region */ -/* 14 Unused region */ -/* 15 Unused region */ +/* 12 User-defined region */ +/* 13 User-defined region */ +/* 14 User-defined region */ +/* 15 User-defined region */ /* */ /* */ /* INPUT */ @@ -294,6 +331,8 @@ UINT srd_bit_index; /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enable user defined regions, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -456,18 +495,18 @@ UINT i; /* Increment MPU table index. */ mpu_table_index++; } - - /* Setup MPU for the remaining regions. */ - while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) - { - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - - /* Increment MPU table index. */ - mpu_table_index++; - } -#else + /* Setup user-defined regions (12-15). */ + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_12; + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_12; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_13; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_13; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_14; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_14; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_15; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_15; + +#else /* TXM_MODULE_MANAGER_16_MPU is not defined, only 8 MPU regions. */ ULONG code_address; ULONG code_size; diff --git a/ports_module/cortex_m4/iar/inc/txm_module_port.h b/ports_module/cortex_m4/iar/inc/txm_module_port.h index d02fb1ad3..e92cfc0fe 100644 --- a/ports_module/cortex_m4/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m4/iar/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M4/IAR */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,6 +41,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enabled user-defined and */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -112,6 +115,60 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 #endif +/* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) + are not used by ThreadX. These may be defined by the user. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 + + +/* Users can define these default MPU configuration values. + + If TXM_MODULE_MPU_DEFAULT is *not* defined, the MPU is disabled + when a thread that is not owned by a module is running + and the defines below are not used. + + If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the + below values when a thread that is not owned by a module is running. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_15 0 + + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -377,6 +434,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/IAR Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/IAR Version 6.1.12 *"; #endif diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s index 928409616..8291f3341 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s @@ -28,6 +28,7 @@ EXTERN _tx_thread_preempt_disable EXTERN _txm_module_manager_memory_fault_handler EXTERN _txm_module_manager_memory_fault_info + EXTERN txm_module_default_mpu_registers SECTION `.text`:CODE:NOROOT(2) THUMB @@ -36,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M4/IAR */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -72,6 +73,10 @@ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, optional */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -385,26 +390,33 @@ __tx_ts_restore: LDR r0, =0xE000ED94 // Build MPU control reg address MOV r3, #0 // Build disable value + CPSID i // Disable interrupts STR r3, [r0] // Disable MPU LDR r0, [r1, #0x90] // Pickup the module instance pointer +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r0, default_mpu // Is this thread owned by a module? No, default MPU setup +#else CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup - +#endif + LDR r2, [r0, #0x8C] // Pickup MPU region 5 address +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r2, default_mpu // Is protection required for this module? No, default MPU setup +#else CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup - - // Is the MPU already set up for this module? - MOV r1, #5 // Select region 5 from MPU - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 5 +#endif LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 5 - BIC r2, r2, #0x10 // Clear VALID bit - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block +#ifdef TXM_MODULE_MPU_DEFAULT + B config_mpu // configure MPU for module +default_mpu: + LDR r0, =txm_module_default_mpu_registers // default MPU configuration +#endif + +config_mpu: LDM r0!,{r2-r9} // Load MPU regions 0-3 STM r1,{r2-r9} // Store MPU regions 0-3 LDM r0!,{r2-r9} // Load MPU regions 4-7 @@ -412,14 +424,17 @@ __tx_ts_restore: #ifdef TXM_MODULE_MANAGER_16_MPU LDM r0!,{r2-r9} // Load MPU regions 8-11 STM r1,{r2-r9} // Store MPU regions 8-11 + // Regions 12-15 are reserved for the user to define. LDM r0,{r2-r9} // Load MPU regions 12-15 STM r1,{r2-r9} // Store MPU regions 12-15 #endif + _tx_enable_mpu: LDR r0, =0xE000ED94 // Build MPU control reg address MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU skip_mpu_setup: + CPSIE i // Enable interrupts LDMIA r12!, {LR} // Pickup LR #ifdef __ARMVFP__ TST LR, #0x10 // Determine if the VFP extended frame is present @@ -574,14 +589,14 @@ _tx_no_lazy_clear: #endif /* Copy kernel hardware stack to module thread stack. */ - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} + LDM r3!, {r1-r2} // Get r0, r1 from kernel stack + STM r0!, {r1-r2} // Insert r0, r1 into thread stack + LDM r3!, {r1-r2} // Get r2, r3 from kernel stack + STM r0!, {r1-r2} // Insert r2, r3 into thread stack + LDM r3!, {r1-r2} // Get r12, lr from kernel stack + STM r0!, {r1-r2} // Insert r12, lr into thread stack + LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack + STM r0!, {r1-r2} // Insert pc, xpsr into thread stack SUB r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c index dcc8d2aa0..36127034f 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -25,6 +25,43 @@ #include "tx_api.h" #include "txm_module.h" +#ifdef TXM_MODULE_MPU_DEFAULT +const ULONG txm_module_default_mpu_registers[32] = + { + TXM_MODULE_MPU_DEFAULT_RBAR_0, + TXM_MODULE_MPU_DEFAULT_RASR_0, + TXM_MODULE_MPU_DEFAULT_RBAR_1, + TXM_MODULE_MPU_DEFAULT_RASR_1, + TXM_MODULE_MPU_DEFAULT_RBAR_2, + TXM_MODULE_MPU_DEFAULT_RASR_2, + TXM_MODULE_MPU_DEFAULT_RBAR_3, + TXM_MODULE_MPU_DEFAULT_RASR_3, + TXM_MODULE_MPU_DEFAULT_RBAR_4, + TXM_MODULE_MPU_DEFAULT_RASR_4, + TXM_MODULE_MPU_DEFAULT_RBAR_5, + TXM_MODULE_MPU_DEFAULT_RASR_5, + TXM_MODULE_MPU_DEFAULT_RBAR_6, + TXM_MODULE_MPU_DEFAULT_RASR_6, + TXM_MODULE_MPU_DEFAULT_RBAR_7, + TXM_MODULE_MPU_DEFAULT_RASR_7, + TXM_MODULE_MPU_DEFAULT_RBAR_8, + TXM_MODULE_MPU_DEFAULT_RASR_8, + TXM_MODULE_MPU_DEFAULT_RBAR_9, + TXM_MODULE_MPU_DEFAULT_RASR_9, + TXM_MODULE_MPU_DEFAULT_RBAR_10, + TXM_MODULE_MPU_DEFAULT_RASR_10, + TXM_MODULE_MPU_DEFAULT_RBAR_11, + TXM_MODULE_MPU_DEFAULT_RASR_11, + TXM_MODULE_MPU_DEFAULT_RBAR_12, + TXM_MODULE_MPU_DEFAULT_RASR_12, + TXM_MODULE_MPU_DEFAULT_RBAR_13, + TXM_MODULE_MPU_DEFAULT_RASR_13, + TXM_MODULE_MPU_DEFAULT_RBAR_14, + TXM_MODULE_MPU_DEFAULT_RASR_14, + TXM_MODULE_MPU_DEFAULT_RBAR_15, + TXM_MODULE_MPU_DEFAULT_RASR_15 + }; +#endif /**************************************************************************/ /* */ @@ -231,7 +268,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M4 */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -267,10 +304,10 @@ UINT srd_bit_index; /* 9 Module shared memory region */ /* 10 Module shared memory region */ /* 11 Module shared memory region */ -/* 12 Unused region */ -/* 13 Unused region */ -/* 14 Unused region */ -/* 15 Unused region */ +/* 12 User-defined region */ +/* 13 User-defined region */ +/* 14 User-defined region */ +/* 15 User-defined region */ /* */ /* */ /* INPUT */ @@ -294,6 +331,8 @@ UINT srd_bit_index; /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enable user defined regions, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -456,18 +495,18 @@ UINT i; /* Increment MPU table index. */ mpu_table_index++; } - - /* Setup MPU for the remaining regions. */ - while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) - { - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - - /* Increment MPU table index. */ - mpu_table_index++; - } -#else + /* Setup user-defined regions (12-15). */ + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_12; + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_12; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_13; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_13; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_14; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_14; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_15; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_15; + +#else /* TXM_MODULE_MANAGER_16_MPU is not defined, only 8 MPU regions. */ ULONG code_address; ULONG code_size; diff --git a/ports_module/cortex_m7/ac5/inc/txm_module_port.h b/ports_module/cortex_m7/ac5/inc/txm_module_port.h index e7a4e8268..3ac5acf76 100644 --- a/ports_module/cortex_m7/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_m7/ac5/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M7/AC5 */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,6 +41,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enabled user-defined and */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -111,6 +114,60 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 #endif +/* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) + are not used by ThreadX. These may be defined by the user. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 + + +/* Users can define these default MPU configuration values. + + If TXM_MODULE_MPU_DEFAULT is *not* defined, the MPU is disabled + when a thread that is not owned by a module is running + and the defines below are not used. + + If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the + below values when a thread that is not owned by a module is running. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_15 0 + + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.s index 150f9818f..21b92ae79 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.s @@ -40,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M7/AC5 */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,6 +76,10 @@ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, optional */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -385,26 +389,33 @@ __tx_ts_restore LDR r0, =0xE000ED94 // Build MPU control reg address MOV r3, #0 // Build disable value + CPSID i // Disable interrupts STR r3, [r0] // Disable MPU LDR r0, [r1, #0x90] // Pickup the module instance pointer +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r0, default_mpu // Is this thread owned by a module? No, default MPU setup +#else CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup - +#endif + LDR r2, [r0, #0x8C] // Pickup MPU region 5 address +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r2, default_mpu // Is protection required for this module? No, default MPU setup +#else CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup - - // Is the MPU already set up for this module? - MOV r1, #5 // Select region 5 from MPU - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 5 +#endif LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 5 - BIC r2, r2, #0x10 // Clear VALID bit - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block +#ifdef TXM_MODULE_MPU_DEFAULT + B config_mpu // configure MPU for module +default_mpu: + LDR r0, =txm_module_default_mpu_registers // default MPU configuration +#endif + +config_mpu: LDM r0!,{r2-r9} // Load MPU regions 0-3 STM r1,{r2-r9} // Store MPU regions 0-3 LDM r0!,{r2-r9} // Load MPU regions 4-7 @@ -412,6 +423,7 @@ __tx_ts_restore #ifdef TXM_MODULE_MANAGER_16_MPU LDM r0!,{r2-r9} // Load MPU regions 8-11 STM r1,{r2-r9} // Store MPU regions 8-11 + // Regions 12-15 are reserved for the user to define. LDM r0,{r2-r9} // Load MPU regions 12-15 STM r1,{r2-r9} // Store MPU regions 12-15 #endif @@ -420,6 +432,7 @@ _tx_enable_mpu MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU skip_mpu_setup + CPSIE i // Enable interrupts LDMIA r12!, {LR} // Pickup LR #ifdef __TARGET_FPU_VFP TST LR, #0x10 // Determine if the VFP extended frame is present @@ -573,14 +586,14 @@ _tx_no_lazy_clear: #endif /* Copy kernel hardware stack to module thread stack. */ - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} + LDM r3!, {r1-r2} // Get r0, r1 from kernel stack + STM r0!, {r1-r2} // Insert r0, r1 into thread stack + LDM r3!, {r1-r2} // Get r2, r3 from kernel stack + STM r0!, {r1-r2} // Insert r2, r3 into thread stack + LDM r3!, {r1-r2} // Get r12, lr from kernel stack + STM r0!, {r1-r2} // Insert r12, lr into thread stack + LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack + STM r0!, {r1-r2} // Insert pc, xpsr into thread stack SUB r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index bfffa5bc1..55369436b 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -25,6 +25,43 @@ #include "tx_api.h" #include "txm_module.h" +#ifdef TXM_MODULE_MPU_DEFAULT +const ULONG txm_module_default_mpu_registers[32] = + { + TXM_MODULE_MPU_DEFAULT_RBAR_0, + TXM_MODULE_MPU_DEFAULT_RASR_0, + TXM_MODULE_MPU_DEFAULT_RBAR_1, + TXM_MODULE_MPU_DEFAULT_RASR_1, + TXM_MODULE_MPU_DEFAULT_RBAR_2, + TXM_MODULE_MPU_DEFAULT_RASR_2, + TXM_MODULE_MPU_DEFAULT_RBAR_3, + TXM_MODULE_MPU_DEFAULT_RASR_3, + TXM_MODULE_MPU_DEFAULT_RBAR_4, + TXM_MODULE_MPU_DEFAULT_RASR_4, + TXM_MODULE_MPU_DEFAULT_RBAR_5, + TXM_MODULE_MPU_DEFAULT_RASR_5, + TXM_MODULE_MPU_DEFAULT_RBAR_6, + TXM_MODULE_MPU_DEFAULT_RASR_6, + TXM_MODULE_MPU_DEFAULT_RBAR_7, + TXM_MODULE_MPU_DEFAULT_RASR_7, + TXM_MODULE_MPU_DEFAULT_RBAR_8, + TXM_MODULE_MPU_DEFAULT_RASR_8, + TXM_MODULE_MPU_DEFAULT_RBAR_9, + TXM_MODULE_MPU_DEFAULT_RASR_9, + TXM_MODULE_MPU_DEFAULT_RBAR_10, + TXM_MODULE_MPU_DEFAULT_RASR_10, + TXM_MODULE_MPU_DEFAULT_RBAR_11, + TXM_MODULE_MPU_DEFAULT_RASR_11, + TXM_MODULE_MPU_DEFAULT_RBAR_12, + TXM_MODULE_MPU_DEFAULT_RASR_12, + TXM_MODULE_MPU_DEFAULT_RBAR_13, + TXM_MODULE_MPU_DEFAULT_RASR_13, + TXM_MODULE_MPU_DEFAULT_RBAR_14, + TXM_MODULE_MPU_DEFAULT_RASR_14, + TXM_MODULE_MPU_DEFAULT_RBAR_15, + TXM_MODULE_MPU_DEFAULT_RASR_15 + }; +#endif /**************************************************************************/ /* */ @@ -231,7 +268,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M7 */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -267,10 +304,10 @@ UINT srd_bit_index; /* 9 Module shared memory region */ /* 10 Module shared memory region */ /* 11 Module shared memory region */ -/* 12 Unused region */ -/* 13 Unused region */ -/* 14 Unused region */ -/* 15 Unused region */ +/* 12 User-defined region */ +/* 13 User-defined region */ +/* 14 User-defined region */ +/* 15 User-defined region */ /* */ /* */ /* INPUT */ @@ -294,6 +331,8 @@ UINT srd_bit_index; /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enable user defined regions, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -456,18 +495,18 @@ UINT i; /* Increment MPU table index. */ mpu_table_index++; } - - /* Setup MPU for the remaining regions. */ - while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) - { - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - - /* Increment MPU table index. */ - mpu_table_index++; - } -#else + /* Setup user-defined regions (12-15). */ + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_12; + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_12; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_13; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_13; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_14; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_14; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_15; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_15; + +#else /* TXM_MODULE_MANAGER_16_MPU is not defined, only 8 MPU regions. */ ULONG code_address; ULONG code_size; diff --git a/ports_module/cortex_m7/ac6/inc/txm_module_port.h b/ports_module/cortex_m7/ac6/inc/txm_module_port.h index 1fd6ce263..e1cce9ca4 100644 --- a/ports_module/cortex_m7/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m7/ac6/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M7/AC6 */ -/* 6.1.10 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -44,6 +44,9 @@ /* 01-31-2022 Scott Larson Modified comments and made */ /* heap user-configurable, */ /* resulting in version 6.1.10 */ +/* 07-29-2022 Scott Larson Enabled user-defined and */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -119,6 +122,60 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 #endif +/* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) + are not used by ThreadX. These may be defined by the user. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 + + +/* Users can define these default MPU configuration values. + + If TXM_MODULE_MPU_DEFAULT is *not* defined, the MPU is disabled + when a thread that is not owned by a module is running + and the defines below are not used. + + If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the + below values when a thread that is not owned by a module is running. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_15 0 + + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -384,6 +441,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/AC6 Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/AC6 Version 6.1.12 *"; #endif diff --git a/ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c index cf2cc1666..a5c1cc72a 100644 --- a/ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -57,7 +57,7 @@ extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top); /* FUNCTION RELEASE */ /* */ /* _txm_module_thread_shell_entry Cortex-M7/AC6 */ -/* 6.1.10 */ +/* 6.1.10 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S index c6b66e540..7111ccf18 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S @@ -42,7 +42,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M7/AC6 */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -78,6 +78,10 @@ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, optional */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -398,26 +402,33 @@ __tx_ts_restore: LDR r0, =0xE000ED94 // Build MPU control reg address MOV r3, #0 // Build disable value + CPSID i // Disable interrupts STR r3, [r0] // Disable MPU LDR r0, [r1, #0x90] // Pickup the module instance pointer +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r0, default_mpu // Is this thread owned by a module? No, default MPU setup +#else CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup - +#endif + LDR r2, [r0, #0x8C] // Pickup MPU region 5 address +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r2, default_mpu // Is protection required for this module? No, default MPU setup +#else CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup - - // Is the MPU already set up for this module? - MOV r1, #5 // Select region 5 from MPU - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 5 +#endif LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 5 - BIC r2, r2, #0x10 // Clear VALID bit - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block +#ifdef TXM_MODULE_MPU_DEFAULT + B config_mpu // configure MPU for module +default_mpu: + LDR r0, =txm_module_default_mpu_registers // default MPU configuration +#endif + +config_mpu: LDM r0!,{r2-r9} // Load MPU regions 0-3 STM r1,{r2-r9} // Store MPU regions 0-3 LDM r0!,{r2-r9} // Load MPU regions 4-7 @@ -425,14 +436,17 @@ __tx_ts_restore: #ifdef TXM_MODULE_MANAGER_16_MPU LDM r0!,{r2-r9} // Load MPU regions 8-11 STM r1,{r2-r9} // Store MPU regions 8-11 + // Regions 12-15 are reserved for the user to define. LDM r0,{r2-r9} // Load MPU regions 12-15 STM r1,{r2-r9} // Store MPU regions 12-15 #endif + _tx_enable_mpu: LDR r0, =0xE000ED94 // Build MPU control reg address MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU skip_mpu_setup: + CPSIE i // Enable interrupts LDMIA r12!, {LR} // Pickup LR #ifdef __ARM_FP TST LR, #0x10 // Determine if the VFP extended frame is present diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index bfffa5bc1..55369436b 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -25,6 +25,43 @@ #include "tx_api.h" #include "txm_module.h" +#ifdef TXM_MODULE_MPU_DEFAULT +const ULONG txm_module_default_mpu_registers[32] = + { + TXM_MODULE_MPU_DEFAULT_RBAR_0, + TXM_MODULE_MPU_DEFAULT_RASR_0, + TXM_MODULE_MPU_DEFAULT_RBAR_1, + TXM_MODULE_MPU_DEFAULT_RASR_1, + TXM_MODULE_MPU_DEFAULT_RBAR_2, + TXM_MODULE_MPU_DEFAULT_RASR_2, + TXM_MODULE_MPU_DEFAULT_RBAR_3, + TXM_MODULE_MPU_DEFAULT_RASR_3, + TXM_MODULE_MPU_DEFAULT_RBAR_4, + TXM_MODULE_MPU_DEFAULT_RASR_4, + TXM_MODULE_MPU_DEFAULT_RBAR_5, + TXM_MODULE_MPU_DEFAULT_RASR_5, + TXM_MODULE_MPU_DEFAULT_RBAR_6, + TXM_MODULE_MPU_DEFAULT_RASR_6, + TXM_MODULE_MPU_DEFAULT_RBAR_7, + TXM_MODULE_MPU_DEFAULT_RASR_7, + TXM_MODULE_MPU_DEFAULT_RBAR_8, + TXM_MODULE_MPU_DEFAULT_RASR_8, + TXM_MODULE_MPU_DEFAULT_RBAR_9, + TXM_MODULE_MPU_DEFAULT_RASR_9, + TXM_MODULE_MPU_DEFAULT_RBAR_10, + TXM_MODULE_MPU_DEFAULT_RASR_10, + TXM_MODULE_MPU_DEFAULT_RBAR_11, + TXM_MODULE_MPU_DEFAULT_RASR_11, + TXM_MODULE_MPU_DEFAULT_RBAR_12, + TXM_MODULE_MPU_DEFAULT_RASR_12, + TXM_MODULE_MPU_DEFAULT_RBAR_13, + TXM_MODULE_MPU_DEFAULT_RASR_13, + TXM_MODULE_MPU_DEFAULT_RBAR_14, + TXM_MODULE_MPU_DEFAULT_RASR_14, + TXM_MODULE_MPU_DEFAULT_RBAR_15, + TXM_MODULE_MPU_DEFAULT_RASR_15 + }; +#endif /**************************************************************************/ /* */ @@ -231,7 +268,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M7 */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -267,10 +304,10 @@ UINT srd_bit_index; /* 9 Module shared memory region */ /* 10 Module shared memory region */ /* 11 Module shared memory region */ -/* 12 Unused region */ -/* 13 Unused region */ -/* 14 Unused region */ -/* 15 Unused region */ +/* 12 User-defined region */ +/* 13 User-defined region */ +/* 14 User-defined region */ +/* 15 User-defined region */ /* */ /* */ /* INPUT */ @@ -294,6 +331,8 @@ UINT srd_bit_index; /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enable user defined regions, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -456,18 +495,18 @@ UINT i; /* Increment MPU table index. */ mpu_table_index++; } - - /* Setup MPU for the remaining regions. */ - while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) - { - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - - /* Increment MPU table index. */ - mpu_table_index++; - } -#else + /* Setup user-defined regions (12-15). */ + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_12; + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_12; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_13; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_13; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_14; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_14; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_15; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_15; + +#else /* TXM_MODULE_MANAGER_16_MPU is not defined, only 8 MPU regions. */ ULONG code_address; ULONG code_size; diff --git a/ports_module/cortex_m7/gnu/inc/txm_module_port.h b/ports_module/cortex_m7/gnu/inc/txm_module_port.h index 8731adfe3..ba3b3ec0c 100644 --- a/ports_module/cortex_m7/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m7/gnu/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M7/GNU */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,6 +41,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enabled user-defined and */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -111,6 +114,60 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 #endif +/* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) + are not used by ThreadX. These may be defined by the user. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 + + +/* Users can define these default MPU configuration values. + + If TXM_MODULE_MPU_DEFAULT is *not* defined, the MPU is disabled + when a thread that is not owned by a module is running + and the defines below are not used. + + If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the + below values when a thread that is not owned by a module is running. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_15 0 + + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -376,6 +433,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/GNU Version 6.1.9 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/GNU Version 6.1.12 *"; #endif diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S index e34017824..69cb74bb5 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S @@ -40,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M7/GNU */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -78,6 +78,10 @@ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, optional */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -398,26 +402,33 @@ __tx_ts_restore: LDR r0, =0xE000ED94 // Build MPU control reg address MOV r3, #0 // Build disable value + CPSID i // Disable interrupts STR r3, [r0] // Disable MPU LDR r0, [r1, #0x90] // Pickup the module instance pointer +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r0, default_mpu // Is this thread owned by a module? No, default MPU setup +#else CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup - +#endif + LDR r2, [r0, #0x8C] // Pickup MPU region 5 address +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r2, default_mpu // Is protection required for this module? No, default MPU setup +#else CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup - - // Is the MPU already set up for this module? - MOV r1, #5 // Select region 5 from MPU - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 5 +#endif LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 5 - BIC r2, r2, #0x10 // Clear VALID bit - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block +#ifdef TXM_MODULE_MPU_DEFAULT + B config_mpu // configure MPU for module +default_mpu: + LDR r0, =txm_module_default_mpu_registers // default MPU configuration +#endif + +config_mpu: LDM r0!,{r2-r9} // Load MPU regions 0-3 STM r1,{r2-r9} // Store MPU regions 0-3 LDM r0!,{r2-r9} // Load MPU regions 4-7 @@ -425,14 +436,17 @@ __tx_ts_restore: #ifdef TXM_MODULE_MANAGER_16_MPU LDM r0!,{r2-r9} // Load MPU regions 8-11 STM r1,{r2-r9} // Store MPU regions 8-11 + // Regions 12-15 are reserved for the user to define. LDM r0,{r2-r9} // Load MPU regions 12-15 STM r1,{r2-r9} // Store MPU regions 12-15 #endif + _tx_enable_mpu: LDR r0, =0xE000ED94 // Build MPU control reg address MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU skip_mpu_setup: + CPSIE i // Enable interrupts LDMIA r12!, {LR} // Pickup LR #ifdef __ARM_FP TST LR, #0x10 // Determine if the VFP extended frame is present @@ -588,14 +602,14 @@ _tx_no_lazy_clear: #endif /* Copy kernel hardware stack to module thread stack. */ - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} + LDM r3!, {r1-r2} // Get r0, r1 from kernel stack + STM r0!, {r1-r2} // Insert r0, r1 into thread stack + LDM r3!, {r1-r2} // Get r2, r3 from kernel stack + STM r0!, {r1-r2} // Insert r2, r3 into thread stack + LDM r3!, {r1-r2} // Get r12, lr from kernel stack + STM r0!, {r1-r2} // Insert r12, lr into thread stack + LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack + STM r0!, {r1-r2} // Insert pc, xpsr into thread stack SUB r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index bfffa5bc1..55369436b 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -25,6 +25,43 @@ #include "tx_api.h" #include "txm_module.h" +#ifdef TXM_MODULE_MPU_DEFAULT +const ULONG txm_module_default_mpu_registers[32] = + { + TXM_MODULE_MPU_DEFAULT_RBAR_0, + TXM_MODULE_MPU_DEFAULT_RASR_0, + TXM_MODULE_MPU_DEFAULT_RBAR_1, + TXM_MODULE_MPU_DEFAULT_RASR_1, + TXM_MODULE_MPU_DEFAULT_RBAR_2, + TXM_MODULE_MPU_DEFAULT_RASR_2, + TXM_MODULE_MPU_DEFAULT_RBAR_3, + TXM_MODULE_MPU_DEFAULT_RASR_3, + TXM_MODULE_MPU_DEFAULT_RBAR_4, + TXM_MODULE_MPU_DEFAULT_RASR_4, + TXM_MODULE_MPU_DEFAULT_RBAR_5, + TXM_MODULE_MPU_DEFAULT_RASR_5, + TXM_MODULE_MPU_DEFAULT_RBAR_6, + TXM_MODULE_MPU_DEFAULT_RASR_6, + TXM_MODULE_MPU_DEFAULT_RBAR_7, + TXM_MODULE_MPU_DEFAULT_RASR_7, + TXM_MODULE_MPU_DEFAULT_RBAR_8, + TXM_MODULE_MPU_DEFAULT_RASR_8, + TXM_MODULE_MPU_DEFAULT_RBAR_9, + TXM_MODULE_MPU_DEFAULT_RASR_9, + TXM_MODULE_MPU_DEFAULT_RBAR_10, + TXM_MODULE_MPU_DEFAULT_RASR_10, + TXM_MODULE_MPU_DEFAULT_RBAR_11, + TXM_MODULE_MPU_DEFAULT_RASR_11, + TXM_MODULE_MPU_DEFAULT_RBAR_12, + TXM_MODULE_MPU_DEFAULT_RASR_12, + TXM_MODULE_MPU_DEFAULT_RBAR_13, + TXM_MODULE_MPU_DEFAULT_RASR_13, + TXM_MODULE_MPU_DEFAULT_RBAR_14, + TXM_MODULE_MPU_DEFAULT_RASR_14, + TXM_MODULE_MPU_DEFAULT_RBAR_15, + TXM_MODULE_MPU_DEFAULT_RASR_15 + }; +#endif /**************************************************************************/ /* */ @@ -231,7 +268,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M7 */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -267,10 +304,10 @@ UINT srd_bit_index; /* 9 Module shared memory region */ /* 10 Module shared memory region */ /* 11 Module shared memory region */ -/* 12 Unused region */ -/* 13 Unused region */ -/* 14 Unused region */ -/* 15 Unused region */ +/* 12 User-defined region */ +/* 13 User-defined region */ +/* 14 User-defined region */ +/* 15 User-defined region */ /* */ /* */ /* INPUT */ @@ -294,6 +331,8 @@ UINT srd_bit_index; /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enable user defined regions, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -456,18 +495,18 @@ UINT i; /* Increment MPU table index. */ mpu_table_index++; } - - /* Setup MPU for the remaining regions. */ - while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) - { - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - - /* Increment MPU table index. */ - mpu_table_index++; - } -#else + /* Setup user-defined regions (12-15). */ + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_12; + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_12; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_13; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_13; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_14; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_14; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_15; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_15; + +#else /* TXM_MODULE_MANAGER_16_MPU is not defined, only 8 MPU regions. */ ULONG code_address; ULONG code_size; diff --git a/ports_module/cortex_m7/iar/inc/txm_module_port.h b/ports_module/cortex_m7/iar/inc/txm_module_port.h index 153d6604b..32103d561 100644 --- a/ports_module/cortex_m7/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m7/iar/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M7/IAR */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,6 +41,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enabled user-defined and */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ @@ -112,6 +115,60 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 #endif +/* For Cortex-M devices with 16 MPU regions, the last four regions (12-15) + are not used by ThreadX. These may be defined by the user. */ +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_12 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_13 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_14 0 +#define TXM_MODULE_MPU_USER_DEFINED_RBAR_15 0 +#define TXM_MODULE_MPU_USER_DEFINED_RASR_15 0 + + +/* Users can define these default MPU configuration values. + + If TXM_MODULE_MPU_DEFAULT is *not* defined, the MPU is disabled + when a thread that is not owned by a module is running + and the defines below are not used. + + If TXM_MODULE_MPU_DEFAULT is defined, the MPU is configured to the + below values when a thread that is not owned by a module is running. */ +#define TXM_MODULE_MPU_DEFAULT_RBAR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_0 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_1 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_2 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_3 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_4 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_5 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_6 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_7 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_8 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_9 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_10 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_11 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_12 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_13 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_14 0 +#define TXM_MODULE_MPU_DEFAULT_RBAR_15 0 +#define TXM_MODULE_MPU_DEFAULT_RASR_15 0 + + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -377,6 +434,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/IAR Version 6.1.10 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/IAR Version 6.1.12 *"; #endif diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s index 2d66551f2..632b507c6 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s @@ -28,6 +28,7 @@ EXTERN _tx_thread_preempt_disable EXTERN _txm_module_manager_memory_fault_handler EXTERN _txm_module_manager_memory_fault_info + EXTERN txm_module_default_mpu_registers SECTION `.text`:CODE:NOROOT(2) THUMB @@ -36,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M7/IAR */ -/* 6.1.11 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -72,6 +73,10 @@ /* 04-25-2022 Scott Larson Optimized MPU configuration, */ /* added BASEPRI support, */ /* resulting in version 6.1.11 */ +/* 07-29-2022 Scott Larson Removed the code path to skip */ +/* MPU reloading, optional */ +/* default MPU settings, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -385,26 +390,33 @@ __tx_ts_restore: LDR r0, =0xE000ED94 // Build MPU control reg address MOV r3, #0 // Build disable value + CPSID i // Disable interrupts STR r3, [r0] // Disable MPU LDR r0, [r1, #0x90] // Pickup the module instance pointer +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r0, default_mpu // Is this thread owned by a module? No, default MPU setup +#else CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup - +#endif + LDR r2, [r0, #0x8C] // Pickup MPU region 5 address +#ifdef TXM_MODULE_MPU_DEFAULT + CBZ r2, default_mpu // Is protection required for this module? No, default MPU setup +#else CBZ r2, skip_mpu_setup // Is protection required for this module? No, skip MPU setup - - // Is the MPU already set up for this module? - MOV r1, #5 // Select region 5 from MPU - LDR r3, =0xE000ED98 // MPU_RNR register address - STR r1, [r3] // Set region to 5 +#endif LDR r1, =0xE000ED9C // MPU_RBAR register address - LDR r3, [r1] // Load address stored in MPU region 5 - BIC r2, r2, #0x10 // Clear VALID bit - CMP r2, r3 // Is module already loaded? - BEQ _tx_enable_mpu // Yes - skip MPU reconfiguration // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block +#ifdef TXM_MODULE_MPU_DEFAULT + B config_mpu // configure MPU for module +default_mpu: + LDR r0, =txm_module_default_mpu_registers // default MPU configuration +#endif + +config_mpu: LDM r0!,{r2-r9} // Load MPU regions 0-3 STM r1,{r2-r9} // Store MPU regions 0-3 LDM r0!,{r2-r9} // Load MPU regions 4-7 @@ -412,14 +424,17 @@ __tx_ts_restore: #ifdef TXM_MODULE_MANAGER_16_MPU LDM r0!,{r2-r9} // Load MPU regions 8-11 STM r1,{r2-r9} // Store MPU regions 8-11 + // Regions 12-15 are reserved for the user to define. LDM r0,{r2-r9} // Load MPU regions 12-15 STM r1,{r2-r9} // Store MPU regions 12-15 #endif + _tx_enable_mpu: LDR r0, =0xE000ED94 // Build MPU control reg address MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU skip_mpu_setup: + CPSIE i // Enable interrupts LDMIA r12!, {LR} // Pickup LR #ifdef __ARMVFP__ TST LR, #0x10 // Determine if the VFP extended frame is present @@ -574,14 +589,14 @@ _tx_no_lazy_clear: #endif /* Copy kernel hardware stack to module thread stack. */ - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} + LDM r3!, {r1-r2} // Get r0, r1 from kernel stack + STM r0!, {r1-r2} // Insert r0, r1 into thread stack + LDM r3!, {r1-r2} // Get r2, r3 from kernel stack + STM r0!, {r1-r2} // Insert r2, r3 into thread stack + LDM r3!, {r1-r2} // Get r12, lr from kernel stack + STM r0!, {r1-r2} // Insert r12, lr into thread stack + LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack + STM r0!, {r1-r2} // Insert pc, xpsr into thread stack SUB r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c index bfffa5bc1..55369436b 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -25,6 +25,43 @@ #include "tx_api.h" #include "txm_module.h" +#ifdef TXM_MODULE_MPU_DEFAULT +const ULONG txm_module_default_mpu_registers[32] = + { + TXM_MODULE_MPU_DEFAULT_RBAR_0, + TXM_MODULE_MPU_DEFAULT_RASR_0, + TXM_MODULE_MPU_DEFAULT_RBAR_1, + TXM_MODULE_MPU_DEFAULT_RASR_1, + TXM_MODULE_MPU_DEFAULT_RBAR_2, + TXM_MODULE_MPU_DEFAULT_RASR_2, + TXM_MODULE_MPU_DEFAULT_RBAR_3, + TXM_MODULE_MPU_DEFAULT_RASR_3, + TXM_MODULE_MPU_DEFAULT_RBAR_4, + TXM_MODULE_MPU_DEFAULT_RASR_4, + TXM_MODULE_MPU_DEFAULT_RBAR_5, + TXM_MODULE_MPU_DEFAULT_RASR_5, + TXM_MODULE_MPU_DEFAULT_RBAR_6, + TXM_MODULE_MPU_DEFAULT_RASR_6, + TXM_MODULE_MPU_DEFAULT_RBAR_7, + TXM_MODULE_MPU_DEFAULT_RASR_7, + TXM_MODULE_MPU_DEFAULT_RBAR_8, + TXM_MODULE_MPU_DEFAULT_RASR_8, + TXM_MODULE_MPU_DEFAULT_RBAR_9, + TXM_MODULE_MPU_DEFAULT_RASR_9, + TXM_MODULE_MPU_DEFAULT_RBAR_10, + TXM_MODULE_MPU_DEFAULT_RASR_10, + TXM_MODULE_MPU_DEFAULT_RBAR_11, + TXM_MODULE_MPU_DEFAULT_RASR_11, + TXM_MODULE_MPU_DEFAULT_RBAR_12, + TXM_MODULE_MPU_DEFAULT_RASR_12, + TXM_MODULE_MPU_DEFAULT_RBAR_13, + TXM_MODULE_MPU_DEFAULT_RASR_13, + TXM_MODULE_MPU_DEFAULT_RBAR_14, + TXM_MODULE_MPU_DEFAULT_RASR_14, + TXM_MODULE_MPU_DEFAULT_RBAR_15, + TXM_MODULE_MPU_DEFAULT_RASR_15 + }; +#endif /**************************************************************************/ /* */ @@ -231,7 +268,7 @@ UINT srd_bit_index; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_mm_register_setup Cortex-M7 */ -/* 6.1.9 */ +/* 6.1.12 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -267,10 +304,10 @@ UINT srd_bit_index; /* 9 Module shared memory region */ /* 10 Module shared memory region */ /* 11 Module shared memory region */ -/* 12 Unused region */ -/* 13 Unused region */ -/* 14 Unused region */ -/* 15 Unused region */ +/* 12 User-defined region */ +/* 13 User-defined region */ +/* 14 User-defined region */ +/* 15 User-defined region */ /* */ /* */ /* INPUT */ @@ -294,6 +331,8 @@ UINT srd_bit_index; /* DATE NAME DESCRIPTION */ /* */ /* 10-15-2021 Scott Larson Initial Version 6.1.9 */ +/* 07-29-2022 Scott Larson Enable user defined regions, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -456,18 +495,18 @@ UINT i; /* Increment MPU table index. */ mpu_table_index++; } - - /* Setup MPU for the remaining regions. */ - while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) - { - /* Build the base address register with address, MPU region, set Valid bit. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - - /* Increment MPU table index. */ - mpu_table_index++; - } -#else + /* Setup user-defined regions (12-15). */ + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_12; + module_instance -> txm_module_instance_mpu_registers[12].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_12; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_13; + module_instance -> txm_module_instance_mpu_registers[13].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_13; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_14; + module_instance -> txm_module_instance_mpu_registers[14].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_14; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_address = TXM_MODULE_MPU_USER_DEFINED_RBAR_15; + module_instance -> txm_module_instance_mpu_registers[15].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_USER_DEFINED_RASR_15; + +#else /* TXM_MODULE_MANAGER_16_MPU is not defined, only 8 MPU regions. */ ULONG code_address; ULONG code_size; diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex_r4/ac6/example_build/sample_threadx/.cproject new file mode 100644 index 000000000..71818fd90 --- /dev/null +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx/.cproject @@ -0,0 +1,170 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx/.project b/ports_module/cortex_r4/ac6/example_build/sample_threadx/.project new file mode 100644 index 000000000..a1b15572c --- /dev/null +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx/.project @@ -0,0 +1,26 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 000000000..4a6770593 --- /dev/null +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,374 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" +#include "timer.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; +UCHAR memory_area[DEMO_BYTE_POOL_SIZE]; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Setup the timer. */ + timer_init(); + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx/tx_cortex_r4.launch b/ports_module/cortex_r4/ac6/example_build/sample_threadx/tx_cortex_r4.launch new file mode 100644 index 000000000..4d4f7ba9c --- /dev/null +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx/tx_cortex_r4.launch @@ -0,0 +1,469 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protect.S index 08e8e54d9..e1960770a 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protect.S @@ -50,7 +50,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_smp_protect SMP/Cortex-A7/GNU */ -@/* 6.1 */ +@/* 6.1.12 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -81,7 +81,9 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 07-29-2022 Scott Larson Fixed preprocessor statement, */ +@/* resulting in version 6.1.12 */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_protect @@ -98,7 +100,7 @@ _tx_thread_smp_protect: #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if @ Disable IRQ and FIQ interrupts - ELSE +#else CPSID i @ Disable IRQ interrupts #endif @ @@ -249,7 +251,7 @@ _try_to_get_lock: @ #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if @ Disable IRQ and FIQ interrupts - ELSE +#else CPSID i @ Disable IRQ interrupts #endif diff --git a/utility/execution_profile_kit/smp_version/tx_execution_profile.c b/utility/execution_profile_kit/smp_version/tx_execution_profile.c new file mode 100644 index 000000000..b1dad888b --- /dev/null +++ b/utility/execution_profile_kit/smp_version/tx_execution_profile.c @@ -0,0 +1,1278 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Execution Profile Kit */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_execution_profile.h" + +/* The thread execution profile kit is designed to track thread execution time + based on the hardware timer defined by TX_EXECUTION_TIME_SOURCE and + TX_EXECUTION_MAX_TIME_SOURCE below. When the thread's total time reaches + the maximum value, it remains there until the time is reset to 0 via a call + to tx_thread_execution_time_reset. There are several assumptions to the + operation of this kit, as follows: + + 1. In tx_port.h replace: + + #define TX_THREAD_EXTENSION_3" + + with: + + #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ + unsigned long tx_thread_execution_time_last_start; + + Note: if 64-bit time source is present, the tx_thread_execution_time_last_start type should be unsigned long long. + + 2. The TX_EXECUTION_TIME_SOURCE and TX_EXECUTION_MAX_TIME_SOURCE macros are + defined to utilize a local hardware time source. + + 3. ThreadX 5.4 (or later) is being used, with the assembly code enabled to + call the following routines from assembly code: + + VOID _tx_execution_thread_enter(void); + VOID _tx_execution_thread_exit(void); + VOID _tx_execution_isr_enter(void); + VOID _tx_execution_isr_exit(void); + + 4. The ThreadX library assembly code must be rebuilt with TX_ENABLE_EXECUTION_CHANGE_NOTIFY so + that these macros are expanded in the TX_THREAD structure and so the assembly code macros + are enabled to call the execution profile routines. + + 5. Add tx_execution_profile.c to the application build. */ + + +/* Externally reference several internal ThreadX variables. */ + +extern ULONG _tx_thread_system_state[TX_THREAD_SMP_MAX_CORES]; +extern UINT _tx_thread_preempt_disable; +extern TX_THREAD *_tx_thread_current_ptr[TX_THREAD_SMP_MAX_CORES]; +extern TX_THREAD *_tx_thread_execute_ptr[TX_THREAD_SMP_MAX_CORES]; +extern TX_THREAD *_tx_thread_created_ptr; +extern ULONG _tx_thread_created_count; + + +/* Define the total time for all threads. This is accumulated as each thread's total time is accumulated. */ + +EXECUTION_TIME _tx_execution_thread_time_total[TX_THREAD_SMP_MAX_CORES]; + + +/* Define the ISR time gathering information. This is setup to track total ISR time presently, but + could easily be expanded to track different ISRs. Also, only ISRs that utilize _tx_thread_context_save + and _tx_thread_context_restore are tracked by this utility. */ + +EXECUTION_TIME _tx_execution_isr_time_total[TX_THREAD_SMP_MAX_CORES]; +EXECUTION_TIME_SOURCE_TYPE _tx_execution_isr_time_last_start[TX_THREAD_SMP_MAX_CORES]; + + +/* Define the system idle time gathering information. For idle time that exceeds the range of the timer + source, another timer source may be needed. In addition, the total thread execution time added to the + total ISR time, less the total system time is also a measure of idle time. */ + +EXECUTION_TIME _tx_execution_idle_time_total[TX_THREAD_SMP_MAX_CORES]; +EXECUTION_TIME_SOURCE_TYPE _tx_execution_idle_time_last_start[TX_THREAD_SMP_MAX_CORES]; + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_execution_thread_enter PORTABLE SMP */ +/* 6.1.12 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called whenever thread execution starts. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_schedule Thread scheduling */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 07-29-2022 William E. Lamie Initial Version 6.1.12 */ +/* */ +/**************************************************************************/ +VOID _tx_execution_thread_enter(void) +{ + +TX_THREAD *thread_ptr; +EXECUTION_TIME_SOURCE_TYPE last_start_time; +EXECUTION_TIME_SOURCE_TYPE current_time; +EXECUTION_TIME delta_time; +EXECUTION_TIME total_time; +EXECUTION_TIME new_total_time; +UINT core; + + + /* Pickup the current time. */ + current_time = TX_EXECUTION_TIME_SOURCE; + + /* Pickup the core index. */ + core = TX_SMP_CORE_ID; + + /* Pickup the current thread control block. */ + thread_ptr = _tx_thread_current_ptr[core]; + + /* This thread is being scheduled. Simply setup the last start time in the + thread control block. */ + thread_ptr -> tx_thread_execution_time_last_start = current_time; + + /* Pickup the last idle start time. */ + last_start_time = _tx_execution_idle_time_last_start[core]; + + /* Determine if idle time is being measured. */ + if (last_start_time) + { + + /* Determine how to calculate the difference. */ + if (current_time >= last_start_time) + { + + /* Simply subtract. */ + delta_time = (EXECUTION_TIME) (current_time - last_start_time); + } + else + { + + /* Timer wrapped, compute the delta assuming incrementing time counter. */ + delta_time = (EXECUTION_TIME) (current_time + (((EXECUTION_TIME_SOURCE_TYPE) TX_EXECUTION_MAX_TIME_SOURCE) - last_start_time)); + } + + /* Pickup the total time. */ + total_time = _tx_execution_idle_time_total[core]; + + /* Now compute the new total time. */ + new_total_time = total_time + delta_time; + + /* Determine if a rollover on the total time is present. */ + if (new_total_time < total_time) + { + + /* Rollover. Set the total time to max value. */ + new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; + } + + /* Now store back the total idle time. */ + _tx_execution_idle_time_total[core] = new_total_time; + + /* Disable the idle time measurement. */ + _tx_execution_idle_time_last_start[core] = 0; + } +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_execution_thread_exit PORTABLE SMP */ +/* 6.1.12 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called whenever a thread execution ends. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_system_return Thread exiting */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 07-29-2022 William E. Lamie Initial Version 6.1.12 */ +/* */ +/**************************************************************************/ +VOID _tx_execution_thread_exit(void) +{ + +TX_THREAD *thread_ptr; +EXECUTION_TIME total_time; +EXECUTION_TIME new_total_time; +EXECUTION_TIME_SOURCE_TYPE last_start_time; +EXECUTION_TIME_SOURCE_TYPE current_time; +EXECUTION_TIME delta_time; +UINT core; + + + /* Pickup the core index. */ + core = TX_SMP_CORE_ID; + + /* Pickup the current thread control block. */ + thread_ptr = _tx_thread_current_ptr[core]; + + /* Determine if there is a thread. */ + if (thread_ptr) + { + + /* Pickup the current time. */ + current_time = TX_EXECUTION_TIME_SOURCE; + + /* Pickup the last start time. */ + last_start_time = thread_ptr -> tx_thread_execution_time_last_start; + + /* Determine if there is an actual start time. */ + if (last_start_time) + { + + /* Clear the last start time. */ + thread_ptr -> tx_thread_execution_time_last_start = 0; + + /* Determine how to calculate the difference. */ + if (current_time >= last_start_time) + { + + /* Simply subtract. */ + delta_time = (EXECUTION_TIME) (current_time - last_start_time); + } + else + { + + /* Timer wrapped, compute the delta assuming incrementing time counter. */ + delta_time = (EXECUTION_TIME) (current_time + (((EXECUTION_TIME_SOURCE_TYPE) TX_EXECUTION_MAX_TIME_SOURCE) - last_start_time)); + } + + /* Pickup the total time. */ + total_time = thread_ptr -> tx_thread_execution_time_total; + + /* Now compute the new total time. */ + new_total_time = total_time + delta_time; + + /* Determine if a rollover on the total time is present. */ + if (new_total_time < total_time) + { + + /* Rollover. Set the total time to max value. */ + new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; + } + + /* Store back the new total time. */ + thread_ptr -> tx_thread_execution_time_total = new_total_time; + + /* Now accumulate this thread's execution time into the total thread execution time. */ + new_total_time = _tx_execution_thread_time_total[core] + delta_time; + + /* Determine if a rollover on the total time is present. */ + if (new_total_time < _tx_execution_thread_time_total[core]) + { + + /* Rollover. Set the total time to max value. */ + new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; + } + + /* Store back the new total time. */ + _tx_execution_thread_time_total[core] = new_total_time; + } + + /* Is the system now idle? */ + if (_tx_thread_execute_ptr[core] == TX_NULL) + { + + /* Yes, idle system. Pickup the start of idle time. */ + _tx_execution_idle_time_last_start[core] = TX_EXECUTION_TIME_SOURCE; + } + } +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_execution_isr_enter PORTABLE SMP */ +/* 6.1.12 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called whenever ISR processing starts. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_context_save ISR context save */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 07-29-2022 William E. Lamie Initial Version 6.1.12 */ +/* */ +/**************************************************************************/ +VOID _tx_execution_isr_enter(void) +{ + +TX_THREAD *thread_ptr; +EXECUTION_TIME_SOURCE_TYPE current_time; +EXECUTION_TIME total_time; +EXECUTION_TIME new_total_time; +EXECUTION_TIME_SOURCE_TYPE last_start_time; +EXECUTION_TIME delta_time; +UINT core; + + + /* Pickup the core index. */ + core = TX_SMP_CORE_ID; + + /* Determine if this is the first interrupt. Nested interrupts are all treated as + general interrupt processing. */ + if (_tx_thread_system_state[core] == 1) + { + /* Pickup the current time. */ + current_time = TX_EXECUTION_TIME_SOURCE; + + /* Pickup the current thread control block. */ + thread_ptr = _tx_thread_current_ptr[core]; + + /* Determine if a thread was interrupted. */ + if (thread_ptr) + { + + /* Pickup the last start time. */ + last_start_time = thread_ptr -> tx_thread_execution_time_last_start; + + /* Determine if there is an actual start time. */ + if (last_start_time) + { + + /* Clear the last start time. */ + thread_ptr -> tx_thread_execution_time_last_start = 0; + + /* Determine how to calculate the difference. */ + if (current_time >= last_start_time) + { + + /* Simply subtract. */ + delta_time = (EXECUTION_TIME) (current_time - last_start_time); + } + else + { + + /* Timer wrapped, compute the delta assuming incrementing time counter. */ + delta_time = (EXECUTION_TIME) (current_time + (((EXECUTION_TIME_SOURCE_TYPE) TX_EXECUTION_MAX_TIME_SOURCE) - last_start_time)); + } + + /* Pickup the total time. */ + total_time = thread_ptr -> tx_thread_execution_time_total; + + /* Now compute the new total time. */ + new_total_time = total_time + delta_time; + + /* Determine if a rollover on the total time is present. */ + if (new_total_time < total_time) + { + + /* Rollover. Set the total time to max value. */ + new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; + } + + /* Store back the new total time. */ + thread_ptr -> tx_thread_execution_time_total = new_total_time; + + /* Now accumulate this thread's execution time into the total thread execution time. */ + new_total_time = _tx_execution_thread_time_total[core] + delta_time; + + /* Determine if a rollover on the total time is present. */ + if (new_total_time < _tx_execution_thread_time_total[core]) + { + + /* Rollover. Set the total time to max value. */ + new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; + } + + /* Store back the new total time. */ + _tx_execution_thread_time_total[core] = new_total_time; + } + } + + /* Has idle time started? */ + else if (_tx_execution_idle_time_last_start[core]) + { + + /* Pickup the last idle start time. */ + last_start_time = _tx_execution_idle_time_last_start[core]; + + /* Determine how to calculate the difference. */ + if (current_time >= last_start_time) + { + + /* Simply subtract. */ + delta_time = (EXECUTION_TIME) (current_time - last_start_time); + } + else + { + + /* Timer wrapped, compute the delta assuming incrementing time counter. */ + delta_time = (EXECUTION_TIME) (current_time + (((EXECUTION_TIME_SOURCE_TYPE) TX_EXECUTION_MAX_TIME_SOURCE) - last_start_time)); + } + + /* Pickup the total time. */ + total_time = _tx_execution_idle_time_total[core]; + + /* Now compute the new total time. */ + new_total_time = total_time + delta_time; + + /* Determine if a rollover on the total time is present. */ + if (new_total_time < total_time) + { + + /* Rollover. Set the total time to max value. */ + new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; + } + + /* Now store back the total idle time. */ + _tx_execution_idle_time_total[core] = new_total_time; + + /* Disable the idle time measurement. */ + _tx_execution_idle_time_last_start[core] = 0; + } + + /* Save the ISR start time. */ + _tx_execution_isr_time_last_start[core] = current_time; + } +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_execution_isr_exit PORTABLE SMP */ +/* 6.1.12 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called whenever ISR processing ends. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_context_restore Thread de-scheduling */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 07-29-2022 William E. Lamie Initial Version 6.1.12 */ +/* */ +/**************************************************************************/ +VOID _tx_execution_isr_exit(void) +{ + +TX_THREAD *thread_ptr; +EXECUTION_TIME total_time; +EXECUTION_TIME new_total_time; +EXECUTION_TIME_SOURCE_TYPE last_start_time; +EXECUTION_TIME_SOURCE_TYPE current_time; +EXECUTION_TIME delta_time; +UINT core; + + + /* Pickup the core index. */ + core = TX_SMP_CORE_ID; + + /* Determine if this is the first interrupt. Nested interrupts are all treated as + general interrupt processing. */ + if (_tx_thread_system_state[core] == 1) + { + + /* Pickup the current time. */ + current_time = TX_EXECUTION_TIME_SOURCE; + + /* Pickup the last start time. */ + last_start_time = _tx_execution_isr_time_last_start[core]; + + /* Determine how to calculate the difference. */ + if (current_time >= last_start_time) + { + + /* Simply subtract. */ + delta_time = (EXECUTION_TIME) (current_time - last_start_time); + } + else + { + + /* Timer wrapped, compute the delta assuming incrementing time counter. */ + delta_time = (EXECUTION_TIME) (current_time + (((EXECUTION_TIME_SOURCE_TYPE) TX_EXECUTION_MAX_TIME_SOURCE) - last_start_time)); + } + + /* Pickup the total time. */ + total_time = _tx_execution_isr_time_total[core]; + + /* Now compute the new total time. */ + new_total_time = total_time + delta_time; + + /* Determine if a rollover on the total time is present. */ + if (new_total_time < total_time) + { + + /* Rollover. Set the total time to max value. */ + new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; + } + + /* Store back the new total time. */ + _tx_execution_isr_time_total[core] = new_total_time; + + /* Pickup the current thread control block. */ + thread_ptr = _tx_thread_current_ptr[core]; + + /* Was a thread interrupted? */ + if (thread_ptr) + { + + /* Now determine if the thread will execution is going to occur immediately. */ + if ((thread_ptr == _tx_thread_execute_ptr[core]) || (_tx_thread_preempt_disable)) + { + + /* Yes, setup the thread last start time in the thread control block. */ + thread_ptr -> tx_thread_execution_time_last_start = current_time; + } + } + + /* Determine if the system is now idle. */ + if (_tx_thread_execute_ptr[core] == TX_NULL) + { + + /* Yes, idle system. Pickup the start of idle time. */ + _tx_execution_idle_time_last_start[core] = TX_EXECUTION_TIME_SOURCE; + } + } +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_execution_thread_time_reset PORTABLE SMP */ +/* 6.1.12 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function resets the execution time of the specified thread. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 07-29-2022 William E. Lamie Initial Version 6.1.12 */ +/* */ +/**************************************************************************/ +UINT _tx_execution_thread_time_reset(TX_THREAD *thread_ptr) +{ + + /* Reset the total time to 0. */ + thread_ptr -> tx_thread_execution_time_total = 0; + + /* Return success. */ + return(TX_SUCCESS); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_execution_thread_total_time_reset PORTABLE SMP */ +/* 6.1.12 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function resets the total thread execution time. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 07-29-2022 William E. Lamie Initial Version 6.1.12 */ +/* */ +/**************************************************************************/ +UINT _tx_execution_thread_total_time_reset(void) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +UINT total_threads; +UINT core; + + + /* Disable interrupts. */ + TX_DISABLE + + /* Reset the total time for all cores. */ + for (core = 0; core < TX_THREAD_SMP_MAX_CORES; core++) + { + + _tx_execution_thread_time_total[core] = 0; + } + + /* Loop through threads to clear their accumulated time. */ + total_threads = _tx_thread_created_count; + thread_ptr = _tx_thread_created_ptr; + while (total_threads--) + { + thread_ptr -> tx_thread_execution_time_total = 0; + thread_ptr = thread_ptr -> tx_thread_created_next; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success. */ + return(TX_SUCCESS); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_execution_isr_time_reset PORTABLE SMP */ +/* 6.1.12 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function resets the execution time of the ISR calculation. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 07-29-2022 William E. Lamie Initial Version 6.1.12 */ +/* */ +/**************************************************************************/ +UINT _tx_execution_isr_time_reset(void) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT core; + + /* Disable interrupts. */ + TX_DISABLE + + /* Reset the ISR total time to 0. */ + for (core = 0; core < TX_THREAD_SMP_MAX_CORES; core++) + { + + _tx_execution_isr_time_total[core] = 0; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success. */ + return(TX_SUCCESS); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_execution_idle_time_reset PORTABLE SMP */ +/* 6.1.12 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function resets the idle execution time calculation. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 07-29-2022 William E. Lamie Initial Version 6.1.12 */ +/* */ +/**************************************************************************/ +UINT _tx_execution_idle_time_reset(void) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT core; + + /* Disable interrupts. */ + TX_DISABLE + + /* Reset the idle total time to 0. */ + for (core = 0; core < TX_THREAD_SMP_MAX_CORES; core++) + { + + _tx_execution_idle_time_total[core] = 0; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success. */ + return(TX_SUCCESS); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_execution_thread_time_get PORTABLE SMP */ +/* 6.1.12 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the execution time of the specified thread. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to the thread */ +/* total_time Destination for total time */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 07-29-2022 William E. Lamie Initial Version 6.1.12 */ +/* */ +/**************************************************************************/ +UINT _tx_execution_thread_time_get(TX_THREAD *thread_ptr, EXECUTION_TIME *total_time) +{ + + /* Return the total time. */ + *total_time = thread_ptr -> tx_thread_execution_time_total; + + /* Return success. */ + return(TX_SUCCESS); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_execution_thread_total_time_get PORTABLE SMP */ +/* 6.1.12 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the execution time of all threads. */ +/* */ +/* INPUT */ +/* */ +/* total_time Destination for total time */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 07-29-2022 William E. Lamie Initial Version 6.1.12 */ +/* */ +/**************************************************************************/ +UINT _tx_execution_thread_total_time_get(EXECUTION_TIME *total_time) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT core; + + /* Disable interrupts. */ + TX_DISABLE + + /* Return the total thread time. */ + for (core = 0; core < TX_THREAD_SMP_MAX_CORES; core++) + { + + *total_time = _tx_execution_thread_time_total[core]; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success. */ + return(TX_SUCCESS); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_execution_isr_time_get PORTABLE SMP */ +/* 6.1.12 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the execution time of all ISRs. */ +/* */ +/* INPUT */ +/* */ +/* total_time Destination for total time */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 07-29-2022 William E. Lamie Initial Version 6.1.12 */ +/* */ +/**************************************************************************/ +UINT _tx_execution_isr_time_get(EXECUTION_TIME *total_time) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT core; + + /* Disable interrupts. */ + TX_DISABLE + + /* Return the total ISR time. */ + for (core = 0; core < TX_THREAD_SMP_MAX_CORES; core++) + { + + /* Return the total time. */ + *total_time = _tx_execution_isr_time_total[core]; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success. */ + return(TX_SUCCESS); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_execution_idle_time_get PORTABLE SMP */ +/* 6.1.12 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the total system idle time. */ +/* */ +/* INPUT */ +/* */ +/* total_time Destination for total time */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 07-29-2022 William E. Lamie Initial Version 6.1.12 */ +/* */ +/**************************************************************************/ +UINT _tx_execution_idle_time_get(EXECUTION_TIME *total_time) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT core; + + /* Disable interrupts. */ + TX_DISABLE + + /* Return the total time. */ + for (core = 0; core < TX_THREAD_SMP_MAX_CORES; core++) + { + + /* Return the total time. */ + *total_time = _tx_execution_idle_time_total[core]; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success. */ + return(TX_SUCCESS); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_execution_core_thread_total_time_get PORTABLE SMP */ +/* 6.1.12 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the total thread execution time of the */ +/* specified core. */ +/* */ +/* INPUT */ +/* */ +/* core Specified core */ +/* total_time Destination for total time */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 07-29-2022 William E. Lamie Initial Version 6.1.12 */ +/* */ +/**************************************************************************/ +UINT _tx_execution_core_thread_total_time_get(UINT core, EXECUTION_TIME *total_time) +{ + + /* Determine if the core is valid. */ + if (core >= TX_THREAD_SMP_MAX_CORES) + { + + /* Invalid core, return an error. */ + return(TX_NOT_DONE); + } + + /* Return the total thread time for the core. */ + *total_time = _tx_execution_thread_time_total[core]; + + /* Return success. */ + return(TX_SUCCESS); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_execution_core_isr_time_get PORTABLE SMP */ +/* 6.1.12 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the execution time of ISRs on the specified */ +/* core. */ +/* */ +/* INPUT */ +/* */ +/* core Specified core */ +/* total_time Destination for total time */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 07-29-2022 William E. Lamie Initial Version 6.1.12 */ +/* */ +/**************************************************************************/ +UINT _tx_execution_core_isr_time_get(UINT core, EXECUTION_TIME *total_time) +{ + + /* Determine if the core is valid. */ + if (core >= TX_THREAD_SMP_MAX_CORES) + { + + /* Invalid core, return an error. */ + return(TX_NOT_DONE); + } + + /* Return the total ISR time for this core. */ + *total_time = _tx_execution_isr_time_total[core]; + + /* Return success. */ + return(TX_SUCCESS); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_execution_core_idle_time_get PORTABLE SMP */ +/* 6.1.12 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the idle time of the specified core. */ +/* */ +/* INPUT */ +/* */ +/* core Specified core */ +/* total_time Destination for total time */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 07-29-2022 William E. Lamie Initial Version 6.1.12 */ +/* */ +/**************************************************************************/ +UINT _tx_execution_core_idle_time_get(UINT core, EXECUTION_TIME *total_time) +{ + + /* Determine if the core is valid. */ + if (core >= TX_THREAD_SMP_MAX_CORES) + { + + /* Invalid core, return an error. */ + return(TX_NOT_DONE); + } + + /* Return the total idle time for this core. */ + *total_time = _tx_execution_idle_time_total[core]; + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/utility/execution_profile_kit/smp_version/tx_execution_profile.h b/utility/execution_profile_kit/smp_version/tx_execution_profile.h new file mode 100644 index 000000000..7149a79f9 --- /dev/null +++ b/utility/execution_profile_kit/smp_version/tx_execution_profile.h @@ -0,0 +1,93 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Execution Profile Kit */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#ifndef TX_EXECUTION_PROFILE_H +#define TX_EXECUTION_PROFILE_H + + +/* The thread execution profile kit is designed to track thread execution time + based on the hardware timer defined by TX_EXECUTION_TIME_SOURCE and + TX_EXECUTION_MAX_TIME_SOURCE below. When the thread's total time reaches + the maximum value, it remains there until the time is reset to 0 via a call + to tx_thread_execution_time_reset. There are several assumptions to the + operation of this kit, as follows: + + 1. In tx_port.h replace: + #define TX_THREAD_EXTENSION_3" + with: + #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ + unsigned long tx_thread_execution_time_last_start; + + 2. The TX_EXECUTION_TIME_SOURCE and TX_EXECUTION_MAX_TIME_SOURCE macros are + defined to utilize a local hardware time source. + + 3. The following routines are called from assembly code: + VOID _tx_execution_thread_enter(void); + VOID _tx_execution_thread_exit(void); + VOID _tx_execution_isr_enter(void); + VOID _tx_execution_isr_exit(void); + + 4. The ThreadX library must be rebuilt with TX_ENABLE_EXECUTION_CHANGE_NOTIFY so + that these macros are expanded in the TX_THREAD structure and so the assembly code macros + are enabled to call the execution profile routines. + + 5. Add tx_execution_profile.c to the application build. */ + +/* Define the basic time typedefs for 64-bit accumulation and a 32-bit timer source, which is the + most common configuration. */ + +typedef unsigned long long EXECUTION_TIME; +typedef unsigned long EXECUTION_TIME_SOURCE_TYPE; +/* For 64-bit time source, the typedef would be: */ +/* typedef unsigned long long EXECUTION_TIME_SOURCE_TYPE; */ + +/* Define basic constants for the execution profile kit. */ + +ULONG _tx_thread_smp_time_get(void); + +#define TX_EXECUTION_TIME_SOURCE (EXECUTION_TIME_SOURCE_TYPE) _tx_thread_smp_time_get(); +#define TX_EXECUTION_MAX_TIME_SOURCE 0xFFFFFFFF +/* For 64-bit time source, the constant would be: */ +/* #define TX_EXECUTION_MAX_TIME_SOURCE 0xFFFFFFFFFFFFFFFF */ + + +/* Define APIs of the execution profile kit. */ + +struct TX_THREAD_STRUCT; +VOID _tx_execution_thread_enter(void); +VOID _tx_execution_thread_exit(void); +VOID _tx_execution_isr_enter(void); +VOID _tx_execution_isr_exit(void); +UINT _tx_execution_thread_time_reset(struct TX_THREAD_STRUCT *thread_ptr); +UINT _tx_execution_thread_total_time_reset(void); +UINT _tx_execution_isr_time_reset(void); +UINT _tx_execution_idle_time_reset(void); +UINT _tx_execution_thread_time_get(struct TX_THREAD_STRUCT *thread_ptr, EXECUTION_TIME *total_time); +UINT _tx_execution_thread_total_time_get(EXECUTION_TIME *total_time); +UINT _tx_execution_isr_time_get(EXECUTION_TIME *total_time); +UINT _tx_execution_idle_time_get(EXECUTION_TIME *total_time); +UINT _tx_execution_core_thread_total_time_get(UINT core, EXECUTION_TIME *total_time); +UINT _tx_execution_core_isr_time_get(UINT core, EXECUTION_TIME *total_time); +UINT _tx_execution_core_idle_time_get(UINT core, EXECUTION_TIME *total_time); + +#endif diff --git a/utility/low_power/low_power.md b/utility/low_power/low_power.md index 8be714a39..ed25ccd6f 100644 --- a/utility/low_power/low_power.md +++ b/utility/low_power/low_power.md @@ -8,25 +8,209 @@ ms.topic: article ms.service: rtos --- -# Low Power APIs +# ThreadX Low Power Utilities -## Summary of Low Power APIs +These low power utilities are intended to maintain ThreadX timers and the internal tick count while the processor is in a low-power/sleep state. The terms "low power" and "sleep" are used interchangeably throughout this document. -There are additional API functions available for low power, as follows: +The low power utilities may be used with any ThreadX port except SMP. -- ***tx_low_power_enter*** - *Enter low power mode* -- ***tx_low_power_exit*** - *Exit low power mode* -- ***tx_time_increment*** - *Increment ThreadX timers by specific amount* -- ***tx_timer_get_next*** - *Get next ThreadX timer expiration* +## Installation of Low Power Utilities + +The ThreadX low power utilities are comprised of two files: + + - [tx_low_power.c](tx_low_power.c) + - [tx_low_power.h](tx_low_power.h) + +These files can be built with the ThreadX library or built in the user application. + +## Detailed Description + +By default, ThreadX spins in an idle loop in the scheduler when there are no threads ready to run. It may be desireable to put the processor in a low power state while idle. Functions ```tx_low_power_enter``` and ```tx_low_power_exit``` are designed to enter and exit low power mode, respectively. + +The ```tx_low_power_enter``` and ```tx_low_power_exit``` functions manage the ThreadX timers and invoke optional macros that the user must define in order to configure the hardware for low power mode. These macros are discussed in a section below. + +For convenience, the Cortex-M and RX ports have calls to the low power APIs already integrated into their schedulers. If symbol **TX_LOW_POWER** is defined, functions ```tx_low_power_enter``` and ```tx_low_power_exit``` are called in the scheduler idle loop. It is assumed that the processor will exit sleep mode and resume execution in the idle loop (or in an interrupt and then return to the idle loop). For processors that exhibit different behavior (such as waking from sleep at the reset vector), these low power functions may need to be called elsewhere. + +### Low Power Timer and Tick-less Low Power Mode + +If accurate timekeeping is not desired while in low power mode, macros **TX_LOW_POWER_TIMER_SETUP** and **TX_LOW_POWER_TICKLESS** do not need to be defined. The internal ThreadX tick count will not reflect the time spent in low power mode. + +If **TX_LOW_POWER_TIMER_SETUP** is defined, there are two use cases for timekeeping in low power operation: +1. Keep track of elapsed time in low power mode only when ThreadX timers are active. If there are ThreadX timers active, the elapsed time while in low power mode must be measured, thus a low power hardware timer is required (this timer can be configured in **TX_LOW_POWER_TIMER_SETUP**). If there are no ThreadX timers active when entering low power mode, then no hardware timer needs to keep track of elapsed time. This is "tick-less" operation. To enable this feature, the symbol **TX_LOW_POWER_TICKLESS** must be defined. The internal ThreadX tick count will not reflect the time spent in low power mode when no ThreadX timers are active. +2. Always keep track of time in low power mode. This is necessary to keep the internal ThreadX tick count accurate. In this case, **TX_LOW_POWER_TICKLESS** must *not* be defined, as a hardware timer will always be needed in low power mode to measure elapsed time. The hardware timer is intended to be configured in **TX_LOW_POWER_TIMER_SETUP**. + +> Example 1: No low power timer is in use (**TX_LOW_POWER_TIMER_SETUP** is *not* defined). There is a ThreadX timer with 50 ticks remaining. The internal ThreadX tick count is 1000. The processor goes into low power mode for some length of time. After exiting low power mode, the ThreadX timer still has 50 ticks remaining. The internal ThreadX tick count is 1000. + +> Example 2: A low power timer is available (**TX_LOW_POWER_TIMER_SETUP** is defined). **TX_LOW_POWER_TICKLESS** is defined. There is a ThreadX timer A with 50 ticks remaining and another ThreadX timer B with 20 ticks remaining. The internal ThreadX tick count is 1000. The processor goes into low power mode for 20 ticks. Upon exiting low power mode, the ThreadX timer A will have 30 ticks remaining. The expiration function for ThreadX timer B will be executed. The internal ThreadX tick count is 1020. +After executing for some time, the internal ThreadX tick count is 2000 and there are no ThreadX timers active. The processor goes into low power mode for some length of time. After exiting low power mode, the internal ThreadX tick count is 2000. + +> Example 3: A low power timer is always used (**TX_LOW_POWER_TIMER_SETUP** is defined and **TX_LOW_POWER_TICKLESS** is *not* defined). The internal ThreadX tick count is 1000 and there are no ThreadX timers active. The processor goes into low power mode for some length of time. Upon exiting low power mode, it is determined that the processor was in low power mode for 20 ticks. The internal ThreadX tick count is updated to 1020. ---- ## User-defined Macros -- **TX_LOW_POWER_TIMER_SETUP** - an optional macro to a user routine that sets up a low power clock. To set up a low power timer or operate ticklessly in low power mode, this must be defined. This is called in **tx_low_power_enter**. -- **TX_LOW_POWER_TICKLESS** - an optional define to operate ticklessly in low power mode. Symbol **TX_LOW_POWER_TIMER_SETUP** must also be defined. With this defined, there is no need to set up a low power timer to keep track of time. ThreadX will not maintain/update the internal tick count during or after exiting low power mode. -- **TX_LOW_POWER_USER_ENTER** - an optional macro to a user routine that configures the processor for entering low power mode (e.g. turn off peripherals and select a sleep mode). This is called in **tx_low_power_enter**. -- **TX_LOW_POWER_USER_EXIT** - an optional macro to a user routine that configures the processor for exiting low power mode (e.g. turn on peripherals). This is called in **tx_low_power_exit**. -- **TX_LOW_POWER_USER_TIMER_ADJUST** - an optional user macro to determine how much time has elapsed while in low power mode (in units of ThreadX ticks). This is called in **tx_low_power_exit** to get the number of ticks needed to adjust the ThreadX timers. +The following macros invoke functions that the user may want to define/implement. + +### Summary of user-defined macros + + - ```TX_LOW_POWER_TIMER_SETUP``` - *set up low power timer* + - ```TX_LOW_POWER_USER_ENTER``` - *configure processor to enter low power mode* + - ```TX_LOW_POWER_USER_EXIT``` - *configure processor to exit low power mode* + - ```TX_LOW_POWER_USER_TIMER_ADJUST``` - *return the number of ticks the processor was in low power mode* + +--- + +### TX_LOW_POWER_TIMER_SETUP +```c +VOID TX_LOW_POWER_TIMER_SETUP(ULONG tx_low_power_next_expiration); +``` + +### Input parameters + +- *tx_low_power_next_expiration* - the number of ticks to configure the low power timer. + +### Return values + +- *none* + +**TX_LOW_POWER_TIMER_SETUP** is a macro invoking user-defined function that sets up a low power timer. To set up a low power timer or operate ticklessly in low power mode, this symbol must be defined. This macro is called in ```tx_low_power_enter```. If **TX_LOW_POWER_TICKLESS** is not defined and there are no timers active, the *tx_low_power_next_expiration* parameter will be set to 0xFFFFFFFF. + +> Note: The number of ThreadX ticks is the input to this function. The frequency of a ThreadX timer tick is defined in **TX_TIMER_TICKS_PER_SECOND** (typically defined in file tx_api.h, tx_user.h, or tx_port.h). + +> Note: do not put the processor to sleep in this macro. + +### Optional Define + +- **TX_LOW_POWER_TICKLESS** - an optional define to operate ticklessly in low power mode only if no ThreadX timers are active. With symbol **TX_LOW_POWER_TICKLESS** defined, if there are no ThreadX timers active, **TX_LOW_POWER_TIMER_SETUP** will not be called in ```tx_low_power_enter```. ThreadX will not maintain/update the internal tick count during or after exiting low power mode. Symbol **TX_LOW_POWER_TIMER_SETUP** must also be defined if defining **TX_LOW_POWER_TICKLESS**. + +### Example + +```c +/* Low power timer function prototype. */ +void low_power_timer_config(ULONG ticks); + +/* Define the TX_LOW_POWER_TIMER_SETUP macro. */ +#define TX_LOW_POWER_TIMER_SETUP low_power_timer_config + +void low_power_timer_config(ULONG ticks) +{ + /* Insert code here to configure a hardware timer + to wake the processor from sleep after + ticks/TX_TIMER_TICKS_PER_SECOND seconds. */ +} +``` + +--- + +### TX_LOW_POWER_USER_ENTER +A macro invoking a user-defined function that configures the processor for entering low power mode (e.g. turn off peripherals and select a sleep mode). This macro is called in ```tx_low_power_enter```. + +### Input parameters + +- *none* + +### Return values + +- *none* + +### Example + +```c +/* Low power enter function prototype. */ +void low_power_enter(void); + +/* Define the TX_LOW_POWER_USER_ENTER macro. */ +#define TX_LOW_POWER_USER_ENTER low_power_enter + +void low_power_enter(void) +{ + /* Insert code here to configure the processor to enter low power mode. */ +} +``` +--- + +### TX_LOW_POWER_USER_EXIT +A macro invoking a user-defined function that configures the processor for exiting low power mode (e.g. turn on peripherals). This is called in ```tx_low_power_exit```. + +### Input parameters + +- *none* + +### Return values + +- *none* + +### Example + +```c +/* Low power exit function prototype. */ +void low_power_exit(void); + +/* Define the TX_LOW_POWER_USER_EXIT macro. */ +#define TX_LOW_POWER_USER_EXIT low_power_exit + +void low_power_exit(void) +{ + /* Insert code here to configure the processor to exit low power mode. */ +} +``` + +--- + +### TX_LOW_POWER_USER_TIMER_ADJUST + +```c +ULONG TX_LOW_POWER_USER_TIMER_ADJUST(VOID); +``` + +A macro invoking a user-defined function to determine how much time has elapsed while in low power mode (in units of ThreadX ticks). This is called in ```tx_low_power_exit``` and returns the number of ticks needed to adjust the ThreadX timers. + +When exiting low power mode, there are two possibilities: + 1. The processor slept for the entire time the timer was configured to sleep. + 2. The processor was awakened early. + +### Input parameters + +- *none* + +### Return values + +- *tx_low_power_adjust_ticks* + +### Example + +```c +/* Low power timer adjust function prototype. */ +ULONG low_power_timer_adjust(void); + +/* Define the TX_LOW_POWER_USER_TIMER_ADJUST macro. */ +#define TX_LOW_POWER_USER_TIMER_ADJUST low_power_timer_adjust + +ULONG low_power_timer_adjust(void) +{ + ULONG actual_ticks_slept; + ULONG elapsed_time_in_ms; + + /* Insert code here to read timer registers to determine + how long the processor actually slept. */ + elapsed_time_in_ms = read_timer_register(); + + /* Convert elapsed time to ThreadX ticks. */ + actual_ticks_slept = elapsed_time_in_ms / (1000/TX_TIMER_TICKS_PER_SECOND); + + return(actual_ticks_slept); +} +``` + +--- + +## Summary of Low Power APIs + +- ```tx_low_power_enter``` - *Enter low power mode* +- ```tx_low_power_exit``` - *Exit low power mode* +- ```tx_time_increment``` - *Increment ThreadX timers by specific amount* +- ```tx_timer_get_next``` - *Get next ThreadX timer expiration* + +--- ## tx_low_power_enter @@ -40,26 +224,24 @@ VOID tx_low_power_enter(VOID); ### Description -This service enters low power mode. -For keeping track of time while in low power mode, there are two possibilities: +This service enters low power mode. The macros **TX_LOW_POWER_TIMER_SETUP** and **TX_LOW_POWER_USER_ENTER** are called in this function to allow the user to configure a low power timer and configure the hardware for low power mode. -1. A ThreadX timer is active. Function **tx_timer_get_next** returns **TX_TRUE**. Note that in this situation, a low power clock must be used in order to wake up the CPU for the next ThreadX timer expiration. Therefore an alternative clock must be programmed. Program the hardware timer source such that the next timer interrupt is equal to: *tx_low_power_next_expiration \* tick_frequency*. The *tick_frequency* is application-specific and typically set up in **tx_low_level_initialize**. +For keeping track of time while in low power mode, there are two possibilities: -2. There are no ThreadX timers active. Function **tx_timer_get_next** returns **TX_FALSE**. - 1. The application may choose not to keep the ThreadX internal - tick count updated (define **TX_LOW_POWER_TICKLESS**), therefore there is no need - to set up a low power clock. +1. A ThreadX timer is active. Function ```tx_timer_get_next``` returns **TX_TRUE**. Note that in this situation, a low power clock must be used in order to wake up the CPU for the next ThreadX timer expiration. Therefore a low power timer/clock must be programmed. Program the hardware timer source such that the next timer interrupt is equal to: *tx_low_power_next_expiration \* tick_frequency*. The *tick_frequency* is application-specific and typically set up in ```tx_low_level_initialize```. - 2. The application still needs to keep the ThreadX tick up-to-date. In this case - a low power clock needs to be set up. +2. There are no ThreadX timers active. Function ```tx_timer_get_next``` returns *TX_FALSE*. + 1. The application may choose **not** to keep the ThreadX internal + tick count updated (define **TX_LOW_POWER_TICKLESS**), therefore there is no need to set up a low power clock. + 2. The application still needs to keep the ThreadX tick up-to-date. In this case a low power clock needs to be configured. ### Input parameters -- **none** +- *none* ### Return values -- **none** +- *none* ### Allowed from @@ -67,7 +249,7 @@ Internal ThreadX code, application ### Example -ARM assembly +ARM Cortex-M assembly ```c #ifdef TX_LOW_POWER PUSH {r0-r3} @@ -106,15 +288,15 @@ VOID tx_low_power_exit(VOID); ### Description -This service exits low power mode. +This service exits low power mode. Macro **TX_LOW_POWER_USER_EXIT** is called in this function to allow the user to configure the hardware to exit low power mode. Macro **TX_LOW_POWER_USER_TIMER_ADJUST** is called in this function to determine how long the processor actually slept. ### Input parameters -- **none** +- *none* ### Return values -- **none** +- *none* ### Allowed from @@ -150,7 +332,7 @@ Internal ThreadX code, application ## tx_time_increment -This function increments the current time by a specified value. The value was derived by the application by calling the **tx_timer_get_next** function prior to this call, which was right before the processor was put in low power mode. +This function increments the current time by a specified value. The value was derived by the application by calling the ```tx_timer_get_next``` function prior to this call, which was right before the processor was put in low power mode. ### Prototype @@ -160,15 +342,15 @@ VOID tx_time_increment(ULONG time_increment); ### Description -This function increments the current time by a specified value. The value was derived by the application by calling the **tx_timer_get_next** function prior to this call, which was right before the processor was put in low power mode. +This function increments the current time by a specified value. The value was derived by the application by calling the ```tx_timer_get_next``` function prior to this call, which was right before the processor was put in low power mode. ### Input parameters -- **time_increment** Number of ThreadX ticks to increment time and timers. +- *time_increment* - Number of ThreadX ticks to increment time and timers. ### Return values -- **none** +- *none* ### Allowed from @@ -176,7 +358,7 @@ Internal ThreadX code, application ### Example -From **tx_low_power_exit**: +From ```tx_low_power_exit```: ```c /* Call the low-power timer driver code to obtain the amount of time (in ticks) @@ -213,16 +395,16 @@ ULONG tx_timer_get_next(ULONG *next_timer_tick_ptr); ### Description -This service gets the next ThreadX timer expiration, in ticks. +This service gets the next ThreadX timer expiration, in ticks. ### Input parameters -- **next_timer_tick_ptr** pointer to hold number of ticks +- *next_timer_tick_ptr* - pointer to hold number of ticks ### Return values -- **TX_TRUE** (1) At least one timer is active. -- **TX_FALSE** (0) No timers are currently active. +- *TX_TRUE* (1) At least one timer is active. +- *TX_FALSE* (0) No timers are currently active. ### Allowed from @@ -230,7 +412,7 @@ Internal ThreadX code, application ### Example -From **tx_low_power_enter**: +From ```tx_low_power_enter```: ```c ULONG tx_low_power_next_expiration; /* The next timer expiration (units of ThreadX timer ticks). */ diff --git a/utility/rtos_compatibility_layers/FreeRTOS/tx_freertos.c b/utility/rtos_compatibility_layers/FreeRTOS/tx_freertos.c index ee617a59d..9882b6546 100644 --- a/utility/rtos_compatibility_layers/FreeRTOS/tx_freertos.c +++ b/utility/rtos_compatibility_layers/FreeRTOS/tx_freertos.c @@ -29,10 +29,15 @@ /* 01-31-2022 William E. Lamie Modified comment(s), and */ /* fixed compiler warnings, */ /* resulting in version 6.1.10 */ +/* 07-29-2022 Cindy Deng Added simple static scheduler */ +/* start flag, corrected stack */ +/* allocation size, */ +/* resulting in version 6.1.12 */ /* */ /**************************************************************************/ #include +#include #include #include @@ -63,6 +68,7 @@ static TX_BYTE_POOL txfr_heap; static UINT txfr_heap_initialized; #if (TX_FREERTOS_AUTO_INIT == 1) static UINT txfr_initialized; +static UINT txfr_scheduler_started; #endif // #if (TX_FREERTOS_AUTO_INIT == 1) // TODO - do something with malloc. @@ -263,6 +269,7 @@ void vPortExitCritical(void) void vTaskStartScheduler(void) { #if (TX_FREERTOS_AUTO_INIT == 1) + txfr_scheduler_started = 1u; _tx_thread_schedule(); #else // Nothing to do, THREADX scheduler is already started. @@ -272,6 +279,11 @@ void vTaskStartScheduler(void) BaseType_t xTaskGetSchedulerState(void) { +#if (TX_FREERTOS_AUTO_INIT == 1) + if(txfr_scheduler_started == 0u) { + return taskSCHEDULER_NOT_STARTED; + } +#endif if(_tx_thread_preempt_disable > 0u) { return taskSCHEDULER_SUSPENDED; } else { @@ -315,6 +327,7 @@ TaskHandle_t xTaskCreateStatic(TaskFunction_t pxTaskCode, { UINT prio; UINT ret; + ULONG stack_depth_bytes; TX_INTERRUPT_SAVE_AREA; configASSERT(pxTaskCode != NULL); @@ -329,6 +342,13 @@ TaskHandle_t xTaskCreateStatic(TaskFunction_t pxTaskCode, } #endif + if(ulStackDepth > (ULONG_MAX / sizeof(StackType_t))) { + /* Integer overflow in stack depth */ + TX_FREERTOS_ASSERT_FAIL(); + return NULL; + } + stack_depth_bytes = ulStackDepth * sizeof(StackType_t); + TX_MEMSET(pxTaskBuffer, 0, sizeof(*pxTaskBuffer)); pxTaskBuffer->p_task_arg = pvParameters; pxTaskBuffer->p_task_func = pxTaskCode; @@ -342,7 +362,7 @@ TaskHandle_t xTaskCreateStatic(TaskFunction_t pxTaskCode, prio = txfr_prio_fr_to_tx(uxPriority); ret = tx_thread_create(&pxTaskBuffer->thread, (CHAR *)pcName, txfr_thread_wrapper, (ULONG)pvParameters, - puxStackBuffer, ulStackDepth, prio, prio, 0u, TX_DONT_START); + puxStackBuffer, stack_depth_bytes, prio, prio, 0u, TX_DONT_START); if(ret != TX_SUCCESS) { TX_FREERTOS_ASSERT_FAIL(); return NULL; @@ -375,6 +395,7 @@ BaseType_t xTaskCreate(TaskFunction_t pvTaskCode, txfr_task_t *p_task; UINT ret; UINT prio; + ULONG stack_depth_bytes; TX_INTERRUPT_SAVE_AREA; configASSERT(pvTaskCode != NULL); @@ -387,8 +408,14 @@ BaseType_t xTaskCreate(TaskFunction_t pvTaskCode, tx_freertos_auto_init(); } #endif + if((usStackDepth > (SIZE_MAX / sizeof(StackType_t))) + || (usStackDepth > (ULONG_MAX / sizeof(StackType_t)))) { + /* Integer overflow in stack depth */ + return errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + stack_depth_bytes = usStackDepth * sizeof(StackType_t); - p_stack = txfr_malloc(usStackDepth); + p_stack = txfr_malloc((size_t)stack_depth_bytes); if(p_stack == NULL) { return errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; } @@ -417,7 +444,7 @@ BaseType_t xTaskCreate(TaskFunction_t pvTaskCode, prio = txfr_prio_fr_to_tx(uxPriority); ret = tx_thread_create(&p_task->thread, (CHAR *)pcName, txfr_thread_wrapper, (ULONG)pvParameters, - p_stack, usStackDepth, prio, prio, 0u, TX_DONT_START); + p_stack, stack_depth_bytes, prio, prio, 0u, TX_DONT_START); if(ret != TX_SUCCESS) { (void)tx_semaphore_delete(&p_task->notification_sem); txfr_free(p_stack);