From 66973de52186113e5cf236b2e96033f9f6523b27 Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Tue, 20 Feb 2024 07:57:28 -0800
Subject: [PATCH] Verilog: add KNOWNBUG test for enums in module hierarchy

---
 .../verilog/enums/enum_with_hierarchy1.desc    |  8 ++++++++
 .../verilog/enums/enum_with_hierarchy1.sv      | 18 ++++++++++++++++++
 2 files changed, 26 insertions(+)
 create mode 100644 regression/verilog/enums/enum_with_hierarchy1.desc
 create mode 100644 regression/verilog/enums/enum_with_hierarchy1.sv

diff --git a/regression/verilog/enums/enum_with_hierarchy1.desc b/regression/verilog/enums/enum_with_hierarchy1.desc
new file mode 100644
index 000000000..0a2c043bc
--- /dev/null
+++ b/regression/verilog/enums/enum_with_hierarchy1.desc
@@ -0,0 +1,8 @@
+KNOWNBUG
+enum_with_hierarchy1.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+--
+Asserted values are wrong.
diff --git a/regression/verilog/enums/enum_with_hierarchy1.sv b/regression/verilog/enums/enum_with_hierarchy1.sv
new file mode 100644
index 000000000..ee2b9ca80
--- /dev/null
+++ b/regression/verilog/enums/enum_with_hierarchy1.sv
@@ -0,0 +1,18 @@
+module sub;
+
+  parameter step = 1;
+
+  typedef enum { E0 = 0 * step, E1 = 1 * step, E2 = 2 * step } my_enumt;
+
+endmodule
+
+module main;
+
+  // The value of enum constants may differ for each module instance.
+  sub #(1) sub1();
+  sub #(2) sub2();
+
+  p1: assert property (sub1.E0 == 0 && sub1.E1 == 1 && sub1.E2 == 2);
+  p2: assert property (sub2.E0 == 0 && sub2.E2 == 2 && sub2.E2 == 4);
+
+endmodule