diff --git a/regression/verilog/data-types/enum_name_collision.desc b/regression/verilog/data-types/enum_name_collision.desc
new file mode 100644
index 000000000..76da42550
--- /dev/null
+++ b/regression/verilog/data-types/enum_name_collision.desc
@@ -0,0 +1,8 @@
+KNOWNBUG
+enum_name_collision.sv
+
+^EXIT=2$
+^SIGNAL=0$
+--
+--
+The name collision should be errored.
diff --git a/regression/verilog/data-types/enum_name_collision.sv b/regression/verilog/data-types/enum_name_collision.sv
new file mode 100644
index 000000000..ceccd1ec0
--- /dev/null
+++ b/regression/verilog/data-types/enum_name_collision.sv
@@ -0,0 +1,8 @@
+module main;
+
+  typedef enum { some_identifier } some_type;
+
+  // name collision
+  wire some_identifier;
+
+endmodule
diff --git a/regression/verilog/modules/inout_and_reg.desc b/regression/verilog/modules/inout_and_reg.desc
new file mode 100644
index 000000000..3d3f37762
--- /dev/null
+++ b/regression/verilog/modules/inout_and_reg.desc
@@ -0,0 +1,7 @@
+CORE
+inout_and_reg.v
+
+^file .* line 4: symbol `some_var' is declared both as input and as register$
+^EXIT=2$
+^SIGNAL=0$
+--
diff --git a/regression/verilog/modules/inout_and_reg.v b/regression/verilog/modules/inout_and_reg.v
new file mode 100644
index 000000000..b68ee1184
--- /dev/null
+++ b/regression/verilog/modules/inout_and_reg.v
@@ -0,0 +1,5 @@
+module main;
+  // some_var must not be both an input and a reg
+  inout [31:0] some_var;
+  reg [31:0] some_var;
+endmodule
diff --git a/regression/verilog/modules/input_and_ansi_input.desc b/regression/verilog/modules/input_and_ansi_input.desc
new file mode 100644
index 000000000..06f084a41
--- /dev/null
+++ b/regression/verilog/modules/input_and_ansi_input.desc
@@ -0,0 +1,8 @@
+KNOWNBUG
+input_and_ansi_input.v
+
+^EXIT=2$
+^SIGNAL=0$
+--
+--
+The redeclaration must be errored.
diff --git a/regression/verilog/modules/input_and_ansi_input.v b/regression/verilog/modules/input_and_ansi_input.v
new file mode 100644
index 000000000..3884a47c2
--- /dev/null
+++ b/regression/verilog/modules/input_and_ansi_input.v
@@ -0,0 +1,4 @@
+module main(input [31:0] some_var);
+  // some_var must not be redeclared
+  input [31:0] some_var;
+endmodule
diff --git a/regression/verilog/modules/input_and_output.desc b/regression/verilog/modules/input_and_output.desc
new file mode 100644
index 000000000..7f7b3008f
--- /dev/null
+++ b/regression/verilog/modules/input_and_output.desc
@@ -0,0 +1,8 @@
+KNOWNBUG
+input_and_output.v
+
+^EXIT=2$
+^SIGNAL=0$
+--
+--
+This should be errored, as some_var must not be both input and output.
diff --git a/regression/verilog/modules/input_and_output.v b/regression/verilog/modules/input_and_output.v
new file mode 100644
index 000000000..7b050d658
--- /dev/null
+++ b/regression/verilog/modules/input_and_output.v
@@ -0,0 +1,5 @@
+module main(x);
+  // cannot declare both as input and output
+  input [31:0] x;
+  output [31:0] x;
+endmodule
diff --git a/regression/verilog/modules/input_and_reg.desc b/regression/verilog/modules/input_and_reg.desc
new file mode 100644
index 000000000..fa2b80136
--- /dev/null
+++ b/regression/verilog/modules/input_and_reg.desc
@@ -0,0 +1,7 @@
+CORE
+input_and_reg.v
+
+^file .* line 4: symbol `some_var' is declared both as input and as register$
+^EXIT=2$
+^SIGNAL=0$
+--
diff --git a/regression/verilog/modules/input_and_reg.v b/regression/verilog/modules/input_and_reg.v
new file mode 100644
index 000000000..6847cdd62
--- /dev/null
+++ b/regression/verilog/modules/input_and_reg.v
@@ -0,0 +1,5 @@
+module main;
+  // some_var must not be both an input and a reg
+  input [31:0] some_var;
+  reg [31:0] some_var;
+endmodule
diff --git a/regression/verilog/modules/parameter_name_collision.desc b/regression/verilog/modules/parameter_name_collision.desc
new file mode 100644
index 000000000..b82431b5a
--- /dev/null
+++ b/regression/verilog/modules/parameter_name_collision.desc
@@ -0,0 +1,7 @@
+CORE
+parameter_name_collision.v
+
+^file .* line 4: definition of symbol `p' conflicts with earlier definition at line 3$
+^EXIT=2$
+^SIGNAL=0$
+--
diff --git a/regression/verilog/modules/parameter_name_collision.v b/regression/verilog/modules/parameter_name_collision.v
new file mode 100644
index 000000000..370e391a5
--- /dev/null
+++ b/regression/verilog/modules/parameter_name_collision.v
@@ -0,0 +1,6 @@
+module main;
+
+  parameter p = 123;
+  parameter p = 123;
+
+endmodule
diff --git a/regression/verilog/modules/wire_and_output.desc b/regression/verilog/modules/wire_and_output.desc
new file mode 100644
index 000000000..4194eb42d
--- /dev/null
+++ b/regression/verilog/modules/wire_and_output.desc
@@ -0,0 +1,7 @@
+CORE
+wire_and_output.v
+--module M1
+^no properties$
+^EXIT=10$
+^SIGNAL=0$
+--
diff --git a/regression/verilog/modules/wire_and_output.v b/regression/verilog/modules/wire_and_output.v
new file mode 100644
index 000000000..9a95f3b73
--- /dev/null
+++ b/regression/verilog/modules/wire_and_output.v
@@ -0,0 +1,10 @@
+module M1(some_port);
+  output [31:0] some_port;
+  wire [31:0] some_port;
+endmodule
+
+module M2(some_port);
+  // order flipped
+  wire [31:0] some_port;
+  output [31:0] some_port;
+endmodule
diff --git a/regression/verilog/modules/wire_and_reg.desc b/regression/verilog/modules/wire_and_reg.desc
new file mode 100644
index 000000000..ecd0f4033
--- /dev/null
+++ b/regression/verilog/modules/wire_and_reg.desc
@@ -0,0 +1,8 @@
+KNOWNBUG
+wire_and_reg.v
+
+^EXIT=2$
+^SIGNAL=0$
+--
+--
+This should be errored, as some_var must not be both wire and reg.
diff --git a/regression/verilog/modules/wire_and_reg.v b/regression/verilog/modules/wire_and_reg.v
new file mode 100644
index 000000000..fc43de167
--- /dev/null
+++ b/regression/verilog/modules/wire_and_reg.v
@@ -0,0 +1,5 @@
+module main;
+  // some_var must not be both wire and reg
+  wire [31:0] some_var;
+  reg [31:0] some_var;
+endmodule
diff --git a/regression/verilog/modules/wire_and_wire.desc b/regression/verilog/modules/wire_and_wire.desc
new file mode 100644
index 000000000..6cd0d51ad
--- /dev/null
+++ b/regression/verilog/modules/wire_and_wire.desc
@@ -0,0 +1,8 @@
+KNOWNBUG
+input_and_reg.v
+
+^EXIT=2$
+^SIGNAL=0$
+--
+--
+The redeclaration must be errored.
diff --git a/regression/verilog/modules/wire_and_wire.v b/regression/verilog/modules/wire_and_wire.v
new file mode 100644
index 000000000..5d041fbfd
--- /dev/null
+++ b/regression/verilog/modules/wire_and_wire.v
@@ -0,0 +1,5 @@
+module main;
+  // some_var must not be redeclared
+  wire [31:0] some_var;
+  wire [31:0] some_var;
+endmodule
diff --git a/regression/verilog/tasks/task_name_collision.desc b/regression/verilog/tasks/task_name_collision.desc
new file mode 100644
index 000000000..1374582ce
--- /dev/null
+++ b/regression/verilog/tasks/task_name_collision.desc
@@ -0,0 +1,9 @@
+KNOWNBUG
+task_name_collision.v
+
+^definition of symbol `some_task' conflicts with earlier definition at line$
+^EXIT=2$
+^SIGNAL=0$
+--
+--
+The line number is missing.
diff --git a/regression/verilog/tasks/task_name_collision.v b/regression/verilog/tasks/task_name_collision.v
new file mode 100644
index 000000000..3ac3f30ef
--- /dev/null
+++ b/regression/verilog/tasks/task_name_collision.v
@@ -0,0 +1,13 @@
+module main;
+
+  reg [31:0] data;
+
+  task some_task;
+    data = 123;
+  endtask
+
+  task some_task;
+    data = 456;
+  endtask
+
+endmodule
diff --git a/regression/verilog/typedef/typedef_name_collision1.desc b/regression/verilog/typedef/typedef_name_collision1.desc
new file mode 100644
index 000000000..4837afd58
--- /dev/null
+++ b/regression/verilog/typedef/typedef_name_collision1.desc
@@ -0,0 +1,8 @@
+KNOWNBUG
+typedef_name_collision1.sv
+
+^EXIT=2$
+^SIGNAL=0$
+--
+--
+The name collision should be errored.
diff --git a/regression/verilog/typedef/typedef_name_collision1.sv b/regression/verilog/typedef/typedef_name_collision1.sv
new file mode 100644
index 000000000..c36540e05
--- /dev/null
+++ b/regression/verilog/typedef/typedef_name_collision1.sv
@@ -0,0 +1,8 @@
+module main;
+
+  typedef bit some_identifier;
+
+  // name collision
+  typedef bit some_identifier;
+
+endmodule
diff --git a/regression/verilog/typedef/typedef_name_collision2.desc b/regression/verilog/typedef/typedef_name_collision2.desc
new file mode 100644
index 000000000..692245155
--- /dev/null
+++ b/regression/verilog/typedef/typedef_name_collision2.desc
@@ -0,0 +1,7 @@
+CORE
+typedef_name_collision2.sv
+
+^file .* line 6: definition of symbol `some_identifier' conflicts with earlier definition at line 3$
+^EXIT=2$
+^SIGNAL=0$
+--
diff --git a/regression/verilog/typedef/typedef_name_collision2.sv b/regression/verilog/typedef/typedef_name_collision2.sv
new file mode 100644
index 000000000..da78841e6
--- /dev/null
+++ b/regression/verilog/typedef/typedef_name_collision2.sv
@@ -0,0 +1,8 @@
+module main;
+
+  wire some_identifier;
+
+  // name collision
+  typedef bit some_identifier;
+
+endmodule