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[linux-6.6.y] x86/mce: Add Centaur MCA support #254

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merged 1 commit into from
Jun 14, 2024
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[linux-6.6.y] x86/mce: Add Centaur MCA support #254

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29 changes: 9 additions & 20 deletions arch/x86/kernel/cpu/mce/core.c
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Original file line number Diff line number Diff line change
Expand Up @@ -482,6 +482,7 @@ int mce_usable_address(struct mce *m)

/* Checks after this one are Intel/Zhaoxin-specific: */
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR &&
boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
return 1;

Expand All @@ -506,6 +507,7 @@ bool mce_is_memory_error(struct mce *m)
return amd_mce_is_memory_error(m);

case X86_VENDOR_INTEL:
case X86_VENDOR_CENTAUR:
case X86_VENDOR_ZHAOXIN:
/*
* Intel SDM Volume 3B - 15.9.2 Compound Error Codes
Expand Down Expand Up @@ -1231,7 +1233,8 @@ static noinstr bool mce_check_crashing_cpu(void)

mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS);

if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR ||
boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
if (mcgstatus & MCG_STATUS_LMCES)
return false;
}
Expand Down Expand Up @@ -1505,6 +1508,7 @@ noinstr void do_machine_check(struct pt_regs *regs)
* on Intel, Zhaoxin only.
*/
if (m.cpuvendor == X86_VENDOR_INTEL ||
m.cpuvendor == X86_VENDOR_CENTAUR ||
m.cpuvendor == X86_VENDOR_ZHAOXIN)
lmce = m.mcgstatus & MCG_STATUS_LMCES;

Expand Down Expand Up @@ -1932,7 +1936,8 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
mce_flags.skx_repmov_quirk = 1;
}

if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
if (c->x86_vendor == X86_VENDOR_CENTAUR ||
c->x86_vendor == X86_VENDOR_ZHAOXIN) {
/*
* All newer Zhaoxin CPUs support MCE broadcasting. Enable
* synchronization with a one second timeout.
Expand Down Expand Up @@ -1985,21 +1990,6 @@ static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
}
}

static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
{
struct mca_config *cfg = &mca_cfg;

/*
* All newer Centaur CPUs support MCE broadcasting. Enable
* synchronization with a one second timeout.
*/
if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
c->x86 > 6) {
if (cfg->monarch_timeout < 0)
cfg->monarch_timeout = USEC_PER_SEC;
}
}

static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
{
struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
Expand Down Expand Up @@ -2047,9 +2037,6 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
break;

case X86_VENDOR_CENTAUR:
mce_centaur_feature_init(c);
break;

case X86_VENDOR_ZHAOXIN:
mce_zhaoxin_feature_init(c);
break;
Expand All @@ -2066,6 +2053,7 @@ static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
mce_intel_feature_clear(c);
break;

case X86_VENDOR_CENTAUR:
case X86_VENDOR_ZHAOXIN:
mce_zhaoxin_feature_clear(c);
break;
Expand Down Expand Up @@ -2351,6 +2339,7 @@ static void vendor_disable_error_reporting(void)
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR ||
boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN)
return;

Expand Down
1 change: 1 addition & 0 deletions arch/x86/kernel/cpu/mce/intel.c
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Original file line number Diff line number Diff line change
Expand Up @@ -93,6 +93,7 @@ static int cmci_supported(int *banks)
* makes sure none of the backdoors are entered otherwise.
*/
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR &&
boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
return 0;

Expand Down
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