diff --git a/README.md b/README.md
index a5e73aad..b412faaf 100644
--- a/README.md
+++ b/README.md
@@ -1,446 +1,27 @@
+[![Review Assignment Due Date](https://classroom.github.com/assets/deadline-readme-button-24ddc0f5d75046c5622901739e7c5dd533143b0c8e959d652212380cedb1ea36.svg)](https://classroom.github.com/a/pelSJLGu)
 # Catalog of Verilog Components to Build and Simulate a MIPS-based RISC.
 
 This work is based off the MIPS Verilog code by [Harris and Harris](https://pages.hmc.edu/harris/ddca/ddca2e.html)
 
 The basis of the single cycle computer as provided by these Verilog components:
 
-```verilog
-// mips.sv
-// From Section 7.6 of Digital Design & Computer Architecture
-// Updated to SystemVerilog 26 July 2011 David_Harris@hmc.edu
-`timescale 1ms/100us // 1ms period, 100us precision
+This processor is single-cycled with 32-bit words and byte addressable memory. The datapath components include a program counter, a memory split into data and 
+instruction memory, a regfile of 32 registers,, an ALU, a sign extender for immediate values, a maindecoder, an ALU decoder, several MUXes, and 2 adders. The main decoder and ALU decoder together form the controller, which turns on and off the other components in the data path to execute certain actions depending on the 
+input instruction. 
 
-module mips_single_cycle_tb();
-
-  logic        clk;
-  logic        reset;
-
-  logic [31:0] writedata, dataadr;
-  logic        memwrite;
-
-  logic firstTest, secondTest;
-
-  // instantiate device to be tested
-  top dut(clk, reset, writedata, dataadr, memwrite);
-
-  initial
-  begin
-      firstTest = 1'b0;
-      secondTest = 1'b0;
-      $dumpfile("mips_single_cycle_test.vcd");
-      $dumpvars(0,clk,reset,writedata,dataadr,memwrite);
-      // $display("writedata\tdataadr\tmemwrite");
-      $monitor("0x%7h\t%7d\t%8d",writedata,dataadr,memwrite);
-      // $dumpvars(0,clk,a,b,ctrl,result,zero,negative,carryOut,overflow);
-      // $display("Ctl Z  N  O  C  A                    B                    ALUresult");
-      // $monitor("%3b %b  %b  %b  %b  %8b (0x%2h;%3d)  %8b (0x%2h;%3d)  %8b (0x%2h;%3d)",ctrl,zero,negative,overflow,carryOut,a,a,a,b,b,b,result,result,result);
-  end
-
-  // initialize test
-  initial
-    begin
-      reset <= 1; # 22; reset <= 0;
-    end
-
-  // generate clock to sequence tests
-  always
-    begin
-      clk <= 1; # 5; clk <= 0; # 5;
-    end
-
-  always @(posedge clk)
-  begin
-      $display("+");
-      $display("\t+instr = 0x%8h",dut.instr);
-      $display("\t+op = 0b%6b",dut.mips.c.op);
-      $display("\t+controls = 0b%9b",dut.mips.c.md.controls);
-      $display("\t+funct = 0b%6b",dut.mips.c.ad.funct);
-      $display("\t+aluop = 0b%2b",dut.mips.c.ad.aluop);
-      $display("\t+alucontrol = 0b%3b",dut.mips.c.ad.alucontrol);
-      $display("\t+alu result = 0x%8h",dut.mips.dp.alu.result);
-      $display("\t+HiLo = 0x%8h",dut.mips.dp.alu.HiLo);
-      $display("\t+$v0 = 0x%4h",dut.mips.dp.rf.rf[2]);
-      $display("\t+$v1 = 0x%4h",dut.mips.dp.rf.rf[3]);
-      $display("\t+$a0 = 0x%4h",dut.mips.dp.rf.rf[4]);
-      $display("\t+$a1 = 0x%4h",dut.mips.dp.rf.rf[5]);
-      $display("\t+$t0 = 0x%4h",dut.mips.dp.rf.rf[8]);
-      $display("\t+$t1 = 0x%4h",dut.mips.dp.rf.rf[9]);
-      $display("\t+regfile -- ra1 = %d",dut.mips.dp.rf.ra1);
-      $display("\t+regfile -- ra2 = %d",dut.mips.dp.rf.ra2);
-      $display("\t+regfile -- we3 = %d",dut.mips.dp.rf.we3);
-      $display("\t+regfile -- wa3 = %d",dut.mips.dp.rf.wa3);
-      $display("\t+regfile -- wd3 = %d",dut.mips.dp.rf.wd3);
-      $display("\t+regfile -- rd1 = %d",dut.mips.dp.rf.rd1);
-      $display("\t+regfile -- rd2 = %d",dut.mips.dp.rf.rd2);
-      $display("\t+RAM[%4d] = %4d",dut.dmem.a,dut.dmem.rd);
-      $display("writedata\tdataadr\tmemwrite");
-  end
-
-  // check results
-  always @(negedge clk)
-    begin
-      $display("-");
-      $display("\t-instr = 0x%8h",dut.instr);
-      $display("\t-op = 0b%6b",dut.mips.c.op);
-      $display("\t-controls = 0b%9b",dut.mips.c.md.controls);
-      $display("\t-funct = 0b%6b",dut.mips.c.ad.funct);
-      $display("\t-aluop = 0b%2b",dut.mips.c.ad.aluop);
-      $display("\t-alucontrol = 0b%3b",dut.mips.c.ad.alucontrol);
-      $display("\t-alu result = 0x%8h",dut.mips.dp.alu.result);
-      $display("\t-HiLo = 0x%8h",dut.mips.dp.alu.HiLo);
-      $display("\t-$v0 = 0x%4h",dut.mips.dp.rf.rf[2]);
-      $display("\t-$v1 = 0x%4h",dut.mips.dp.rf.rf[3]);
-      $display("\t-$a0 = 0x%4h",dut.mips.dp.rf.rf[4]);
-      $display("\t-$a1 = 0x%4h",dut.mips.dp.rf.rf[5]);
-      $display("\t-$t0 = 0x%4h",dut.mips.dp.rf.rf[8]);
-      $display("\t-$t1 = 0x%4h",dut.mips.dp.rf.rf[9]);
-      $display("\t-regfile -- ra1 = %d",dut.mips.dp.rf.ra1);
-      $display("\t-regfile -- ra2 = %d",dut.mips.dp.rf.ra2);
-      $display("\t-regfile -- we3 = %d",dut.mips.dp.rf.we3);
-      $display("\t-regfile -- wa3 = %d",dut.mips.dp.rf.wa3);
-      $display("\t-regfile -- wd3 = %d",dut.mips.dp.rf.wd3);
-      $display("\t-regfile -- rd1 = %d",dut.mips.dp.rf.rd1);
-      $display("\t-regfile -- rd2 = %d",dut.mips.dp.rf.rd2);
-      $display("\t+RAM[%4d] = %4d",dut.dmem.a,dut.dmem.rd);
-      $display("writedata\tdataadr\tmemwrite");
-      if (dut.dmem.RAM[84] === 32'h9504)
-        begin
-          $display("Successfully wrote 0x%4h at RAM[%3d]",84,32'h9504);
-          firstTest = 1'b1;
-        end
-      if (dut.dmem.RAM[88] === 0)
-        begin
-          $display("Successfully wrote 0x%4h at RAM[%3d]",88,0);
-          secondTest = 1'b1;
-        end
-      if(memwrite) begin
-        if(dataadr === 84 & writedata === 32'h9504)
-        begin
-          $display("Successfully wrote 0x%4h at RAM[%3d]",writedata,dataadr);
-          firstTest = 1'b1;
-        end
-        if(dataadr === 88 & writedata === 0)
-        begin
-          $display("Successfully wrote 0x%4h at RAM[%3d]",writedata,dataadr);
-          secondTest = 1'b1;
-        //if(dataadr === 60 & writedata === 28) begin
-            // $display("Simulation succeeded");
-            // $finish;
-          // end
-        end
-        // else if (dataadr !== 80) begin
-        //   $display("Simulation failed");
-        //   $finish;
-        // end
-      end
-      if (firstTest === 1'b1 & secondTest === 1'b1)
-      begin
-          $display("Program successfully completed");
-          $finish;
-      end
-      // else
-      // begin
-      //     $display("Program UNsuccessfully completed");
-      //     $finish;
-      // end
-    end
-endmodule
-
-module top(input  logic        clk, reset,
-           output logic [31:0] writedata, dataadr,
-           output logic        memwrite);
-
-  logic [31:0] pc, instr, readdata;
-
-  // instantiate processor and memories
-  mips mips(clk, reset, pc, instr, memwrite, dataadr,
-            writedata, readdata);
-  imem imem(pc[7:2], instr);
-  dmem dmem(clk, memwrite, dataadr, writedata, readdata);
-endmodule
-
-module dmem(input  logic        clk, we,
-            input  logic [31:0] a, wd,
-            output logic [31:0] rd);
-
-  logic [31:0] RAM[0:63];
-
-  assign rd = RAM[a[31:2]]; // word aligned
-
-  always @(posedge clk)
-    if (we) RAM[a[31:2]] <= wd;
-endmodule
-
-module imem(input  logic [5:0] a,
-            output logic [31:0] rd);
-
-  logic [31:0] RAM[0:63];
-
-  initial
-    begin
-      // read memory in hex format from file
-      $readmemh("memfile.dat",RAM);
-    end
-
-  assign rd = RAM[a]; // word aligned
-endmodule
-
-module mips(input  logic        clk, reset,
-            output logic [31:0] pc,
-            input  logic [31:0] instr,
-            output logic        memwrite,
-            output logic [31:0] aluout, writedata,
-            input  logic [31:0] readdata);
-
-  logic       memtoreg, alusrc, regdst,
-              regwrite, jump, pcsrc, zero;
-  logic [2:0] alucontrol;
-
-  controller c(instr[31:26], instr[5:0], zero,
-               memtoreg, memwrite, pcsrc,
-               alusrc, regdst, regwrite, jump,
-               alucontrol);
-  datapath dp(clk, reset, memtoreg, pcsrc,
-              alusrc, regdst, regwrite, jump,
-              alucontrol,
-              zero, pc, instr,
-              aluout, writedata, readdata);
-endmodule
-
-module controller(input  logic [5:0] op, funct,
-                  input  logic       zero,
-                  output logic       memtoreg, memwrite,
-                  output logic       pcsrc, alusrc,
-                  output logic       regdst, regwrite,
-                  output logic       jump,
-                  output logic [2:0] alucontrol);
-
-  logic [1:0] aluop;
-  logic       branch;
-
-  maindec md(op, memtoreg, memwrite, branch,
-             alusrc, regdst, regwrite, jump, aluop);
-  aludec  ad(funct, aluop, alucontrol);
-
-  assign pcsrc = branch & zero;
-endmodule
-
-module maindec(input  logic [5:0] op,
-               output logic       memtoreg, memwrite,
-               output logic       branch, alusrc,
-               output logic       regdst, regwrite,
-               output logic       jump,
-               output logic [1:0] aluop);
-
-  logic [8:0] controls;
-
-  assign {regwrite, regdst, alusrc, branch, memwrite,
-          memtoreg, jump, aluop} = controls; // controls has 9 logical signals
-
-  always @*
-    case(op)
-      6'b000000: controls <= 9'b110000010; // RTYPE
-      6'b100011: controls <= 9'b101001000; // LW
-      6'b101011: controls <= 9'b001010000; // SW
-      6'b000100: controls <= 9'b000100001; // BEQ
-      6'b001000: controls <= 9'b101000000; // ADDI
-      6'b000010: controls <= 9'b000000100; // J
-      default:   controls <= 9'bxxxxxxxxx; // illegal op
-    endcase
-endmodule
-
-module aludec(input  logic [5:0] funct,
-              input  logic [1:0] aluop,
-              output logic [2:0] alucontrol);
-
-  always @*
-    case(aluop)
-      2'b00: alucontrol <= 3'b010;  // add (for lw/sw/addi)
-      2'b01: alucontrol <= 3'b110;  // sub (for beq)
-      default: case(funct)          // R-type instructions]
-          6'b100000: alucontrol <= 3'b010; // add
-          6'b100010: alucontrol <= 3'b110; // sub
-          6'b100100: alucontrol <= 3'b000; // and
-          6'b100101: alucontrol <= 3'b001; // or
-          6'b101010: alucontrol <= 3'b111; // slt
-          6'b011000: alucontrol <= 3'b011; // mult
-          6'b010010: alucontrol <= 3'b100; // mflo
-          6'b010000: alucontrol <= 3'b101; // mfhi
-          default:   alucontrol <= 3'bxxx; // ???
-        endcase
-    endcase
-endmodule
-
-//
-// 000
-// 001
-// 010
-// 011 - available - use for mult
-// 100 - available - use for mfhi
-// 101 - available - use for mflo
-// 110
-// 111
-
-module datapath(input  logic        clk, reset,
-                input  logic        memtoreg, pcsrc,
-                input  logic        alusrc, regdst,
-                input  logic        regwrite, jump,
-                input  logic [2:0]  alucontrol,
-                output logic        zero,
-                output logic [31:0] pc,
-                input  logic [31:0] instr,
-                output logic [31:0] aluout, writedata,
-                input  logic [31:0] readdata);
-
-  logic [4:0]  writereg;
-  logic [31:0] pcnext, pcnextbr, pcplus4, pcbranch;
-  logic [31:0] signimm, signimmsh;
-  logic [31:0] srca, srcb;
-  logic [31:0] result;
-
-  // next PC logic
-  flopr #(32) pcreg(clk, reset, pcnext, pc);
-  adder       pcadd1(pc, 32'b100, pcplus4);
-  sl2         immsh(signimm, signimmsh);
-  adder       pcadd2(pcplus4, signimmsh, pcbranch);
-  mux2 #(32)  pcbrmux(pcplus4, pcbranch, pcsrc, pcnextbr);
-  mux2 #(32)  pcmux(pcnextbr, {pcplus4[31:28], instr[25:0], 2'b00}, jump, pcnext);
-
-  // register file logic
-  regfile     rf(clk, regwrite, instr[25:21], instr[20:16],
-                 writereg, result, srca, writedata);
-  mux2 #(5)   wrmux(instr[20:16], instr[15:11],
-                    regdst, writereg);
-  mux2 #(32)  resmux(aluout, readdata, memtoreg, result);
-  signext     se(instr[15:0], signimm);
-
-  // ALU logic
-  mux2 #(32)  srcbmux(writedata, signimm, alusrc, srcb);
-  alu         alu(clk, srca, srcb, alucontrol, aluout, zero);
-endmodule
-
-module regfile(input  logic        clk,
-               input  logic        we3,
-               input  logic [4:0]  ra1, ra2, wa3,
-               input  logic [31:0] wd3,
-               output logic [31:0] rd1, rd2);
-
-  logic [31:0] rf[31:0];
-
-  // three ported register file
-  // read two ports combinationally
-  // write third port on rising edge of clk
-  // register 0 hardwired to 0
-  // note: for pipelined processor, write third port
-  // on falling edge of clk
-
-  always @(posedge clk)
-    if (we3) rf[wa3] <= wd3;
-
-  assign rd1 = (ra1 != 0) ? rf[ra1] : 0;
-  assign rd2 = (ra2 != 0) ? rf[ra2] : 0;
-endmodule
-
-module adder(input  logic [31:0] a, b,
-             output logic [31:0] y);
-
-  assign y = a + b;
-endmodule
-
-module sl2(input  logic [31:0] a,
-           output logic [31:0] y);
-
-  // shift left by 2
-  assign y = {a[29:0], 2'b00};
-endmodule
-
-module signext(input  logic [15:0] a,
-               output logic [31:0] y);
-
-  assign y = {{16{a[15]}}, a};
-endmodule
-
-module flopr #(parameter WIDTH = 8)
-              (input  logic             clk, reset,
-               input  logic [WIDTH-1:0] d,
-               output logic [WIDTH-1:0] q);
-
-  always @(posedge clk, posedge reset)
-    if (reset) q <= 0;
-    else       q <= d;
-endmodule
-
-module mux2 #(parameter WIDTH = 8)
-             (input  logic [WIDTH-1:0] d0, d1,
-              input  logic             s,
-              output logic [WIDTH-1:0] y);
-
-  assign y = s ? d1 : d0;
-endmodule
-
-module alu(input  logic clk,
-           input  logic [31:0] a, b,
-           input  logic [2:0]  alucontrol,
-           output logic [31:0] result,
-           output logic        zero);
-
-  logic [31:0] condinvb, sum;
-  logic [63:0] HiLo;
-
-  assign zero = (result == 32'b0);
-  assign condinvb = alucontrol[2] ? ~b : b;
-  assign sumSlt = a + condinvb + alucontrol[2];
-
-	initial
-		begin
-			HiLo = 64'b0;
-		end
-
-  always @(a,b,alucontrol)
-    begin
-      case (alucontrol)
-        3'b000: result = a & b; // and
-        3'b001: result = a | b; // or
-        3'b010: result = a + b; // add
-        3'b100: result = HiLo[31:0]; // MFLO
-        3'b101: result = HiLo[63:32]; // MFHI
-        3'b110: result = sumSlt; // sub
-        3'b111: result = sumSlt[31]; // slt
-      endcase
-    end
+To successfully demo, the mult-prog_exe file must be modified so that instructions, using our ISA, are hand compiled into machine code in hex and placed into the file. There can be no more than 64 instructions at a time due to instruction memory size limitations, and anything underneath that size should have the rest of the lines filled as 8 0s. In this case, there is a leaf and recursive demonstration (fibonacci) attached. To run the program, underneath the \catalog\computer directory, run:
+```
+make compile simulate
+```
+To view the timing diagram on GTKWave, run:
+```
+make display
+```
 
-    // case (alucontrol[1:0])
-    //   2'b00: result = a & b;
-    //   2'b01: result = a | b;
-    //   2'b10: result = sum;
-    //   2'b11: result = sum[31];
-    // endcase
+Note that the duration alotted in each of the programs vary, so in the tb_computer.sv file underneath \catalog\computer, underneath the "// initialize test" commend, change the number next to finish. In the two demos, the leaf code will run and finish with #90, and the fib code will run with #500.
 
-	// always @(posedge clk)
-	// 	begin
-  //     case (alucontrol)
-  //       3'b000: result = a & b; // and
-  //       3'b001: result = a | b; // or
-  //       3'b010: result = a + b; // add
-  //       3'b100: result = HiLo[31:0]; // MFLO
-  //       3'b101: result = HiLo[63:32]; // MFHI
-  //       3'b110: result = sumSlt; // sub
-  //       3'b111: result = sum[31]; // slt
-  //     endcase
-  //   end
+It should also be noted that we are aware that our last few lines of our fib code are sketchy, as we did not implement a stack pointer and function call in our assembly. We attempted to do so, but were unsuccessful. We believe that the issue lied somewhere in the fact that we were not utilizing the stack pointer, return address register, or the proper data path for a jal function. One of those (or a combination of those) resulted in $ra always being "don't care" values, and any time we attempted to load word to restore $s0, the register we were using to store the result of a function call, the value in $s0 would also become "don't care" values. The functions were iterating correctly, and the failed attempts with jal/implementation as function calls is attached.
 
-	//Multiply and divide results are only stored at clock falling edge.
-	always @(negedge clk)
-		begin
-      case (alucontrol)
-        3'b011: HiLo = a * b; // mult
-        3'b101: // div
-          begin
-            HiLo[31:0] = a / b;
-            HiLo[63:32] = a % b;
-          end
-      endcase
-		end
-endmodule
+Due to this error, instead, a non-function implementation was done for fib and our leaf code, and in the assembly, we are aware that without a stack pointer and function call system, we cannot quite save our resulting register into non-reserved or non-instruction memory space (we can only store up to 16 bits of an address, not 32, from our add immediate). So, we just wrote that we stored it into reserved space anyway, and the lw function that comes after is basically pointless. This was done just as a placeholder for storing it into the proper place in memory.
 
-```
+**Note: The attached timing diagram corresponds to the different type of instructions used in the attempted Leaf (stack pointer) procedure. In the working Fibonacci procedure, the different types of instructions are still applied. 
\ No newline at end of file
diff --git a/catalog/adder/adder.sv b/catalog/adder/adder.sv
index f087c643..71aa790d 100644
--- a/catalog/adder/adder.sv
+++ b/catalog/adder/adder.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Andrew Yuan and Zachary Hsieh
 // 
 //     Create Date: 2023-02-07
 //     Module Name: adder
@@ -20,11 +20,17 @@ module adder
     //
     // ---------------- PORT DEFINITIONS ----------------
     //
-
+    
+    input logic [n-1:0] a,
+    input logic [n-1:0] b,
+    output logic [n-1:0] y
 );
+
     //
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
+    assign y = a + b;
+
 
 endmodule
 
diff --git a/catalog/adder/tb_adder.sv b/catalog/adder/tb_adder.sv
index 0b9579f7..bde74441 100644
--- a/catalog/adder/tb_adder.sv
+++ b/catalog/adder/tb_adder.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Zachary Hsieh and Andrew Yuan
 // 
 //     Create Date: 2023-02-07
 //     Module Name: tb_adder
@@ -14,25 +14,34 @@
 `define TB_ADDER
 
 `timescale 1ns/100ps
-`include "adder.sv"
+`include "./adder.sv"
 
 module tb_adder;
-    parameter n = 32;
-    logic [(n-1):0] a, b, y;
-
-   initial begin
-        $dumpfile("adder.vcd");
-        $dumpvars(0, uut);
-        $monitor("a = 0x%0h b = 0x%0h y = 0x%0h", a, b, y);
-    end
-
-    initial begin
-        a <= #n'hFFFFFFFF;
-        b <= #n'hFFFFFFFF;
-    end
-
-    adder uut(
-        .A(a), .B(b), .Y(y)
-    );
+   parameter N = 32;
+
+   reg [N-1:0] A;
+   reg [N-1:0] B;   //inputs are reg for test bench
+
+   wire [N-1:0] Y;     //outputs are wire for test bench
+   
+   //
+   // ---------------- INITIALIZE TEST BENCH ----------------
+   //
+
+   //apply input vectors
+   initial begin: apply_stimulus
+   A = 32'b00110101100100111001111111000000;
+   B = 32'b10101111010000000101010001011001;
+   $display("A=%b B=%b Y=%b\n", A, B, Y);
+      $finish;
+   end
+
+
+   //
+   // ---------------- INSTANTIATE UNIT UNDER TEST (UUT) ----------------
+   //
+   adder uut(.a(A), .b(B), .y(Y));
+
 endmodule
+
 `endif // TB_ADDER
\ No newline at end of file
diff --git a/catalog/alu/alu.sv b/catalog/alu/alu.sv
index b57d643f..656943cd 100644
--- a/catalog/alu/alu.sv
+++ b/catalog/alu/alu.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Zachary Hsieh and Andrew Yuan
 // 
 //     Create Date: 2023-02-07
 //     Module Name: alu
@@ -20,11 +20,36 @@ module alu
     //
     // ---------------- PORT DEFINITIONS ----------------
     //
+
+    input logic clk,
+    input logic [n-1:0] a, 
+    input logic [n-1:0] b,
+    input logic [2:0] op,
+    output logic [n-1: 0] y,
+    output logic zero
 );
     //
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
 
+
+    assign zero = (y==0);
+
+    always @(a,b,op) begin
+        case(op)
+            3'b000: y = a & b;  //and
+            3'b001: y = a | b;  //or
+            3'b010: y = a + b;  //add
+            3'b011: y = ~(a | b);   //nor
+            3'b100: y = a-b;    //subtract
+            3'b101: y = (a < b) ? {n{1'b1}} : {n{1'b0}};   //set less than
+            3'b110: y = a << b[4:0]; //sll; we have 32 bits, so our max shift amount of 32, which is 5 bits of b if we assume that b is the shift amount and a is the shifted number
+            3'b111: y = a >> b[4:0]; //slr
+        endcase
+    end
+
+
+
 endmodule
 
 `endif // ALU
diff --git a/catalog/alu/tb_alu.sv b/catalog/alu/tb_alu.sv
index 01b626ff..e9def0a2 100644
--- a/catalog/alu/tb_alu.sv
+++ b/catalog/alu/tb_alu.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Zachary Hsieh and Andrew Yuan
 // 
 //     Create Date: 2023-02-07
 //     Module Name: tb_alu
@@ -17,7 +17,69 @@
 `include "alu.sv"
 
 module tb_alu;
-    parameter n = 32;
+    parameter N = 32;
+
+    reg [N-1:0] A;
+    reg [N-1:0] B;
+    reg [2:0] OP;
+    reg CLK;
+
+    wire [N-1:0] Y;
+
+    initial begin : initialize_variable
+    A = 0;
+    B = 0;
+    end
+
+    always begin : clock
+        #5 CLK = ~CLK;
+    end
+
+    always @(posedge CLK) 
+    begin
+        case (OP)
+            3'b000: $display("A=%b B=%b OP=%b Y=%b Zero=%b\n", A, B, OP, Y, ZERO);
+            3'b001: $display("A=%b B=%b OP=%b Y=%b Zero=%b\n", A, B, OP, Y, ZERO);
+            3'b010: $display("A=%b B=%b OP=%b Y=%b Zero=%b\n", A, B, OP, Y, ZERO);
+            3'b011: $display("A=%b B=%b OP=%b Y=%b Zero=%b\n", A, B, OP, Y, ZERO);
+            3'b100: $display("A=%b B=%b OP=%b Y=%b Zero=%b\n", A, B, OP, Y, ZERO);
+            3'b101: $display("A=%b B=%b OP=%b Y=%b Zero=%b\n", A, B, OP, Y, ZERO);
+            3'b110: $display("A=%b B=%b OP=%b Y=%b Zero=%b\n", A, B, OP, Y, ZERO);
+            3'b111: $display("A=%b B=%b OP=%b Y=%b Zero=%b\n", A, B, OP, Y, ZERO);
+        endcase
+    end
+
+
+    //apply input vectors
+    initial begin
+    $dumpfile("tb_alu.vcd");
+    $dumpvars(0, tb_alu.uut);
+    A = 32'b11100000010100010110011110101010;
+    B = 32'b01100001100101100100101001011111;
+    CLK = 0;
+    #10;
+    OP = 3'b000;
+    #10;
+    OP = 3'b001;
+    #10;
+    OP = 3'b010;
+    #10;
+    OP = 3'b011;
+    #10;
+    OP = 3'b100;
+    #10;
+    OP = 3'b101;
+    #10;
+    OP = 3'b110;
+    #10;
+    $finish;
+end
+
+//
+// ---------------- INSTANTIATE UNIT UNDER TEST (UUT) ----------------
+//
+alu uut(.a(A), .b(B), .clk(CLK), .op(OP), .zero(ZERO), .y(Y));
+
 
 endmodule
 `endif // TB_ALU
\ No newline at end of file
diff --git a/catalog/aludec/aludec.sv b/catalog/aludec/aludec.sv
index f4938e14..8121aa5b 100644
--- a/catalog/aludec/aludec.sv
+++ b/catalog/aludec/aludec.sv
@@ -1,11 +1,11 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Zachary Hsieh & Andrew Yuan
 // 
 //     Create Date: 2023-02-07
 //     Module Name: aludec
-//     Description: 32-bit RISC ALU decoder
+//     Description: 16-bit RISC ALU decoder
 //
 // Revision: 1.0
 //
@@ -16,15 +16,36 @@
 `timescale 1ns/100ps
 
 module aludec
-    #(parameter n = 32)(
+    #(parameter n = 16)(
     //
     // ---------------- PORT DEFINITIONS ----------------
     //
-
+    input logic [5:0] funct,      //
+    input logic [1:0] aluop,      //Operation type
+    output logic [2:0] alucontrol //ALU operations
+    );
     //
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
-
+    always @*
+    begin
+        case(aluop)                  //I-type instructions
+        2'b11: alucontrol <= 3'b010; // addi (for lw/sw/jr/addi)
+        2'b10: alucontrol <= 3'b100; // subi (for beq)
+        2'b01: alucontrol <= 3'b101; //slt (for slti)
+            default: case(funct)           // R-type instructions
+                6'b100100: alucontrol <= 3'b000; // and
+                6'b100101: alucontrol <= 3'b001; // or
+                6'b100000: alucontrol <= 3'b010; // add
+                6'b100111: alucontrol <= 3'b011; // nor
+                6'b100010: alucontrol <= 3'b100; // subtract
+                6'b101010: alucontrol <= 3'b101; // slt
+                6'b000000: alucontrol <= 3'b110; // sll
+                6'b000010: alucontrol <= 3'b111; // slr
+                default: alucontrol <= 3'bxxx; // ???
+            endcase
+        endcase
+    end
 endmodule
 
 `endif // ALUDEC
\ No newline at end of file
diff --git a/catalog/aludec/tb_aludec.sv b/catalog/aludec/tb_aludec.sv
index 7fc14cdd..492944a5 100644
--- a/catalog/aludec/tb_aludec.sv
+++ b/catalog/aludec/tb_aludec.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Zachary Hsieh & Andrew Yuan
 // 
 //     Create Date: 2023-02-07
 //     Module Name: tb_aludec
@@ -17,7 +17,54 @@
 `include "aludec.sv"
 
 module tb_aludec;
-    parameter n = 32;
+ // Inputs
+    reg [5:0] funct;
+    reg [1:0] aluop;
+
+    // Outputs
+    wire [2:0] alucontrol;
+
+    // Instantiate the Unit Under Test (UUT)
+    aludec uut (
+        .funct(funct),
+        .aluop(aluop),
+        .alucontrol(alucontrol)
+    );
+
+    // Testbench logic
+    initial begin
+        // Initialize Inputs
+        funct = 0;
+        aluop = 0;
+
+        // Wait for global reset
+        #100;
+        
+        // Test various combinations
+        funct = 6'b100000; aluop = 2'b00; #100;
+        funct = 6'b100101; aluop = 2'b00; #100;
+        funct = 6'b100000; aluop = 2'b00; #100;
+        funct = 6'b100111; aluop = 2'b00; #100;
+        funct = 6'b100010; aluop = 2'b00; #100;
+        funct = 6'b101010; aluop = 2'b00; #100;
+        funct = 6'b000000; aluop = 2'b00; #100;
+        funct = 6'b000010; aluop = 2'b00; #100;
+
+        funct = 6'bxxxxxx; aluop = 2'b01; #100; // Tests for partial don't care in `funct`
+        funct = 6'bxxxxxx; aluop = 2'b10; #100; // Tests for partial don't care in `funct`
+        funct = 6'bxxxxxx; aluop = 2'b11; #100; // Tests for partial don't care in `funct`
+
+        // Additional test for undefined operation
+        funct = 6'b010101; aluop = 2'b11; #100;
+
+        // Finish simulation
+        $finish;
+    end
+
+    // Monitor changes
+    initial begin
+        $monitor("At time %t, funct = %b, aluop = %b, alucontrol = %b", $time, funct, aluop, alucontrol);
+    end
 
 endmodule
 `endif // TB_ALUDEC
\ No newline at end of file
diff --git a/catalog/computer/mult-prog_exe b/catalog/computer/mult-prog_exe
index 1dcb4a0f..dc145b5f 100644
--- a/catalog/computer/mult-prog_exe
+++ b/catalog/computer/mult-prog_exe
@@ -1,11 +1,11 @@
-2002000a
-2003000f
-00620018
-00001010
-00001012
-ac020054
-00000000
-00000000
+0c040004
+0c050004
+0C060002
+0C070005
+00854020
+00c74820
+01098022
+02001020
 00000000
 00000000
 00000000
diff --git a/catalog/computer/tb_computer.sv b/catalog/computer/tb_computer.sv
index 003e5d11..4d8684d6 100644
--- a/catalog/computer/tb_computer.sv
+++ b/catalog/computer/tb_computer.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: Prof Rob Marano
+// Engineer: Zachary Hsieh & Andrew Yuan
 // 
 //     Create Date: 2023-02-07
 //     Module Name: tb_computer
@@ -45,8 +45,9 @@ module tb_computer;
   initial begin
     firstTest = 1'b0;
     secondTest = 1'b0;
-    $dumpfile("tb_computer.vcd");
+    $dumpfile("computer.vcd");
     $dumpvars(0,dut1,clk,reset,writedata,dataadr,memwrite);
+    $dumpvars(0,dut,clk,reset,writedata,dataadr,memwrite);
     $monitor("t=%t\t0x%7h\t%7d\t%8d",$realtime,writedata,dataadr,memwrite);
     // $dumpvars(0,clk,a,b,ctrl,result,zero,negative,carryOut,overflow);
     // $display("Ctl Z  N  O  C  A                    B                    ALUresult");
@@ -55,37 +56,54 @@ module tb_computer;
 
   // initialize test
   initial begin
-    #0 clk_enable <= 0; #50 reset <= 1; # 50; reset <= 0; #50 clk_enable <= 1;
-    #100 $finish;
+    #0 clk_enable <= 1; #10 reset <= 1; #10; reset <= 0;
+    //#530 $finish; //fib
+    #90 $finish; //leaf
   end
 
   // monitor what happens at posedge of clock transition
   always @(posedge clk)
   begin
-      $display("+");
-      $display("\t+instr = 0x%8h",dut.instr);
-      $display("\t+op = 0b%6b",dut.mips.c.op);
-      $display("\t+controls = 0b%9b",dut.mips.c.md.controls);
-      $display("\t+funct = 0b%6b",dut.mips.c.ad.funct);
-      $display("\t+aluop = 0b%2b",dut.mips.c.ad.aluop);
-      $display("\t+alucontrol = 0b%3b",dut.mips.c.ad.alucontrol);
-      $display("\t+alu result = 0x%8h",dut.mips.dp.alu.result);
-      $display("\t+HiLo = 0x%8h",dut.mips.dp.alu.HiLo);
-      $display("\t+$v0 = 0x%4h",dut.mips.dp.rf.rf[2]);
-      $display("\t+$v1 = 0x%4h",dut.mips.dp.rf.rf[3]);
-      $display("\t+$a0 = 0x%4h",dut.mips.dp.rf.rf[4]);
-      $display("\t+$a1 = 0x%4h",dut.mips.dp.rf.rf[5]);
-      $display("\t+$t0 = 0x%4h",dut.mips.dp.rf.rf[8]);
-      $display("\t+$t1 = 0x%4h",dut.mips.dp.rf.rf[9]);
-      $display("\t+regfile -- ra1 = %d",dut.mips.dp.rf.ra1);
-      $display("\t+regfile -- ra2 = %d",dut.mips.dp.rf.ra2);
-      $display("\t+regfile -- we3 = %d",dut.mips.dp.rf.we3);
-      $display("\t+regfile -- wa3 = %d",dut.mips.dp.rf.wa3);
-      $display("\t+regfile -- wd3 = %d",dut.mips.dp.rf.wd3);
-      $display("\t+regfile -- rd1 = %d",dut.mips.dp.rf.rd1);
-      $display("\t+regfile -- rd2 = %d",dut.mips.dp.rf.rd2);
-      $display("\t+RAM[%4d] = %4d",dut.dmem.addr,dut.dmem.readdata);
-      $display("writedata\tdataadr\tmemwrite");
+    $display("+");
+    $display("\t+instr = 0x%8h",dut.instr);
+    $display("\t+pc = 0x%8h", dut.mips.dp.pc);
+    $display("\t+$a0 = 0x%8h", dut.mips.dp.rf.rf[4]);
+    $display("\t+pcbranch = 0x%8h", dut.mips.dp.pcbranch);
+    $display("\t+ra1 = %b", dut.mips.dp.instr[25:21]);
+    $display("\t+ra2 = %b", dut.mips.dp.instr[20:16]);
+    //$display("\t+aluzero = %b", dut.mips.dp.alu.zero);
+    //$display("\t+aluA = 0x%8h", dut.mips.dp.alu.a);
+    //$display("\t+aluB = 0x%8h", dut.mips.dp.alu.b);
+    //$display("\t+alu = 0x%8h", dut.mips.dp.alu.y);
+    //$display("\t+op = 0b%6b",dut.mips.c.op);
+    //$display("\t+controls = 0b%9b",dut.mips.c.md.controls);
+    //$display("\t+funct = 0b%6b",dut.mips.c.ad.funct);
+    //$display("\t+aluop = 0b%2b",dut.mips.c.ad.aluop);
+    //$display("\t+alucontrol = 0b%3b",dut.mips.c.ad.alucontrol);
+    //$display("\t+alu result = 0x%8h",dut.mips.dp.alu.y);
+    //$display("\t+HiLo = 0x%8h",dut.mips.dp.alu.HiLo);
+    //$display("\t+$sp = 0x%4h", dut.mips.dp.rf.rf[29]);
+    $display("\t+$s0 = 0x%4h", dut.mips.dp.rf.rf[16]);
+    //$display("\t+$ra = 0x%4h", dut.mips.dp.rf.rf[31]);
+    $display("\t+$v0 = 0x%4h",dut.mips.dp.rf.rf[2]);
+    $display("\t+$s1 = 0x%4h", dut.mips.dp.rf.rf[17]);
+    $display("\t+$s2 = 0x%4h", dut.mips.dp.rf.rf[18]);
+    //$display("\t+$v1 = 0x%4h",dut.mips.dp.rf.rf[3]);
+    //$display("\t+$a0 = 0x%4h",dut.mips.dp.rf.rf[4]);
+    //$display("\t+$a1 = 0x%4h",dut.mips.dp.rf.rf[5]);
+    $display("\t+$t0 = 0x%4h",dut.mips.dp.rf.rf[8]);
+    $display("\t+$t1 = 0x%4h",dut.mips.dp.rf.rf[9]);
+    $display("\t+$t2 = 0x%4h",dut.mips.dp.rf.rf[10]);
+    $display("\t+$t3 = 0x%4h",dut.mips.dp.rf.rf[11]);
+    //$display("\t+regfile -- ra1 = %d",dut.mips.dp.rf.ra1);
+    //$display("\t+regfile -- ra2 = %d",dut.mips.dp.rf.ra2);
+    //$display("\t+regfile -- we3 = %d",dut.mips.dp.rf.we3);
+    //$display("\t+regfile -- wa3 = %d",dut.mips.dp.rf.wa3);
+    //$display("\t+regfile -- wd3 = %d",dut.mips.dp.rf.wd3);
+    //$display("\t+regfile -- rd1 = %d",dut.mips.dp.rf.rd1);
+    //$display("\t+regfile -- rd2 = %d",dut.mips.dp.rf.rd2);
+    //$display("\t+RAM[%4d] = %4d",dut.dmem.addr,dut.dmem.readdata);
+    //$display("writedata\tdataadr\tmemwrite");
   end
 
   // run program
@@ -93,28 +111,45 @@ module tb_computer;
   always @(negedge clk) begin
     $display("-");
     $display("\t-instr = 0x%8h",dut.instr);
-    $display("\t-op = 0b%6b",dut.mips.c.op);
-    $display("\t-controls = 0b%9b",dut.mips.c.md.controls);
-    $display("\t-funct = 0b%6b",dut.mips.c.ad.funct);
-    $display("\t-aluop = 0b%2b",dut.mips.c.ad.aluop);
-    $display("\t-alucontrol = 0b%3b",dut.mips.c.ad.alucontrol);
-    $display("\t-alu result = 0x%8h",dut.mips.dp.alu.result);
-    $display("\t-HiLo = 0x%8h",dut.mips.dp.alu.HiLo);
+    $display("\t-pc = 0x%8h", dut.mips.dp.pc);
+    $display("\t-pcbranch = 0x%8h", dut.mips.dp.pcbranch);
+    $display("\t-$a0 = 0x%8h", dut.mips.dp.rf.rf[4]);
+    $display("\t-ra1 = %b", dut.mips.dp.instr[25:21]);
+    $display("\t-ra2 = %b", dut.mips.dp.instr[20:16]);
+    //$display("\t-aluzero = %b", dut.mips.dp.alu.zero);
+    //$display("\t-aluA = 0x%8h", dut.mips.dp.alu.a);
+    //$display("\t-aluB = 0x%8h", dut.mips.dp.alu.b);
+    //$display("\t-alu = 0x%8h", dut.mips.dp.alu.y);
+    //$display("\t-op = 0b%6b",dut.mips.c.op);
+    //$display("\t-controls = 0b%9b",dut.mips.c.md.controls);
+    //$display("\t-funct = 0b%6b",dut.mips.c.ad.funct);
+    //$display("\t-aluop = 0b%2b",dut.mips.c.ad.aluop);
+    //$display("\t-alucontrol = 0b%3b",dut.mips.c.ad.alucontrol);
+    //$display("\t-alu result = 0x%8h",dut.mips.dp.alu.y);
+
+    //$display("\t-HiLo = 0x%8h",dut.mips.dp.alu.HiLo);
+    //$display("\t-$sp = 0x%4h", dut.mips.dp.rf.rf[29]);
+    $display("\t-$s0 = 0x%4h", dut.mips.dp.rf.rf[16]);
+    //$display("\t-$ra = 0x%4h", dut.mips.dp.rf.rf[31]);
     $display("\t-$v0 = 0x%4h",dut.mips.dp.rf.rf[2]);
-    $display("\t-$v1 = 0x%4h",dut.mips.dp.rf.rf[3]);
-    $display("\t-$a0 = 0x%4h",dut.mips.dp.rf.rf[4]);
-    $display("\t-$a1 = 0x%4h",dut.mips.dp.rf.rf[5]);
+    $display("\t-$s1 = 0x%4h", dut.mips.dp.rf.rf[17]);
+    $display("\t-$s2 = 0x%4h", dut.mips.dp.rf.rf[18]);
+    //$display("\t-$v1 = 0x%4h",dut.mips.dp.rf.rf[3]);
+    //$display("\t-$a0 = 0x%4h",dut.mips.dp.rf.rf[4]);
+    //$display("\t-$a1 = 0x%4h",dut.mips.dp.rf.rf[5]);
     $display("\t-$t0 = 0x%4h",dut.mips.dp.rf.rf[8]);
     $display("\t-$t1 = 0x%4h",dut.mips.dp.rf.rf[9]);
-    $display("\t-regfile -- ra1 = %d",dut.mips.dp.rf.ra1);
-    $display("\t-regfile -- ra2 = %d",dut.mips.dp.rf.ra2);
-    $display("\t-regfile -- we3 = %d",dut.mips.dp.rf.we3);
-    $display("\t-regfile -- wa3 = %d",dut.mips.dp.rf.wa3);
-    $display("\t-regfile -- wd3 = %d",dut.mips.dp.rf.wd3);
-    $display("\t-regfile -- rd1 = %d",dut.mips.dp.rf.rd1);
-    $display("\t-regfile -- rd2 = %d",dut.mips.dp.rf.rd2);
-    $display("\t+RAM[%4d] = %4d",dut.dmem.addr,dut.dmem.readdata);
-    $display("writedata\tdataadr\tmemwrite");
+    $display("\t-$t2 = 0x%4h",dut.mips.dp.rf.rf[10]);
+    $display("\t-$t3 = 0x%4h",dut.mips.dp.rf.rf[11]);
+    //$display("\t-regfile -- ra1 = %d",dut.mips.dp.rf.ra1);
+    //$display("\t-regfile -- ra2 = %d",dut.mips.dp.rf.ra2);
+    //$display("\t-regfile -- we3 = %d",dut.mips.dp.rf.we3);
+    //$display("\t-regfile -- wa3 = %d",dut.mips.dp.rf.wa3);
+    //$display("\t-regfile -- wd3 = %d",dut.mips.dp.rf.wd3);
+    //$display("\t-regfile -- rd1 = %d",dut.mips.dp.rf.rd1);
+    //$display("\t-regfile -- rd2 = %d",dut.mips.dp.rf.rd2);
+    //$display("\t+RAM[%4d] = %4d",dut.dmem.addr,dut.dmem.readdata);
+    //$display("writedata\tdataadr\tmemwrite");
   end
 
   always @(negedge clk, posedge clk) begin
@@ -126,13 +161,13 @@ module tb_computer;
     //     firstTest = 1'b1;
     //   end
 
-    if (dut.dmem.RAM[84] === 32'h96)
+    if (dut.dmem.RAM[63] === 32'h96)
       begin
         $display("Successfully wrote 0x%4h at RAM[%3d]",84,32'h0096);
         firstTest = 1'b1;
       end
     if(memwrite) begin
-      if(dataadr === 84 & writedata === 32'h96)
+      if(dataadr === 63 & writedata === 32'h96)
       begin
         $display("Successfully wrote 0x%4h at RAM[%3d]",writedata,dataadr);
         firstTest = 1'b1;
diff --git a/catalog/controller/controller.sv b/catalog/controller/controller.sv
index 0ff678dd..6bb22d4d 100644
--- a/catalog/controller/controller.sv
+++ b/catalog/controller/controller.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: Prof Rob Marano
+// Engineer: Zachary Hsieh & Andrew Yuan
 // 
 //     Create Date: 2023-02-07
 //     Module Name: controller
@@ -28,7 +28,7 @@ module controller
     output logic       memtoreg, memwrite,
     output logic       pcsrc, alusrc,
     output logic       regdst, regwrite,
-    output logic       jump,
+    output logic       jump, jumpreg,
     output logic [2:0] alucontrol
 );
     //
@@ -38,7 +38,7 @@ module controller
     logic       branch;
     
     // CPU main decoder
-    maindec md(op, memtoreg, memwrite, branch, alusrc, regdst, regwrite, jump, aluop);
+    maindec md(op, memtoreg, memwrite, branch, alusrc, regdst, regwrite, jump, jumpreg, aluop);
     // CPU's ALU decoder
     aludec  ad(funct, aluop, alucontrol);
 
diff --git a/catalog/cpu/cpu.sv b/catalog/cpu/cpu.sv
index 4d61e9da..a3f4715b 100644
--- a/catalog/cpu/cpu.sv
+++ b/catalog/cpu/cpu.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: Prof Rob Marano
+// Engineer: Zachary Hsieh & Andrew Yuan
 // 
 //     Create Date: 2023-02-07
 //     Module Name: cpu
@@ -35,16 +35,16 @@ module cpu
     //
 
     // cpu internal components
-    logic       memtoreg, alusrc, regdst, regwrite, jump, pcsrc, zero;
+    logic       memtoreg, alusrc, regdst, regwrite, jump, jumpreg, pcsrc, zero;
     logic [2:0] alucontrol;
     
     controller c(instr[(31):26], instr[5:0], zero,
                     memtoreg, memwrite, pcsrc,
-                    alusrc, regdst, regwrite, jump,
+                    alusrc, regdst, regwrite, jump, jumpreg,
                     alucontrol);
 
     datapath dp(clk, reset, memtoreg, pcsrc,
-                    alusrc, regdst, regwrite, jump,
+                    alusrc, regdst, regwrite, jump, jumpreg,
                     alucontrol,
                     zero, pc, instr,
                     aluout, writedata, readdata);
diff --git a/catalog/datapath/datapath.sv b/catalog/datapath/datapath.sv
index 970a4aab..6d2637c0 100644
--- a/catalog/datapath/datapath.sv
+++ b/catalog/datapath/datapath.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: Prof Rob Marano
+// Engineer: Zachary Hsieh and Andrew Yuan
 // 
 //     Create Date: 2023-02-07
 //     Module Name: datapath
@@ -24,7 +24,7 @@
 `include "../signext/signext.sv"
 
 module datapath
-    #(parameter n = 32)(
+    #(parameter n = 32, parameter r = 5)(
     //
     // ---------------- PORT DEFINITIONS ----------------
     //
@@ -32,6 +32,7 @@ module datapath
     input  logic        memtoreg, pcsrc,
     input  logic        alusrc, regdst,
     input  logic        regwrite, jump,
+    input  logic        jumpreg,
     input  logic [2:0]  alucontrol,
     output logic        zero,
     output logic [(n-1):0] pc,
@@ -43,18 +44,19 @@ module datapath
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
     logic [4:0]  writereg;
-    logic [(n-1):0] pcnext, pcnextbr, pcplus4, pcbranch;
+    logic [(n-1):0] pcnext, pcnextbr, pcplus4, pcbranch, finalpcnext;
     logic [(n-1):0] signimm, signimmsh;
     logic [(n-1):0] srca, srcb;
     logic [(n-1):0] result;
 
     // "next PC" logic
-    dff #(n)    pcreg(clk, reset, pcnext, pc);
+    dff #(n)    pcreg(clk, reset, finalpcnext, pc);
     adder       pcadd1(pc, 32'b100, pcplus4);
     sl2         immsh(signimm, signimmsh);
     adder       pcadd2(pcplus4, signimmsh, pcbranch);
     mux2 #(n)   pcbrmux(pcplus4, pcbranch, pcsrc, pcnextbr);
     mux2 #(n)   pcmux(pcnextbr, {pcplus4[31:28], instr[25:0], 2'b00}, jump, pcnext);
+    mux2 #(n)   pcmux2(pcnext, aluout, jumpreg, finalpcnext);
 
     // register file logic
     regfile     rf(clk, regwrite, instr[25:21], instr[20:16], writereg, result, srca, writedata);
diff --git a/catalog/dmem/dmem.sv b/catalog/dmem/dmem.sv
index acf246c8..539ea7c9 100644
--- a/catalog/dmem/dmem.sv
+++ b/catalog/dmem/dmem.sv
@@ -32,7 +32,7 @@ module dmem
 
     assign readdata = RAM[addr[(n-1):2]]; // word aligned (ignores lower 2 bits of address)
 
-    always @(posedge clk) // write on posedge
+    always @(posedge clk) // write on negedge
         if (write_enable) RAM[addr[(n-1):2]] <= writedata;
 
 endmodule
diff --git a/catalog/imem/imem.sv b/catalog/imem/imem.sv
index e9d554c3..ed1e1ddd 100644
--- a/catalog/imem/imem.sv
+++ b/catalog/imem/imem.sv
@@ -34,6 +34,7 @@ module imem
       // read memory in hex format from file 
       // $readmemh("program_exe",RAM);
       $readmemh("mult-prog_exe",RAM);
+      //$readmemh()
     end
 
   assign readdata = RAM[addr]; // word aligned
diff --git a/catalog/maindec/maindec.sv b/catalog/maindec/maindec.sv
index 6b0a741c..7af4e55a 100644
--- a/catalog/maindec/maindec.sv
+++ b/catalog/maindec/maindec.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: Prof Rob Marano
+// Engineer: Zachary Hsieh and Andrew Yuan
 // 
 //     Create Date: 2023-02-07
 //     Module Name: maindec
@@ -24,27 +24,30 @@ module maindec
     output logic       memtoreg, memwrite,
     output logic       branch, alusrc,
     output logic       regdst, regwrite,
-    output logic       jump,
+    output logic       jump, jumpreg,
     output logic [1:0] aluop
 );
     //
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
-    logic [8:0] controls; // 9-bit control vector
+    logic [9:0] controls; // 10-bit control vector
 
-    // controls has 9 logical signals
+    // controls has 10 logical signals
     assign {regwrite, regdst, alusrc, branch, memwrite,
-            memtoreg, jump, aluop} = controls;
+            memtoreg, jump, jumpreg, aluop} = controls;
 
     always @* begin
         case(op)
-            6'b000000: controls <= 9'b110000010; // RTYPE
-            6'b100011: controls <= 9'b101001000; // LW
-            6'b101011: controls <= 9'b001010000; // SW
-            6'b000100: controls <= 9'b000100001; // BEQ
-            6'b001000: controls <= 9'b101000000; // ADDI
-            6'b000010: controls <= 9'b000000100; // J
-            default:   controls <= 9'bxxxxxxxxx; // illegal operation
+            6'b000000: controls <= 10'b1100000000; // RTYPE
+            6'b000001: controls <= 10'b1010010011; // LW
+            6'b000010: controls <= 10'b0010100011; // SW
+            6'b000011: controls <= 10'b1010000011; // ADDI
+            6'b000100: controls <= 10'b0001000010; // BEQ
+            6'b000101: controls <= 10'b1010000001; // STLI
+            6'b000110: controls <= 10'b0000001000; // Jump
+            6'b000111: controls <= 10'b1100011000; //JAL
+            6'b001000: controls <= 10'b0010001111; //jr
+            default:   controls <= 10'bxxxxxxxxxx; // illegal operation
         endcase
     end
 
diff --git a/catalog/maindec/tb_maindec.sv b/catalog/maindec/tb_maindec.sv
index 1b2eed2c..dee99b13 100644
--- a/catalog/maindec/tb_maindec.sv
+++ b/catalog/maindec/tb_maindec.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Zachary Hsieh and Andrew Yuan
 // 
 //     Create Date: 2023-02-07
 //     Module Name: tb_maindec
@@ -17,7 +17,42 @@
 `include "maindec.sv"
 
 module tb_maindec;
-    parameter n = 32;
+    parameter N = 32;
+
+    reg [5:0] OP;
+
+    wire REGWRITE;
+    wire REGDST;
+    wire ALUSRC;
+    wire BRANCH;
+    wire MEMWRITE;
+    wire MEMTOREG;
+    wire JUMP;
+    wire JUMPREG;
+    wire [1:0] ALUOP;
+
+    //apply input vectors
+    initial begin : prog_apply_stimuli
+    #0
+    OP = 0;
+    #10 
+    for(int i=0; i<2**3+1; i++)
+    begin
+        OP = i;
+        #10;
+        $display("OP: %b\tOUTPUT: %b%b%b%b%b%b%b%b%b\n", OP, REGWRITE, REGDST, ALUSRC, BRANCH, MEMWRITE, MEMTOREG, JUMP, JUMPREG, ALUOP);
+        #10;
+    end
+    #10
+    $finish;
+end
+
+//
+// ---------------- INSTANTIATE UNIT UNDER TEST (UUT) ----------------
+//
+maindec uut(.op(OP), .regwrite(REGWRITE), .regdst(REGDST), .alusrc(ALUSRC), .branch(BRANCH), .memwrite(MEMWRITE), .memtoreg(MEMTOREG),
+            .jump(JUMP), .jumpreg(JUMPREG), .aluop(ALUOP));
+
 
 endmodule
 `endif // TB_MAINDEC
\ No newline at end of file
diff --git a/catalog/regfile/regfile.sv b/catalog/regfile/regfile.sv
index 3b4d0876..bf53b66f 100644
--- a/catalog/regfile/regfile.sv
+++ b/catalog/regfile/regfile.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: Prof Rob Marano
+// Engineer: Zachary Hsieh & Andrew Yuan
 // 
 //     Create Date: 2023-02-07
 //     Module Name: regfile
@@ -30,7 +30,7 @@ module regfile
     //
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
-    logic [(n-1):0] rf[(2**5-1):0];
+    logic [(n-1):0] rf[(2**r-1):0];
 
     // three ported register file
     // read two ports combinationally
@@ -38,6 +38,13 @@ module regfile
     // register 0 hardwired to 0
     // note: for pipelined processor, write third port
     // on falling edge of clk
+    initial begin
+        int i;
+        for(i = 0; i<2**r-1; i = i + 1)
+            begin
+                rf[i] <= 32'b0;
+            end
+    end
 
     always @(posedge clk)
         if (we3) rf[wa3] <= wd3;	
diff --git a/documentation/Design.png b/documentation/Design.png
new file mode 100644
index 00000000..15639499
Binary files /dev/null and b/documentation/Design.png differ
diff --git a/documentation/ECE251 Final Project ISA.pdf b/documentation/ECE251 Final Project ISA.pdf
new file mode 100644
index 00000000..9c0d1d4e
Binary files /dev/null and b/documentation/ECE251 Final Project ISA.pdf differ
diff --git a/documentation/fib-prog_exe b/documentation/fib-prog_exe
new file mode 100644
index 00000000..272e66e8
--- /dev/null
+++ b/documentation/fib-prog_exe
@@ -0,0 +1,64 @@
+0c090001
+0c110001
+0C0A0002
+0C0B0009
+116A0006
+01319020
+02204820
+00128820
+0d4a0001
+18100004
+08110000
+04090000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
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+00000000
+00000000
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+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
\ No newline at end of file
diff --git a/documentation/leaf-prog_exe b/documentation/leaf-prog_exe
new file mode 100644
index 00000000..dc145b5f
--- /dev/null
+++ b/documentation/leaf-prog_exe
@@ -0,0 +1,64 @@
+0c040004
+0c050004
+0C060002
+0C070005
+00854020
+00c74820
+01098022
+02001020
+00000000
+00000000
+00000000
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+00000000
+00000000
+00000000
+00000000
+00000000
\ No newline at end of file
diff --git a/documentation/program_assembly.pdf b/documentation/program_assembly.pdf
new file mode 100644
index 00000000..80977c75
Binary files /dev/null and b/documentation/program_assembly.pdf differ
diff --git a/documentation/timing_diagram.png b/documentation/timing_diagram.png
new file mode 100644
index 00000000..f38a732a
Binary files /dev/null and b/documentation/timing_diagram.png differ