diff --git a/README.md b/README.md
index a5e73aad..47401ebd 100644
--- a/README.md
+++ b/README.md
@@ -1,3 +1,18 @@
+# 32 bit MIPS-wannabe Processor
+Isaac Moore and Morris Madeb
+
+
+
+![Opcodes and functions](https://github.com/cooper-union-ece-251-marano/final-project-ece-251-spring-2024-comparchcrunch/assets/44485789/4013d522-ea90-46d7-9a6f-358f8ff4446e)
+Defined functions
+
+![instruction format](https://github.com/cooper-union-ece-251-marano/final-project-ece-251-spring-2024-comparchcrunch/assets/44485789/6d91fd3a-0b64-4fc6-941d-29505cac87e8)
+R, I, and J Formating
+
+![e90449dc-7ca4-4dd5-940c-21ea568a4e40](https://github.com/cooper-union-ece-251-marano/final-project-ece-251-spring-2024-comparchcrunch/assets/44485789/c41e345e-fa31-405a-bd34-1f0094a705eb)
+Datapath
+
+[![Review Assignment Due Date](https://classroom.github.com/assets/deadline-readme-button-24ddc0f5d75046c5622901739e7c5dd533143b0c8e959d652212380cedb1ea36.svg)](https://classroom.github.com/a/pelSJLGu)
 # Catalog of Verilog Components to Build and Simulate a MIPS-based RISC.
 
 This work is based off the MIPS Verilog code by [Harris and Harris](https://pages.hmc.edu/harris/ddca/ddca2e.html)
diff --git a/catalog/adder/adder.sv b/catalog/adder/adder.sv
index f087c643..38fe3b77 100644
--- a/catalog/adder/adder.sv
+++ b/catalog/adder/adder.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Isaac Moore, Morris Madeb
 // 
 //     Create Date: 2023-02-07
 //     Module Name: adder
@@ -17,14 +17,16 @@
 
 module adder
     #(parameter n = 32)(
-    //
-    // ---------------- PORT DEFINITIONS ----------------
-    //
-
-);
-    //
-    // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
-    //
+        //
+        // ---------------- PORT DEFINITIONS ----------------
+        //
+        input [(n-1):0] a, b;
+        output reg [(n-1):0] c;
+    );
+   //
+   // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
+   //
+   assign c = a + b;
 
 endmodule
 
diff --git a/catalog/adder/clean.ps1 b/catalog/adder/clean.ps1
new file mode 100644
index 00000000..f59c741e
--- /dev/null
+++ b/catalog/adder/clean.ps1
@@ -0,0 +1,23 @@
+<#
+ # File: 	clean.ps1
+ # Author: 	Prof. Rob Marano
+ # Build and test file for Verilog on Windows using PowerShell
+ # Note: icarus verilog and gtkwave must be installed
+ #>
+
+# $COMPONENT is named in config.ps1
+# Do not forget to add that file in the same directory as this file and set the variable
+$ScriptDirectory = Split-Path -Path $MyInvocation.MyCommand.Definition -Parent
+try {
+    . ("$ScriptDirectory\config.ps1")
+}
+catch {
+    Write-Host "Error while loading supporting PowerShell Scripts"
+    [Environment]::Exit(1)
+}
+
+# Clean up from last run
+Write-Output "Removing files: $filesToRemove"
+$filesToRemove | ForEach-Object { Remove-Item -Path $_ -Force -ErrorAction SilentlyContinue -Confirm:$false}
+
+Write-Output "Finished cleaning up files."
\ No newline at end of file
diff --git a/catalog/adder/config.ps1 b/catalog/adder/config.ps1
new file mode 100644
index 00000000..6fcd6d4f
--- /dev/null
+++ b/catalog/adder/config.ps1
@@ -0,0 +1,23 @@
+<#
+ # File: 	config.ps1
+ # Author: 	Prof. Rob Marano
+ # Build and test file for Verilog on Windows using PowerShell
+ # Note: icarus verilog and gtkwave must be installed
+ #>
+
+ $COMPONENT = "adder"
+ #
+ $SRC = "$COMPONENT.sv"
+ $TESTBENCH = "tb_$COMPONENT.sv"
+ $TBOUTPUT = "tb_$COMPONENT.vcd"
+ $filesToRemove = @("$COMPONENT", "$TBOUTPUT")
+ 
+ # TOOLS
+ # You need to update the paths below to the tools in your system
+ $COMPILER = "C:\ProgramData\chocolatey\bin\iverilog.exe"
+ $SIMULATOR = "C:\ProgramData\chocolatey\bin\vvp.exe"
+ $VIEWER = "C:\ProgramData\chocolatey\bin\gtkwave.exe" # GUI app
+ # TOOL OPTIONS
+ $COFLAGS = "-g2012"
+ $SFLAGS = "-M ."		#SIMULATOR FLAGS
+ $SOUTPUT = "-lxt2"		#SIMULATOR OUTPUT TYPE
\ No newline at end of file
diff --git a/catalog/adder/display.ps1 b/catalog/adder/display.ps1
new file mode 100644
index 00000000..898f11bf
--- /dev/null
+++ b/catalog/adder/display.ps1
@@ -0,0 +1,27 @@
+<#
+ # File: 	display.ps1
+ # Author: 	Prof. Rob Marano
+ # Build and test file for Verilog on Windows using PowerShell
+ # Note: icarus verilog and gtkwave must be installed
+ #>
+
+# $COMPONENT is named in config.ps1
+# Do not forget to add that file in the same directory as this file and set the variable
+$ScriptDirectory = Split-Path -Path $MyInvocation.MyCommand.Definition -Parent
+try {
+    . ("$ScriptDirectory\config.ps1")
+}
+catch {
+    Write-Host "Error while loading supporting PowerShell Scripts"
+    [Environment]::Exit(1)
+}
+
+#
+# Display Verilog module with testbench
+# $(SIMULATOR) $(SFLAGS) $(COMPONENT) $(TESTBENCH) $(SOUTPUT)
+$displayProcessOptions = @{
+    FilePath = "$VIEWER"
+    ArgumentList = @("$TBOUTPUT")
+    UseNewEnvironment = $true
+}
+Start-Process @displayProcessOptions -NoNewWindow -Wait
\ No newline at end of file
diff --git a/catalog/adder/makefile.ps1 b/catalog/adder/makefile.ps1
new file mode 100644
index 00000000..5ba0fee0
--- /dev/null
+++ b/catalog/adder/makefile.ps1
@@ -0,0 +1,44 @@
+<#
+ # File: 	makefile.ps1
+ # Author: 	Prof. Rob Marano
+ # Build and test file for Verilog on Windows using PowerShell
+ # Note: icarus verilog and gtkwave must be installed
+ #>
+
+# $COMPONENT is named in config.ps1
+# Do not forget to add that file in the same directory as this file and set the variable
+$ScriptDirectory = Split-Path -Path $MyInvocation.MyCommand.Definition -Parent
+try {
+    . ("$ScriptDirectory\config.ps1")
+}
+catch {
+    Write-Host "Error while loading supporting PowerShell Scripts"
+    [Environment]::Exit(1)
+}
+
+# Clean up from last run
+Write-Output "Removing files: $filesToRemove"
+#Remove-Item -Path $filesToRemove -ErrorAction SilentlyContinue -Confirm
+$filesToRemove | ForEach-Object { Remove-Item -Path $_ -Force -ErrorAction SilentlyContinue -Confirm:$false}
+
+#
+# Compile Verilog file
+#
+# $COMPILER $COFLAGS -o $COMPONENT $TESTBENCH $SRC
+$compileProcessOptions = @{
+    FilePath = "$COMPILER"
+    ArgumentList = @("$COFLAGS", "-o", "$COMPONENT", "$TESTBENCH", "$SRC")
+    UseNewEnvironment = $true
+}
+Start-Process -NoNewWindow -Wait @compileProcessOptions
+
+#
+# Simulate Verilog module with testbench
+# $(SIMULATOR) $(SFLAGS) $(COMPONENT) $(TESTBENCH) $(SOUTPUT)
+$simulateProcessOptions = @{
+    FilePath = "$SIMULATOR"
+    ArgumentList = @("$SFLAGS", "$COMPONENT", "$SOUTPUT")
+    UseNewEnvironment = $true
+}
+Write-Output @simulateProcessOptions
+Start-Process @simulateProcessOptions -NoNewWindow -Wait
\ No newline at end of file
diff --git a/catalog/adder/tb_adder.sv b/catalog/adder/tb_adder.sv
index 0b9579f7..f5d47428 100644
--- a/catalog/adder/tb_adder.sv
+++ b/catalog/adder/tb_adder.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Isaac Moore, Morris Madeb
 // 
 //     Create Date: 2023-02-07
 //     Module Name: tb_adder
@@ -18,21 +18,28 @@
 
 module tb_adder;
     parameter n = 32;
-    logic [(n-1):0] a, b, y;
+    logic [(n-1):0] a, b, out;
 
    initial begin
-        $dumpfile("adder.vcd");
+        $dumpfile("tb_adder.vcd");
         $dumpvars(0, uut);
-        $monitor("a = 0x%0h b = 0x%0h y = 0x%0h", a, b, y);
+        $monitor("a = 0x%0h b = 0x%0h out = 0x%0h", a, b, out);
     end
 
     initial begin
-        a <= #n'hFFFFFFFF;
-        b <= #n'hFFFFFFFF;
+        a <= #n'h01B30FFF;
+        b <= #n'hFFA5FFFF;
+        #10
+        a <= #n'987654321;
+        b <= #n'123456789;
+        #10
+        a <= #n'h01000001;
+        b <= #n'101010101;
+        $finish;
     end
 
     adder uut(
-        .A(a), .B(b), .Y(y)
+        .a(a), .b(b), .c(out)
     );
 endmodule
 `endif // TB_ADDER
\ No newline at end of file
diff --git a/catalog/alu/alu.sv b/catalog/alu/alu.sv
index b57d643f..5be32cbc 100644
--- a/catalog/alu/alu.sv
+++ b/catalog/alu/alu.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Isaac Moore, Morris Madeb
 // 
 //     Create Date: 2023-02-07
 //     Module Name: alu
@@ -20,10 +20,41 @@ module alu
     //
     // ---------------- PORT DEFINITIONS ----------------
     //
+    input logic clk,
+    input logic [2:0] alucontrol,
+    input logic [(n-1):0] a, b,
+    output logic [(n-1):0] out,
+    output logic zero
 );
     //
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
+    logic [(2*n-1):0] HILO;
+    
+    assign zero = (result == {n{1'b0}});
+    
+    initial begin 
+        HILO = {(2*n){1'b0}};
+    end
+
+    always@(alucontrol,a,b) begin
+        case(alucontrol)
+            3'b000: result = a & b; //and
+            3'b001: result = a | b; //or
+            3'b010: result = ~(a | b); //nor
+            3'b011: result = a + b; //add
+            3'b100: result = a - b; //sub
+            3'b101: result = HILO[(2*n-1):n]; //mfhi
+            3'b110: result = HILO[(n-1):0]; //mflo
+            3'b111: result = (a<b)?1:0; //slt
+        endcase
+    end
+
+    always@(negedge clk) begin
+        case(alucontrol)
+            3'b101: HILO = a * b;
+        endcase
+    end
 
 endmodule
 
diff --git a/catalog/aludec/aludec.sv b/catalog/aludec/aludec.sv
index f4938e14..d077952d 100644
--- a/catalog/aludec/aludec.sv
+++ b/catalog/aludec/aludec.sv
@@ -16,15 +16,35 @@
 `timescale 1ns/100ps
 
 module aludec
-    #(parameter n = 32)(
+    #(parameter n = 32, r = 6)(
     //
     // ---------------- PORT DEFINITIONS ----------------
     //
-
+    input logic [(r-1):0] = funct,
+    input [1:0] aluop,
+    output reg [2:0] alucontrol
+    );
     //
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
-
+    always@(*) begin
+        case(aluop)
+            2'b00: alucontrol <= 3'b010; //addi
+            2'b01: alucontrol <= 3'b110; //subi
+            default: case(funct)
+                6'b100000: alucontrol <= 3'b011; //add
+                6'b100010: alucontrol <= 3'b100; //sub
+                6'b100100: alucontrol <= 3'b000; //and
+                6'b100101: alucontrol <= 3'b001; //or
+                6'b100111: alucontrol <= 3'b010; //nor
+                6'b011000: alucontrol <= 3'b101; //mult
+                6'b010000: alucontrol <= 3'b101; //move hi
+                6'b010000: alucontrol <= 3'b110; //move lo
+                6'b101010: alucontrol <= 3'b111; //slt
+                default:   alucontrol <= 3'bxxx; //Illegal function
+            endcase
+        endcase
+    end
 endmodule
 
 `endif // ALUDEC
\ No newline at end of file
diff --git a/catalog/clock/clock.sv b/catalog/clock/clock.sv
index 1357f1ee..486c8bf4 100644
--- a/catalog/clock/clock.sv
+++ b/catalog/clock/clock.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: Prof Rob Marano
+// Engineer: Isaac Moore, Morris Madeb
 // 
 //     Create Date: 2023-02-07
 //     Module Name: clock
@@ -55,4 +55,4 @@ module clock
     end
 endmodule
 
-`endif // CLOCK
\ No newline at end of file
+`endif // CLOCK
diff --git a/catalog/clock/tb_clock.sv b/catalog/clock/tb_clock.sv
index 5070756f..d7ce99e5 100644
--- a/catalog/clock/tb_clock.sv
+++ b/catalog/clock/tb_clock.sv
@@ -21,7 +21,7 @@ module tb_clock;
     logic enable;
 
    initial begin
-        $dumpfile("clock.vcd");
+        $dumpfile("tb_clock.vcd");
         $dumpvars(0, uut);
         //$monitor("enable = %b clk = %b", enable, clk);
         $monitor("time=%0t \t enable=%b clk=%b",$realtime, enable, clk);
diff --git a/catalog/computer/computer.sv b/catalog/computer/computer.sv
index 2a6f0b3b..365fc8d1 100644
--- a/catalog/computer/computer.sv
+++ b/catalog/computer/computer.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: Prof Rob Marano
+// Engineer: Isaac Moore, Morris Madeb
 // 
 //     Create Date: 2023-02-07
 //     Module Name: computer
@@ -31,6 +31,7 @@ module computer
     //
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
+    //maybe wire not logic
     logic [(n-1):0] pc, instr, readdata;
 
     // computer internal components
@@ -44,4 +45,4 @@ module computer
 
 endmodule
 
-`endif // COMPUTER
\ No newline at end of file
+`endif // COMPUTER
diff --git a/catalog/controller/controller.sv b/catalog/controller/controller.sv
index 0ff678dd..88bcc775 100644
--- a/catalog/controller/controller.sv
+++ b/catalog/controller/controller.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: Prof Rob Marano
+// Engineer: Isaac Moore, Morris Madeb
 // 
 //     Create Date: 2023-02-07
 //     Module Name: controller
@@ -35,7 +35,7 @@ module controller
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
     logic [1:0] aluop;
-    logic       branch;
+    logic branch;
     
     // CPU main decoder
     maindec md(op, memtoreg, memwrite, branch, alusrc, regdst, regwrite, jump, aluop);
@@ -43,7 +43,6 @@ module controller
     aludec  ad(funct, aluop, alucontrol);
 
   assign pcsrc = branch & zero;
-
 endmodule
 
 `endif // CONTROLLER
diff --git a/catalog/dff/dff.sv b/catalog/dff/dff.sv
index 51c77b94..03c97610 100644
--- a/catalog/dff/dff.sv
+++ b/catalog/dff/dff.sv
@@ -20,22 +20,22 @@ module dff
     //
     // ---------------- PORT DEFINITIONS ----------------
     //
-    input  logic CLOCK, RESET,
-    input  logic [(n-1):0] D,
-    output logic [(n-1):0] Q
+    input  logic clk, rst,
+    input  logic [(n-1):0] d,
+    output logic [(n-1):0] q
 );
     //
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
-    always @(posedge CLOCK, posedge RESET)
+    always @(posedge clk, posedge rst)
     begin
-        if (RESET)
+        if (rst)
         begin
-            Q <= 0;
+            q <= 0;
         end
         else
         begin
-            Q <= D;
+            q <= d;
         end
     end
 endmodule
diff --git a/catalog/dmem/dmem.sv b/catalog/dmem/dmem.sv
index acf246c8..e6ba2ff7 100644
--- a/catalog/dmem/dmem.sv
+++ b/catalog/dmem/dmem.sv
@@ -28,7 +28,7 @@ module dmem
     //
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
-    logic [(n-1):0] RAM[0:(2**r-1)];
+    logic [(n-1):0] RAM[(2**r-1):0];
 
     assign readdata = RAM[addr[(n-1):2]]; // word aligned (ignores lower 2 bits of address)
 
diff --git a/catalog/imem/imem.sv b/catalog/imem/imem.sv
index e9d554c3..e60aae06 100644
--- a/catalog/imem/imem.sv
+++ b/catalog/imem/imem.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: Prof Rob Marano
+// Engineer: Isaac Moore, Morris Madeb
 // 
 //     Create Date: 2023-02-07
 //     Module Name: imem
diff --git a/catalog/maindec/maindec.sv b/catalog/maindec/maindec.sv
index 6b0a741c..3116253f 100644
--- a/catalog/maindec/maindec.sv
+++ b/catalog/maindec/maindec.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: Prof Rob Marano
+// Engineer: Isaac Moore, Morris Madeb
 // 
 //     Create Date: 2023-02-07
 //     Module Name: maindec
@@ -36,13 +36,17 @@ module maindec
     assign {regwrite, regdst, alusrc, branch, memwrite,
             memtoreg, jump, aluop} = controls;
 
+    //first 6 bits is op, determinining control values
+    //aluop is last two digits
     always @* begin
         case(op)
-            6'b000000: controls <= 9'b110000010; // RTYPE
+            6'b000000: controls <= 9'b100100010; // RTYPE
+            //I type
             6'b100011: controls <= 9'b101001000; // LW
             6'b101011: controls <= 9'b001010000; // SW
             6'b000100: controls <= 9'b000100001; // BEQ
             6'b001000: controls <= 9'b101000000; // ADDI
+            //J type
             6'b000010: controls <= 9'b000000100; // J
             default:   controls <= 9'bxxxxxxxxx; // illegal operation
         endcase
diff --git a/catalog/maindec/tb_maindec.sv b/catalog/maindec/tb_maindec.sv
index 1b2eed2c..b9d46e3c 100644
--- a/catalog/maindec/tb_maindec.sv
+++ b/catalog/maindec/tb_maindec.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Isaac Moore, Morris Madeb
 // 
 //     Create Date: 2023-02-07
 //     Module Name: tb_maindec
@@ -18,6 +18,24 @@
 
 module tb_maindec;
     parameter n = 32;
+    input  logic [5:0] op;
+    output logic memtoreg, memwrite, branch, alusrc, regdst, regwrite, jump;
+    output logic [1:0] aluop;
 
+    initial begin
+        $dumpfile("tb_maindec.vcd");
+        $dumpvars(0, uut);
+        $monitor("time=%0t \t op=%b controls=%b", $realtime, op, {regwrite, regdst, alusrc, branch, memwrite,memtoreg, jump, aluop});
+        #10
+    end
+
+    initial begin
+        //TO DO: op code testing, should be straightforward
+        $finish;
+    end
+    
+    maindec uut(
+        .op(op), .memtoreg(memtoreg), .memwrite(memwrite), .branch(branch), .alusrc(alusrc), .regdst(regdst), .regwrite(regwrite), .jump(jump), .aluop(aluop)
+    );
 endmodule
 `endif // TB_MAINDEC
\ No newline at end of file
diff --git a/catalog/mux2/mux2.sv b/catalog/mux2/mux2.sv
index f856a09b..d83f2652 100644
--- a/catalog/mux2/mux2.sv
+++ b/catalog/mux2/mux2.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: Prof Rob Marano
+// Engineer: Isaac Moore, Morris Madeb
 // 
 //     Create Date: 2023-02-07
 //     Module Name: mux2
@@ -20,14 +20,14 @@ module mux2
     //
     // ---------------- PORT DEFINITIONS ----------------
     //
-    input  logic [(n-1):0] D0, D1,
-    input  logic S,
-    output logic [(n-1):0] Y
+    input  logic [(n-1):0] d0, d1,
+    input  logic sel,
+    output logic [(n-1):0] out
 );
     //
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
-    assign Y = S ? D1 : D0;
+    assign out = sel ? d1 : d0;
 endmodule
 
-`endif // MUX2
\ No newline at end of file
+`endif // MUX2
diff --git a/catalog/regfile/regfile.sv b/catalog/regfile/regfile.sv
index 3b4d0876..c016bac5 100644
--- a/catalog/regfile/regfile.sv
+++ b/catalog/regfile/regfile.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: Prof Rob Marano
+// Engineer: Isaac Moore, Morris Madeb
 // 
 //     Create Date: 2023-02-07
 //     Module Name: regfile
@@ -18,14 +18,14 @@
 module regfile
     // n=bit length of register; r=bit length of addr of registers
     #(parameter n = 32, parameter r = 5)(
-    //
-    // ---------------- PORT DEFINITIONS ----------------
-    //
-    input  logic        clk, 
-    input  logic        we3, 
-    input  logic [(r-1):0]  ra1, ra2, wa3, 
-    input  logic [(n-1):0] wd3, 
-    output logic [(n-1):0] rd1, rd2
+        //
+        // ---------------- PORT DEFINITIONS ----------------
+        //
+        input  logic clk, 
+        input  logic we3, 
+        input  logic [(r-1):0] ra1, ra2, wa3, 
+        input  logic [(n-1):0] wd3, 
+        output logic [(n-1):0] rd1, rd2
     );
     //
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
@@ -40,10 +40,10 @@ module regfile
     // on falling edge of clk
 
     always @(posedge clk)
-        if (we3) rf[wa3] <= wd3;	
+        if (we3) rf[wa3] <= wd3;
 
     assign rd1 = (ra1 != 0) ? rf[ra1] : 0;
     assign rd2 = (ra2 != 0) ? rf[ra2] : 0;
 endmodule
 
-`endif // REGFILE
\ No newline at end of file
+`endif // REGFILE
diff --git a/catalog/regfile/tb_regfile.sv b/catalog/regfile/tb_regfile.sv
index 5888e5b6..644020b6 100644
--- a/catalog/regfile/tb_regfile.sv
+++ b/catalog/regfile/tb_regfile.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Isaac Moore, Morris Madeb
 // 
 //     Create Date: 2023-02-07
 //     Module Name: tb_regfile
@@ -18,6 +18,27 @@
 
 module tb_regfile;
     parameter n = 32;
+    parameter r = 5;
+    logic clk, 
+    logic we3, 
+    logic [(r-1):0] ra1, ra2, wa3;
+    logic [(n-1):0] wd3, rd1, rd2;
 
+    initial begin
+        $dumpfile("tb_regfile.vcd");
+        $dumpvars(0, uut);
+        $monitor("time=%0t \t a=%b y=%b",$realtime, a, out);
+        clk <= 0;
+        #10
+    end
+
+    initial begin
+        //TO DO: regfile tests
+        $finish;
+    end
+
+    regfile uut(
+        .clk(clk), .we3(writeControl), .ra1(ra1), .ra2(ra2), .wa3(wa3), .wd3(wd3), .rd1(rd1), .rd2(rd2)
+    );
 endmodule
 `endif // TB_REGFILE
\ No newline at end of file
diff --git a/catalog/signext/signext.sv b/catalog/signext/signext.sv
index fd728855..46ef7fec 100644
--- a/catalog/signext/signext.sv
+++ b/catalog/signext/signext.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: Prof Rob Marano
+// Engineer: Isaac Moore, Morris Madeb
 // 
 //     Create Date: 2023-02-07
 //     Module Name: signext
@@ -20,13 +20,13 @@ module signext
     //
     // ---------------- PORT DEFINITIONS ----------------
     //
-    input  logic [(i-1):0] A,
-    output logic [(n-1):0] Y
+    input  logic [(i-1):0] a,
+    output logic [(n-1):0] out
 );
     //
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
-    assign Y = { {n{A[(i-1)]}}, A}; // sign extend (i-1)th bit i bits to the left.
+    assign out = { {n{a[(i-1)]}}, a}; // sign extend (i-1)th bit i bits to the left.
 endmodule
 
-`endif // SIGNEXT
\ No newline at end of file
+`endif // SIGNEXT
diff --git a/catalog/signext/tb_signext.sv b/catalog/signext/tb_signext.sv
index a2d8da0c..1a35a970 100644
--- a/catalog/signext/tb_signext.sv
+++ b/catalog/signext/tb_signext.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: Prof Rob Marano
+// Engineer: Prof Rob Marano, Isaac Moore
 // 
 //     Create Date: 2023-02-07
 //     Module Name: tb_signext
@@ -20,21 +20,26 @@ module tb_sl2;
     parameter n = 32; // #bits for an operand
     parameter i = n/2; // #bits for an immediate
     logic [(i-1):0] a;
-    logic [(n-1):0] y;
+    logic [(n-1):0] out;
 
    initial begin
         $dumpfile("signext.vcd");
         $dumpvars(0, uut);
         //$monitor("a = %b (0x%0h)(%0d) y = %b (0x%0h)(%0d) ", a, a, a, y, y, y);
-        $monitor("time=%0t \t a=%b y=%b",$realtime, a, y);
+        $monitor("time=%0t \t a=%b y=%b", $realtime, a, out);
     end
 
     initial begin
         a <= #i'h8000;
+        #10
+        a <= #i'h1402;
+        #10
+        a <= #i'h24B7;
+        $finish;
     end
 
     signext uut(
-        .A(a), .Y(y)
+        .a(a), .out(out)
     );
 endmodule
 `endif // TB_SIGNEXT
\ No newline at end of file
diff --git a/catalog/sl2/sl2.sv b/catalog/sl2/sl2.sv
index 4cc60118..25397eb1 100644
--- a/catalog/sl2/sl2.sv
+++ b/catalog/sl2/sl2.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: Prof Rob Marano
+// Engineer: Isaac Moore, Morris Madeb
 // 
 //     Create Date: 2023-02-07
 //     Module Name: sl2
@@ -15,18 +15,17 @@
 
 `timescale 1ns/100ps
 
-module sl2
-    #(parameter n = 32)(
+module sl2 #(parameter n = 32)(
     //
     // ---------------- PORT DEFINITIONS ----------------
     //
-    input  logic [(n-1):0] A,
-    output logic [(n-1):0] Y
+    input  logic [(n-1):0] a,
+    output logic [(n-1):0] out
 );
     //
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
-    assign Y = {A[(n-3):0], 2'b00};
+    assign out = {a[(n-3):0], 2'b00};
 endmodule
 
-`endif // SL2
\ No newline at end of file
+`endif // SL2
diff --git a/catalog/sl2/tb_sl2.sv b/catalog/sl2/tb_sl2.sv
index 79fa9d6e..de943ecc 100644
--- a/catalog/sl2/tb_sl2.sv
+++ b/catalog/sl2/tb_sl2.sv
@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: Prof Rob Marano
+// Engineer: Prof Rob Marano, Isaac Moore
 // 
 //     Create Date: 2023-02-07
 //     Module Name: tb_sl2
@@ -18,21 +18,27 @@
 
 module tb_sl2;
     parameter n = 32;
-    logic [(n-1):0] a, y;
+    logic [(n-1):0] a, out;
 
-   initial begin
+    initial begin
         $dumpfile("sl2.vcd");
         $dumpvars(0, uut);
         //$monitor("a = %0b (0x%0h)(%0d) y = %0b (0x%0h)(%0d) ", a, a, a, y, y, y);
-        $monitor("time=%0t \t a=%b y=%b",$realtime, a, y);
+        $monitor("time=%0t \t a=%b y=%b",$realtime, a, out);
     end
 
     initial begin
         a <= #n'h0000000F;
+        #10
+        a <= #n'h01000001;
+        #10
+        a <= #n'h000A3128;
+        #10
+        $finish;
     end
 
     sl2 uut(
-        .A(a), .Y(y)
+        .a(a), .out(out)
     );
 endmodule
 `endif // TB_SL2
\ No newline at end of file
diff --git a/fib.asm b/fib.asm
new file mode 100644
index 00000000..72a47cf2
--- /dev/null
+++ b/fib.asm
@@ -0,0 +1,32 @@
+fibonacci: 
+  # Initialize loop counters
+  addi $4, $0, $1  
+  addi $5, $1, $0  
+
+loop:
+  sub $6, $2, $1  
+  j  fibonacci   
+  mfhi $3          
+
+  mult $5, $5, $1  
+  mflo $2          
+  add  $7, $3, $5  
+
+  slt  $8, $4, $2  
+  beqz $8, fib_end  
+
+  addi $4, $4, $1 
+  move $5, $7      
+
+  j loop            
+
+fib_zero:
+  addi $7, $0, $0 
+  j fib_end        
+
+fib_one:
+  addi $7, $1, $0 
+  j fib_end        
+
+fib_end:
+  j $ra