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Avalon byteenable and readonly phase exception #8

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BZab opened this issue Dec 29, 2020 · 0 comments
Open

Avalon byteenable and readonly phase exception #8

BZab opened this issue Dec 29, 2020 · 0 comments

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@BZab
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BZab commented Dec 29, 2020

CocoTB: 1.4.0
Python: 3.8.0

I was writing simple TB for my Avalon MM coprocessor. I encountered 3 problems:

  1. TB crashed with "Write to object {} was scheduled during a read-only sync phase." exception
  2. Avalon specifies byteenable signal as optional, lack of which CocoTB's Avalon classes doesn't support
  3. CocoTB's Avalon classes support random wait request, but do not random pauses during burst read

I was able to fix first one, basing on issue 537.
Since right now CocoTB's classes only support full word access I added quick & dirty workaround allowing to use it with designs without byteenable signal.
However, I didn't manage to add random pauses in read burst from Avalon Memory.

Here's small patch:

--- avalon.py	2020-12-29 23:06:58.304282481 +0100
+++ avalon_mod.py	2020-12-29 23:05:01.995759029 +0100
@@ -334,12 +334,15 @@
                            "(addr = " + hex(addr) +
                            ", width = " + str(self._width))
 
-        byteenable = self.bus.byteenable.value
-        if byteenable != int("1"*len(self.bus.byteenable), 2):
-            self.log.error("Only full word access is supported " +
-                           "for burst write (byteenable must be " +
-                           "0b" + "1" * len(self.bus.byteenable) +
-                           ")")
+        if not hasattr(self.bus, "byteenable"):
+            byteenable = int("1"*int(self._width/8), 2)
+        else:
+            byteenable = self.bus.byteenable.value
+            if byteenable != int("1"*len(self.bus.byteenable), 2):
+                self.log.error("Only full word access is supported " +
+                               "for burst write (byteenable must be " +
+                               "0b" + "1" * len(self.bus.byteenable) +
+                               ")")
 
         burstcount = self.bus.burstcount.value.integer
         if burstcount == 0:
@@ -363,8 +366,10 @@
                 randmax = self._avalon_properties.get("MaxWaitReqLen", 0)
                 waitingtime = range(random.randint(0, randmax))
                 for waitreq in waitingtime:
+                    await NextTimeStep()
                     self.bus.waitrequest <= 1
                     await RisingEdge(self.clock)
+                await NextTimeStep()
             else:
                 await NextTimeStep()
 
@@ -399,12 +404,15 @@
                                        ", width = " + str(self._width))
                     addr = int(addr / self.dataByteSize)
                     burstcount = self.bus.burstcount.value.integer
-                    byteenable = self.bus.byteenable.value
-                    if byteenable != int("1"*len(self.bus.byteenable), 2):
-                        self.log.error("Only full word access is supported " +
-                                       "for burst read (byteenable must be " +
-                                       "0b" + "1" * len(self.bus.byteenable) +
-                                       ")")
+                    if not hasattr(self.bus, "byteenable"):
+                        byteenable = int("1"*int(self._width/8), 2)
+                    else:
+                        byteenable = self.bus.byteenable.value
+                        if byteenable != int("1"*len(self.bus.byteenable), 2):
+                            self.log.error("Only full word access is supported " +
+                                           "for burst read (byteenable must be " +
+                                           "0b" + "1" * len(self.bus.byteenable) +
+                                           ")")
                     if burstcount == 0:
                         self.log.error("Burstcount must be 1 at least")
@ktbarrett ktbarrett transferred this issue from cocotb/cocotb Jan 30, 2021
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