Avalon MM Master read capturing readdata from unexpected clock cycle

[saachisen]

Hello,

I'm attempting to read an avalon mm bus using the read method of the AvalonMaster driver:

readdata = await amm.read(addr)

In my waveforms, I can see that the amm_address changes, amm_read goes high, then a few clock cycles later, amm_waitrequest goes low and amm_readdata changes to value A. One clock cycle after that, amm_waitrequest goes high and amm_readdata changes to value B. The read method returns me value B, when I was expecting value A.

If I manually carry out an avalon mm read (assign dut.amm_address, assign dut.amm_read to 1, wait for dut.amm_waitrequest to fall, wait until the next rising edge of dut.amm_clk and then capture dut.amm_readdata), I get value A. We also have vhdl and system verilog sim drivers that return value A.

It's like the read method is sampling readdata marginally late... has anyone else come across this? I have zoomed in as far as I can on my waveforms and everything looks to be changing exactly on the clock, no visible delta.

Happening with Modelsim and Questa (64bit) .

Thanks

[ktbarrett]

This belongs in cocotb-bus, so I'm transferring it.

[ktbarrett]

I have zoomed in as far as I can on my waveforms and everything looks to be changing exactly on the clock, no visible delta.

In the Questa waveform viewer there is an button that will allow you to expand time at your cursor into delta cycles. I don't think Questa will show you delta blips by just zooming in.

Did you try with a different simulator? Is it only Questa?

[marlonjames]

The cause is the await ReadOnly() before getting the value:

cocotb-bus/src/cocotb_bus/drivers/avalon.py

Lines 135 to 148 in a3e22f7

	if hasattr(self.bus, "readdatavalid"):
	while True:
	await ReadOnly()
	if int(self.bus.readdatavalid):
	break
	await RisingEdge(self.clock)
	else:
	# Assume readLatency = 1 if no readdatavalid
	# FIXME need to configure this,
	# should take a dictionary of Avalon properties.
	await ReadOnly()
	# Get the data
	data = self.bus.readdata.value

I don't understand why this is in the bus drivers. As noted it doesn't match the behavior of HDL.