From 423cfcc70553c008a6d2b48eeda3bb79100c0d5b Mon Sep 17 00:00:00 2001 From: ckf104 <1900011634@pku.edu.cn> Date: Mon, 8 Jan 2024 10:50:58 +0800 Subject: [PATCH] misc: fix pre-commit warnings Change-Id: Iaab990ad265f327d0df397b1bd7bd2f3e40f4a79 --- .gitignore | 2 +- README_Zh.md | 49 ++++----- configs/custom/riscv-floating-counter.py | 4 +- configs/custom/riscv-floating.py | 4 +- src/cpu/minor/SConscript | 8 +- src/cpu/minor/custom.cc | 8 +- src/cpu/minor/custom.hh | 8 +- src/cpu/minor/execute.cc | 2 +- src/custom/CustomCounter.py | 6 +- src/custom/CustomObj.py | 5 +- src/custom/SConscript | 1 - src/custom/custom_counter.cc | 22 ++-- src/custom/custom_counter.hh | 10 +- src/custom/custom_obj.cc | 16 +-- src/custom/custom_obj.hh | 14 +-- trace.vcd | 128 ----------------------- 16 files changed, 72 insertions(+), 215 deletions(-) delete mode 100644 trace.vcd diff --git a/.gitignore b/.gitignore index 88df23658a..4a22b21a8c 100644 --- a/.gitignore +++ b/.gitignore @@ -37,4 +37,4 @@ ext/custom/model_counter/libVerilatorCounter.so ext/custom/libVerilatorCounter.so ext/custom/custom_packet_counter.hh ext/custom/wrapper_counter.hh -trace.vcd \ No newline at end of file +trace.vcd diff --git a/README_Zh.md b/README_Zh.md index 92ae538da5..4ca5681b4f 100644 --- a/README_Zh.md +++ b/README_Zh.md @@ -54,7 +54,7 @@ else if (decoded_inst->isFloating()) > > ### commit > -> +> > > pop LSQ阶段： > @@ -62,9 +62,9 @@ else if (decoded_inst->isFloating()) > if (completed_inst && (inst->isMemRef() || inst->isFloating() )) > ~~~ > -> > -> +> +> ### 添加函数 @@ -101,7 +101,7 @@ MinorCPU cpu_, *this, ), - + ~~~ execute的include @@ -160,7 +160,7 @@ execute的include > > ~~~c++ > custominst_port = RequestPort("CustomInst Port") -> +> > _cached_ports = ["icache_port", "dcache_port", "custominst_port"] > ~~~ > @@ -169,9 +169,9 @@ execute的include > ~~~c++ > else if (if_name == "custominst_port") > return getCustPort(); -> -> -> +> +> +> > getCustPort().takeOverFrom(&oldCPU->getCustPort()); > ~~~ > @@ -180,15 +180,15 @@ execute的include > ~~~c++ > /** Custom*/ > virtual Port &getCustPort() = 0; -> -> -> -> +> +> +> +> > ~~~ > -> > -> +> +> @@ -347,13 +347,13 @@ scons build/RISCV/gem5.opt ## 运行gem5 ~~~c++ -build/RISCV/gem5.opt configs/custom/riscv-floating.py +build/RISCV/gem5.opt configs/custom/riscv-floating.py ~~~ 打开debug ~~~bash -build/RISCV/gem5.opt --debug-flags=CustomObj configs/custom/riscv-floating.py +build/RISCV/gem5.opt --debug-flags=CustomObj configs/custom/riscv-floating.py ~~~ @@ -361,7 +361,7 @@ build/RISCV/gem5.opt --debug-flags=CustomObj configs/custom/riscv-floating.py 运行counter ~~~bash -build/RISCV/gem5.opt --debug-flags=CustomObj configs/custom/riscv-floating-counter.py +build/RISCV/gem5.opt --debug-flags=CustomObj configs/custom/riscv-floating-counter.py ~~~ @@ -387,7 +387,7 @@ ext/custom/SConscript里面库路径还用的绝对路径，还待解决 报错 ~~~bash -root@CsxDesktop:/home/csx/workland/mycode/gem5-custom# build/RISCV/gem5.opt --debug-flags=CustomObj configs/custom/riscv-floating-counter.py +root@CsxDesktop:/home/csx/workland/mycode/gem5-custom# build/RISCV/gem5.opt --debug-flags=CustomObj configs/custom/riscv-floating-counter.py build/RISCV/gem5.opt: error while loading shared libraries: libVerilatorCounter.so: cannot open shared object file: No such file or directory ~~~ @@ -396,16 +396,3 @@ build/RISCV/gem5.opt: error while loading shared libraries: libVerilatorCounter. ~~~bash export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/home/csx/workland/mycode/gem5_custom/ext/custom ~~~ - - - - - - - - - - - - - diff --git a/configs/custom/riscv-floating-counter.py b/configs/custom/riscv-floating-counter.py index 0415e5d227..378f9b2fb8 100644 --- a/configs/custom/riscv-floating-counter.py +++ b/configs/custom/riscv-floating-counter.py @@ -58,7 +58,7 @@ system.system_port = system.membus.cpu_side_ports -#system.custom.custominst_port = system.membus.cpu_side_ports +# system.custom.custominst_port = system.membus.cpu_side_ports system.cpu.custominst_port = system.counter.counter_port @@ -75,7 +75,7 @@ thispath, "../../", "custom_test/float" - #"tests/test-progs/hello/bin/riscv/linux/hello", + # "tests/test-progs/hello/bin/riscv/linux/hello", ) system.workload = SEWorkload.init_compatible(binary) diff --git a/configs/custom/riscv-floating.py b/configs/custom/riscv-floating.py index 74ce2b5fbc..cc37fc9276 100644 --- a/configs/custom/riscv-floating.py +++ b/configs/custom/riscv-floating.py @@ -58,7 +58,7 @@ system.system_port = system.membus.cpu_side_ports -#system.custom.custominst_port = system.membus.cpu_side_ports +# system.custom.custominst_port = system.membus.cpu_side_ports system.cpu.custominst_port = system.custom.custominst_port @@ -75,7 +75,7 @@ thispath, "../../", "custom_test/float" - #"tests/test-progs/hello/bin/riscv/linux/hello", + # "tests/test-progs/hello/bin/riscv/linux/hello", ) system.workload = SEWorkload.init_compatible(binary) diff --git a/src/cpu/minor/SConscript b/src/cpu/minor/SConscript index 6f6abbea3e..60d414eee1 100644 --- a/src/cpu/minor/SConscript +++ b/src/cpu/minor/SConscript @@ -45,7 +45,7 @@ if not env['CONF']['USE_NULL_ISA']: 'MinorOpClass', 'MinorOpClassSet', 'MinorFUTiming', 'MinorFU', 'MinorFUPool', 'BaseMinorCPU'], enums=['ThreadPolicy']) - + Source('activity.cc') @@ -61,10 +61,10 @@ if not env['CONF']['USE_NULL_ISA']: Source('pipeline.cc') Source('scoreboard.cc') Source('stats.cc') - + Source('custom.cc') - + DebugFlag('MinorCPU', 'Minor CPU-level events') DebugFlag('MinorExecute', 'Minor Execute stage') @@ -74,7 +74,7 @@ if not env['CONF']['USE_NULL_ISA']: DebugFlag('MinorTrace', 'MinorTrace cycle-by-cycle state trace') DebugFlag('MinorTiming', 'Extra timing for instructions') - + CompoundFlag('Minor', [ 'MinorCPU', 'MinorExecute', 'MinorInterrupt', 'MinorMem', diff --git a/src/cpu/minor/custom.cc b/src/cpu/minor/custom.cc index 234c38c0cf..1494ec340d 100644 --- a/src/cpu/minor/custom.cc +++ b/src/cpu/minor/custom.cc @@ -45,7 +45,7 @@ Custom::SendToRTL(MinorDynInstPtr inst) Custom::tryToSend(packet); } -bool +bool Custom::tryToSend(PacketPtr pkt) { DPRINTF(CustomObj, "customInstPort sendTimingReq:%d\n", curTick()); @@ -55,7 +55,7 @@ Custom::tryToSend(PacketPtr pkt) return false; } -void +void Custom::recvReqRetry() { DPRINTF(CustomObj, "customInstPort recvReqRetry:%d\n", curTick()); @@ -63,7 +63,7 @@ Custom::recvReqRetry() } -Port & +Port & Custom::getPort(const std::string &if_name, PortID idx) { if (if_name == "custominst_port") @@ -75,5 +75,3 @@ Custom::getPort(const std::string &if_name, PortID idx) } //End namespace minor } //End namespace gem5 - - diff --git a/src/cpu/minor/custom.hh b/src/cpu/minor/custom.hh index 9934074013..d944fe2d76 100644 --- a/src/cpu/minor/custom.hh +++ b/src/cpu/minor/custom.hh @@ -14,7 +14,7 @@ namespace gem5 { - + namespace minor { @@ -36,7 +36,7 @@ class Custom : public Named CustomInstPort(std::string name, Custom &custom_, MinorCPU &cpu) : MinorCPU::MinorCPUPort(name, cpu), custom(custom_) { } - + protected: bool recvTimingResp(PacketPtr ptk) override { panic("dont imp recvTimingResp"); } @@ -73,7 +73,7 @@ class Custom : public Named void SendToRTL(MinorDynInstPtr inst); Port & getPort(const std::string &if_name, PortID idx=InvalidPortID); - + @@ -90,4 +90,4 @@ class Custom : public Named -#endif \ No newline at end of file +#endif diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc index 12d1075ab2..e47a647192 100644 --- a/src/cpu/minor/execute.cc +++ b/src/cpu/minor/execute.cc @@ -1914,7 +1914,7 @@ Execute::getCustPort() } /* */ -void +void Execute::SendToCustom(MinorDynInstPtr inst) { DPRINTF(CustomObj, "SendToCustom[%d]\n", curTick()); diff --git a/src/custom/CustomCounter.py b/src/custom/CustomCounter.py index 991e258286..d1c053e3ff 100644 --- a/src/custom/CustomCounter.py +++ b/src/custom/CustomCounter.py @@ -1,12 +1,12 @@ - from m5.params import * from m5.proxy import * from m5.SimObject import SimObject from m5.objects.CustomObj import CustomObj + class CustomCounter(CustomObj): - type = 'CustomCounter' + type = "CustomCounter" cxx_header = "custom/custom_counter.hh" cxx_class = "gem5::CustomCounter" - counter_port = ResponsePort("CPU side port, receives custom inst") \ No newline at end of file + counter_port = ResponsePort("CPU side port, receives custom inst") diff --git a/src/custom/CustomObj.py b/src/custom/CustomObj.py index 3afa6cc451..8addfe0d40 100644 --- a/src/custom/CustomObj.py +++ b/src/custom/CustomObj.py @@ -2,9 +2,10 @@ from m5.proxy import * from m5.SimObject import SimObject + class CustomObj(SimObject): - type = 'CustomObj' + type = "CustomObj" cxx_header = "custom/custom_obj.hh" cxx_class = "gem5::CustomObj" - custominst_port = ResponsePort("CPU side port, receives custom inst") \ No newline at end of file + custominst_port = ResponsePort("CPU side port, receives custom inst") diff --git a/src/custom/SConscript b/src/custom/SConscript index c2dcd04991..ec49e3d75f 100644 --- a/src/custom/SConscript +++ b/src/custom/SConscript @@ -8,4 +8,3 @@ Source('custom_obj.cc') Source('custom_counter.cc') DebugFlag('CustomObj', "Custom Inst") - diff --git a/src/custom/custom_counter.cc b/src/custom/custom_counter.cc index 0b44878dbb..e0e71e89e7 100644 --- a/src/custom/custom_counter.cc +++ b/src/custom/custom_counter.cc @@ -38,7 +38,7 @@ CustomCounter::CPUSidePort::getAddrRanges() const return owner->getAddrRanges(); } -void +void CustomCounter::CPUSidePort::recvFunctional(PacketPtr pkt) { return owner->recvFunctional(pkt); @@ -55,7 +55,7 @@ CustomCounter::CPUSidePort::recvTimingReq(PacketPtr pkt) } } -void +void CustomCounter::CPUSidePort::sendPacket(PacketPtr pkt) { panic_if(blockedPacket != nullptr, "Should never try to send if blocked!\n"); @@ -86,16 +86,16 @@ CustomCounter::CPUSidePort::trySendRetry() } -AddrRangeList +AddrRangeList CustomCounter::getAddrRanges() const { - + } -void +void CustomCounter::recvFunctional(PacketPtr pkt) { - + } //---------------------------// @@ -125,7 +125,7 @@ CustomCounter::handleInst() assert(blocked); DPRINTF(CustomObj, "handle float inst at %d \n", curTick()); reset(); - + input.ena = 1; input.rst = 0; tick(); @@ -145,7 +145,7 @@ void CustomCounter::tick() { DPRINTF(CustomObj, "tick at %d \n", curTick()); - + outputCounter out = wr->tick(input); DPRINTF(CustomObj, "out.cnt = %d \n", out.cnt); @@ -174,7 +174,7 @@ CustomCounter::reset() wr->reset(); } -void +void CustomCounter::initRTLModel() { //traceOn = true @@ -184,7 +184,7 @@ CustomCounter::initRTLModel() //DPRINTF(CustomObj, "out.cnt = %d \n", curTick()); } -void +void CustomCounter::endRTLModel() { DPRINTF(CustomObj, "endRTLModel at %d \n", curTick()); @@ -195,4 +195,4 @@ CustomCounter::endRTLModel() -} \ No newline at end of file +} diff --git a/src/custom/custom_counter.hh b/src/custom/custom_counter.hh index 3474667800..7d4473cf95 100644 --- a/src/custom/custom_counter.hh +++ b/src/custom/custom_counter.hh @@ -12,7 +12,7 @@ namespace gem5 { - + class CustomCounter : public CustomObj { private: @@ -31,7 +31,7 @@ class CustomCounter : public CustomObj PacketPtr blockedPacket; public: - CPUSidePort(const std::string& name, CustomCounter *owner) : + CPUSidePort(const std::string& name, CustomCounter *owner) : ResponsePort(name) ,owner(owner), needRetry(false), blockedPacket(nullptr) { } @@ -49,7 +49,7 @@ class CustomCounter : public CustomObj bool handleRequest(PacketPtr pkt);//override; //bool handleResponse(PacketPtr pkt); - void recvFunctional(PacketPtr pkt);//override; + void recvFunctional(PacketPtr pkt);//override; bool needRetry; AddrRangeList getAddrRanges() const; @@ -62,7 +62,7 @@ class CustomCounter : public CustomObj CustomCounter(const CustomCounterParams ¶ms); ~CustomCounter(); Port &getPort(const std::string &if_name, PortID idx=InvalidPortID) override; - + //wrapper pointer Wrapper_counter *wr; @@ -86,4 +86,4 @@ class CustomCounter : public CustomObj } -#endif \ No newline at end of file +#endif diff --git a/src/custom/custom_obj.cc b/src/custom/custom_obj.cc index 08fdc3256f..284fd8279f 100644 --- a/src/custom/custom_obj.cc +++ b/src/custom/custom_obj.cc @@ -33,7 +33,7 @@ CustomObj::CPUSidePort::getAddrRanges() const return owner->getAddrRanges(); } -void +void CustomObj::CPUSidePort::recvFunctional(PacketPtr pkt) { return owner->recvFunctional(pkt); @@ -50,7 +50,7 @@ CustomObj::CPUSidePort::recvTimingReq(PacketPtr pkt) } } -void +void CustomObj::CPUSidePort::sendPacket(PacketPtr pkt) { panic_if(blockedPacket != nullptr, "Should never try to send if blocked!\n"); @@ -81,16 +81,16 @@ CustomObj::CPUSidePort::trySendRetry() } -AddrRangeList +AddrRangeList CustomObj::getAddrRanges() const { - + } -void +void CustomObj::recvFunctional(PacketPtr pkt) { - + } bool @@ -111,7 +111,7 @@ handle custome inst return true; } -void +void CustomObj::handleInst() { assert(blocked); @@ -127,4 +127,4 @@ void CustomObj::finishInst() DPRINTF(CustomObj, "finish float inst at %d \n", curTick()); } -} //End gem5 namespace \ No newline at end of file +} //End gem5 namespace diff --git a/src/custom/custom_obj.hh b/src/custom/custom_obj.hh index 9c6f5e02c3..d815cef144 100644 --- a/src/custom/custom_obj.hh +++ b/src/custom/custom_obj.hh @@ -34,7 +34,7 @@ class CustomObj : public SimObject PacketPtr blockedPacket; public: - CPUSidePort(const std::string& name, CustomObj *owner) : + CPUSidePort(const std::string& name, CustomObj *owner) : ResponsePort(name) ,owner(owner), needRetry(false), blockedPacket(nullptr) { } @@ -55,13 +55,13 @@ class CustomObj : public SimObject }; - + bool handleRequest(PacketPtr pkt); //bool handleResponse(PacketPtr pkt); void recvFunctional(PacketPtr pkt); - + bool needRetry; @@ -70,7 +70,7 @@ class CustomObj : public SimObject CPUSidePort instPort; bool blocked; - + public: @@ -82,14 +82,14 @@ class CustomObj : public SimObject //interface to RTL model //this function will call tick() in wrapper_xxx //virtual void tick(); - + //virtual void initRTLModel(); //virtual void endRTLModel(); - + }; } // End namespace gem5 -#endif +#endif diff --git a/trace.vcd b/trace.vcd deleted file mode 100644 index 15d1941bbd..0000000000 --- a/trace.vcd +++ /dev/null @@ -1,128 +0,0 @@ -$version Generated by VerilatedVcd $end -$date Mon Jan 8 09:45:16 2024 - $end -$timescale 1ps $end - - $scope module TOP $end - $var wire 1 # clk $end - $var wire 4 ' cnt [3:0] $end - $var wire 1 % ena $end - $var wire 1 & out $end - $var wire 1 $ rst $end - $scope module Top $end - $var wire 1 # clk $end - $var wire 4 ' cnt [3:0] $end - $var wire 1 % ena $end - $var wire 1 & out $end - $var wire 1 $ rst $end - $scope module counter $end - $var wire 1 # clk $end - $var wire 4 ' cnt [3:0] $end - $var wire 1 % ena $end - $var wire 1 & out $end - $var wire 1 $ rst $end - $upscope $end - $upscope $end - $upscope $end -$enddefinitions $end - - -#0 -1# -1$ -0% -0& -b0000 ' -#1 -0# -#2 -1# -1& -b1111 ' -#3 -0# -#4 -1# -0$ -1% -0& -b1110 ' -#5 -0# -#6 -1# -b1101 ' -#7 -0# -#8 -1# -b1100 ' -#9 -0# -#10 -1# -b1011 ' -#11 -0# -#12 -1# -b1010 ' -#13 -0# -#14 -1# -b1001 ' -#15 -0# -#16 -1# -b1000 ' -#17 -0# -#18 -1# -b0111 ' -#19 -0# -#20 -1# -b0110 ' -#21 -0# -#22 -1# -b0101 ' -#23 -0# -#24 -1# -b0100 ' -#25 -0# -#26 -1# -b0011 ' -#27 -0# -#28 -1# -b0010 ' -#29 -0# -#30 -1# -b0001 ' -#31 -0# -#32 -1# -b0000 ' -#33 -0# -#34 -1# -1& -b1111 ' -#35 -0# -#36