Formatter is confused by macros

[isaacde]

Test case

I'm trying to get the formatter working with legacy verilog code. Here is a simple example that will generate the syntax parsing / token issues I've seen:

`define FDLY 0.1
`define always_pe_ne(clk,rst_n) always @(posedge clk or negedge rst_n)

module verible_formatter_token_defines #(
) (
    input logic clk,
    input logic rst_n
);

  logic [3:0] countA, countB, countC, countD;

  always_ff @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
    countA <= 0;
    countB <= 0;
    end else begin
      countA <= #(`FDLY) (countA + 1);
      countB <= #`FDLY (countB + 1); // verible_formatter_token_defines.sv:18:18-22: syntax error at token "`FDLY"
    end
  end

  `always_pe_ne(clk, rst_n) 
  begin
    if (~rst_n) begin
      countC <= 0;
    end else begin
      countC <= countC + 1;
    end
  end

  `always_pe_ne(clk, rst_n) begin
    if (~rst_n) begin
      countD <= 0;
    end else begin
      countD <= countD + 1;
    end
  end
endmodule

verible-verilog-format diagnostic output:

$ verible-verilog-format verible_formatter_token_defines.sv
I1107 08:40:21.374077   20811 verilog_analyzer.cc:132] AnalyzeAutomaticMode
I1107 08:40:21.374202   20811 text_structure.cc:393] FastLineRangeConsistencyCheck
I1107 08:40:21.374273   20811 text_structure.cc:338] FastTokenRangeConsistencyCheck
I1107 08:40:21.374293   20811 text_structure.cc:408] SyntaxTreeConsistencyCheck
I1107 08:40:21.374311   20811 text_structure.cc:393] FastLineRangeConsistencyCheck
I1107 08:40:21.374331   20811 text_structure.cc:338] FastTokenRangeConsistencyCheck
I1107 08:40:21.374351   20811 text_structure.cc:408] SyntaxTreeConsistencyCheck
I1107 08:40:21.375039   20811 parser_param.cc:51] verible_formatter_token_defines.sv: recovered syntax error: (#297: "`FDLY")
I1107 08:40:21.375091   20811 bison_parser_common.cc:41] verible_formatter_token_defines.sv: verilog_parse error: syntax error
I1107 08:40:21.375158   20811 parser_param.cc:51] verible_formatter_token_defines.sv: recovered syntax error: (#663: "<=")
I1107 08:40:21.375192   20811 bison_parser_common.cc:41] verible_formatter_token_defines.sv: verilog_parse error: syntax error
I1107 08:40:21.375221   20811 parser_param.cc:51] verible_formatter_token_defines.sv: recovered syntax error: (#663: "<=")
I1107 08:40:21.375284   20811 bison_parser_common.cc:41] verible_formatter_token_defines.sv: verilog_parse error: syntax error
I1107 08:40:21.375318   20811 parser_param.cc:51] verible_formatter_token_defines.sv: recovered syntax error: (#320: "begin")
I1107 08:40:21.375367   20811 bison_parser_common.cc:41] verible_formatter_token_defines.sv: verilog_parse error: syntax error
I1107 08:40:21.375391   20811 parser_param.cc:51] verible_formatter_token_defines.sv: recovered syntax error: (#334: "end")
I1107 08:40:21.375441   20811 bison_parser_common.cc:41] verible_formatter_token_defines.sv: verilog_parse error: syntax error
I1107 08:40:21.375487   20811 parser_param.cc:51] verible_formatter_token_defines.sv: recovered syntax error: (#334: "end")
I1107 08:40:21.375523   20811 bison_parser_common.cc:41] verible_formatter_token_defines.sv: verilog_parse error: syntax error
I1107 08:40:21.375565   20811 bison_parser_adapter.h:53] max_used_stack_size : 0
I1107 08:40:21.375603   20811 verilog_analyzer.cc:157] Error analyzing verilog.
I1107 08:40:21.375625   20811 verilog_analyzer.cc:167] Retrying parsing in mode: "".
I1107 08:40:21.375646   20811 verilog_analyzer.cc:200] end of AnalyzeAutomaticMode
I1107 08:40:21.375700   20811 text_structure.cc:393] FastLineRangeConsistencyCheck
I1107 08:40:21.375733   20811 text_structure.cc:338] FastTokenRangeConsistencyCheck
I1107 08:40:21.375757   20811 text_structure.cc:408] SyntaxTreeConsistencyCheck
`define FDLY 0.1
`define always_pe_ne(clk,rst_n) always @(posedge clk or negedge rst_n)

module verible_formatter_token_defines #(
) (
    input logic clk,
    input logic rst_n
);

  logic [3:0] countA, countB, countC, countD;

  always_ff @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
    countA <= 0;
    countB <= 0;
    end else begin
      countA <= #(`FDLY) (countA + 1);
      countB <= #`FDLY (countB + 1);
    end
  end

  `always_pe_ne(clk, rst_n) 
  begin
    if (~rst_n) begin
      countC <= 0;
    end else begin
      countC <= countC + 1;
    end
  end

  `always_pe_ne(clk, rst_n) begin
    if (~rst_n) begin
      countD <= 0;
    end else begin
      countD <= countD + 1;
    end
  end
endmodule
verible_formatter_token_defines.sv: verible_formatter_token_defines.sv:18:18-22: syntax error at token "`FDLY"
verible_formatter_token_defines.sv:25:14-15: syntax error at token "<="
verible_formatter_token_defines.sv:27:14-15: syntax error at token "<="
verible_formatter_token_defines.sv:31:29-33: syntax error at token "begin"
verible_formatter_token_defines.sv:34:5-7: syntax error at token "end"
verible_formatter_token_defines.sv:36:5-7: syntax error at token "end"

Expected behavior

• brackets around the RHS after <= #delay should not behave differently than if there were no brackets
• begin should be paired with end and whether it is on the same line or next line to a macro should not cause syntax errors