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The code below raises an error but is valid according to the LMR
To Reproduce
classtest;
bit [31:0] pattern;
constraintpattern_c{foreach (pattern[i]) if (i!=0) if (i<16) {pattern[15:0],pattern[15:0]}[i+:16] != pattern[15:0];
}endclass
Called with
> verible-verilog-lint test.sv
Version (to be tried on a newer version)
> verible-verilog-lint --version
v0.0-3481-gc517d611
Commit 2024-01-05
Built 2024-01-05T17:03:26Z
Actual behavior:
Reject valid syntax by returning an error.
The problem is the selection of the concatenation.
> verible-verilog-lint test.sv
test.sv:4:75: syntax error at token "["
test.sv:5:3: syntax error at token "}"
Expected behavior
As indicated in LRM 11.4.12
One or more bits of a concatenation can be selected as if the concatenation were a packed array with the range [n-1:0].
The text was updated successfully, but these errors were encountered:
Describe the bug
The code below raises an error but is valid according to the LMR
To Reproduce
Called with
Version (to be tried on a newer version)
Actual behavior:
Reject valid syntax by returning an error.
The problem is the selection of the concatenation.
Expected behavior
As indicated in
LRM 11.4.12
The text was updated successfully, but these errors were encountered: