diff --git a/common/analysis/linter_test_utils.h b/common/analysis/linter_test_utils.h
index 58d35d404..519de3a72 100644
--- a/common/analysis/linter_test_utils.h
+++ b/common/analysis/linter_test_utils.h
@@ -81,20 +81,29 @@ void RunLintTestCase(const LintTestCase& test,
       << absl::StrCat("code:\n", test.code, "\nDiffs:\n", diffs.str(), "\n");
 }
 
-// Accepts an array of LintTestCases and tests them all on a linter
-// containing rule generated by make_rule
+// Accepts an array of LintTestCases and tests them all on a linter containing
+// rule generated by make_rule with a particular configuration.
 template <class AnalyzerType, class RuleClass>
-void RunLintTestCases(std::initializer_list<LintTestCase> tests,
-                      const std::string& filename = "<<inline-test>>") {
+void RunConfiguredLintTestCases(
+    std::initializer_list<LintTestCase> tests, absl::string_view configuration,
+    const std::string& filename = "<<inline-test>>") {
   typedef typename RuleClass::rule_type rule_type;
-  auto rule_generator = []() {
-    return std::unique_ptr<rule_type>(new RuleClass());
+  auto rule_generator = [&configuration]() -> std::unique_ptr<rule_type> {
+    std::unique_ptr<rule_type> instance(new RuleClass());
+    absl::Status config_status = instance->Configure(configuration);
+    CHECK(config_status.ok()) << config_status.message();
+    return instance;
   };
   for (const auto& test : tests) {
     RunLintTestCase<AnalyzerType, rule_type>(test, rule_generator, filename);
   }
 }
 
+template <class AnalyzerType, class RuleClass>
+void RunLintTestCases(std::initializer_list<LintTestCase> tests,
+                      const std::string& filename = "<<inline-test>>") {
+  RunConfiguredLintTestCases<AnalyzerType, RuleClass>(tests, "", filename);
+}
 }  // namespace verible
 
 #endif  // VERIBLE_COMMON_ANALYSIS_LINTER_TEST_UTILS_H_
diff --git a/verilog/analysis/checkers/line_length_rule_test.cc b/verilog/analysis/checkers/line_length_rule_test.cc
index 19850fd66..9892897c1 100644
--- a/verilog/analysis/checkers/line_length_rule_test.cc
+++ b/verilog/analysis/checkers/line_length_rule_test.cc
@@ -31,6 +31,7 @@ namespace analysis {
 namespace {
 
 using verible::LintTestCase;
+using verible::RunConfiguredLintTestCases;
 using verible::RunLintTestCases;
 
 TEST(LineLengthRuleTest, Configuration) {
@@ -189,6 +190,15 @@ TEST(LineLengthRuleTest, RejectsText) {
   RunLintTestCases<VerilogAnalyzer, LineLengthRule>(kTestCases);
 }
 
+TEST(LineLengthRuleTest, RejectsTextConfigured) {
+  const std::initializer_list<LintTestCase> kTestCases = {
+      {"aaaaaaaaaabbbbbbbbbbcccc cccccdddddddddd", {TK_OTHER, "X"}, "\n"},
+      {"aaaaaaaaaabbbbbbbbbbcccc cccccdddddddddd\n"},  // shorter line ok.
+  };
+  RunConfiguredLintTestCases<VerilogAnalyzer, LineLengthRule>(kTestCases,
+                                                              "length:40");
+}
+
 #if 0
 TEST(LineLengthRuleTest, Encrypted) {
   const LintTestCase kTestCases[] = {