From 5db140893a74142ee874f922f1d9ab4322a128ae Mon Sep 17 00:00:00 2001
From: Ignacio Encinas <ignacioencinasrubio@gmail.com>
Date: Thu, 15 Feb 2024 22:04:33 +0100
Subject: [PATCH] lint: remove false positives from uvm-macro-semicolon

Macros like `UVM_REG_DATA_WIDTH were being flagged by the rule when they
shouldn't.

To the best of my knowledge, the only UVM macros that are parsed like
`MacroIdentifier` and should be flagged are the ones ending with `_end`:

  `uvm_component_utils_end
  `uvm_error_context_end
  ...
---
 .../checkers/uvm_macro_semicolon_rule.cc         | 16 +++++++++++++---
 .../checkers/uvm_macro_semicolon_rule_test.cc    |  9 +++++++++
 2 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/verilog/analysis/checkers/uvm_macro_semicolon_rule.cc b/verilog/analysis/checkers/uvm_macro_semicolon_rule.cc
index 3e7bc9d1c..379dcb268 100644
--- a/verilog/analysis/checkers/uvm_macro_semicolon_rule.cc
+++ b/verilog/analysis/checkers/uvm_macro_semicolon_rule.cc
@@ -55,11 +55,21 @@ static std::string FormatReason(const verible::TokenInfo &macro_id) {
 
 // Returns true if leaf is a macro and matches `uvm_
 static bool IsUvmMacroId(const verible::SyntaxTreeLeaf &leaf) {
+  const absl::string_view text = leaf.get().text();
+  const bool starts_with_uvm = absl::StartsWithIgnoreCase(text, "`uvm_");
+
   if (leaf.Tag().tag == verilog_tokentype::MacroCallId ||
-      leaf.Tag().tag == verilog_tokentype::MacroIdItem ||
-      leaf.Tag().tag == verilog_tokentype::MacroIdentifier) {
-    return absl::StartsWithIgnoreCase(leaf.get().text(), "`uvm_");
+      leaf.Tag().tag == verilog_tokentype::MacroIdItem) {
+    return starts_with_uvm;
+  }
+
+  const bool ends_with_end = absl::EndsWithIgnoreCase(text, "_end");
+  // We don't want to complain about macros like:
+  // `UVM_DEFAULT_TIMEOUT, UVM_MAX_STREAMBITS, ...
+  if (leaf.Tag().tag == verilog_tokentype::MacroIdentifier) {
+    return starts_with_uvm && ends_with_end;
   }
+
   return false;
 }
 
diff --git a/verilog/analysis/checkers/uvm_macro_semicolon_rule_test.cc b/verilog/analysis/checkers/uvm_macro_semicolon_rule_test.cc
index db9f69464..1ac39f425 100644
--- a/verilog/analysis/checkers/uvm_macro_semicolon_rule_test.cc
+++ b/verilog/analysis/checkers/uvm_macro_semicolon_rule_test.cc
@@ -43,6 +43,15 @@ TEST(UvmMacroSemicolonRuleTest, BaseTests) {
   RunLintTestCases<VerilogAnalyzer, UvmMacroSemicolonRule>(kTestCases);
 }
 
+TEST(UvmMacroSemicolonRuleTest, NoFalsePositivesTest) {
+  const std::initializer_list<LintTestCase> kTestCases = {
+      {"module m;\nint k = `UVM_DEFAULT_TIMEOUT; endmodule\n"},
+      {"module m;\nbit [63:0] k = `UVM_REG_ADDR_WIDTH'(0); endmodule\n"},
+  };
+
+  RunLintTestCases<VerilogAnalyzer, UvmMacroSemicolonRule>(kTestCases);
+}
+
 TEST(UvmMacroSemicolonRuleTest, AcceptedUvmMacroCallTests) {
   const std::initializer_list<LintTestCase> kTestCases = {
       // Function/Task scope