diff --git a/tilelink/src/utils/package.scala b/tilelink/src/utils/package.scala
deleted file mode 100644
index 7035889..0000000
--- a/tilelink/src/utils/package.scala
+++ /dev/null
@@ -1,35 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-// Copyright 2016-2017 SiFive, Inc.
-
-import chisel3._
-
-import scala.annotation.tailrec
-import scala.math.min
-
-package object utils {
-  // Fill 1s from low bits to high bits
-  def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
-
-  def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
-    val stop = min(width, cap)
-
-    @tailrec
-    def helper(s: Int, x: UInt): UInt =
-      if (s >= stop) x else helper(s + s, x | (x << s)(width - 1, 0))
-
-    helper(1, x)(width - 1, 0)
-  }
-
-  // Fill 1s form high bits to low bits
-  def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
-
-  def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
-    val stop = min(width, cap)
-
-    @tailrec
-    def helper(s: Int, x: UInt): UInt =
-      if (s >= stop) x else helper(s + s, x | (x >> s)(width - 1, 0))
-
-    helper(1, x)(width - 1, 0)
-  }
-}
diff --git a/tilelink/src/xbar/TLArbiter.scala b/tilelink/src/xbar/TLArbiter.scala
index 7cf30b9..e16c96d 100644
--- a/tilelink/src/xbar/TLArbiter.scala
+++ b/tilelink/src/xbar/TLArbiter.scala
@@ -47,8 +47,8 @@ class TLArbiter(val parameter: TLArbiterParameter)
             val valid   = valids(width - 1, 0)
             assert(valid === valids)
             val mask    = RegInit(((BigInt(1) << width) - 1).U(width - 1, 0))
-            val filter  = Cat(valid & (~mask).asUInt, valid)
-            val unready = (rightOR(filter, width * 2, width) >> 1).asUInt | (mask << width).asUInt
+            val filter  = Cat(scanRightOr(valid & ~mask), valid)
+            val unready = (filter >> 1).asUInt | (mask << width).asUInt
             val readys  = (~((unready >> width).asUInt & unready(width - 1, 0))).asUInt
             when(select && valid.orR) {
               mask := scanLeftOr(readys & valid)