From 9b0db75a217fcfdd753f10e6e57a539372ecd40d Mon Sep 17 00:00:00 2001 From: Clo91eaf Date: Mon, 4 Nov 2024 14:35:50 +0800 Subject: [PATCH 1/4] [difftest] remove unused cycle --- difftest/offline_t1emu/src/difftest.rs | 15 +++------------ difftest/offline_t1rocketemu/src/difftest.rs | 15 +-------------- difftest/spike_rs/src/runner.rs | 15 ++------------- 3 files changed, 6 insertions(+), 39 deletions(-) diff --git a/difftest/offline_t1emu/src/difftest.rs b/difftest/offline_t1emu/src/difftest.rs index 454edb09e..bb29ffa42 100644 --- a/difftest/offline_t1emu/src/difftest.rs +++ b/difftest/offline_t1emu/src/difftest.rs @@ -25,19 +25,14 @@ impl Difftest { let event = self.dut.step()?; match event { - JsonEvents::SimulationStart { cycle } => { - self.runner.cycle = *cycle; - Ok(()) - } + JsonEvents::SimulationStart { cycle } => Ok(()), JsonEvents::SimulationStop { reason, cycle } => { anyhow::bail!("stop: simulation stopped at cycle {cycle}, reason {reason}") } JsonEvents::Issue { idx, cycle } => { - self.runner.cycle = *cycle; self.runner.peek_issue(&IssueEvent { idx: *idx, cycle: *cycle }) } JsonEvents::MemoryWrite { mask, data, lsu_idx, address, cycle } => { - self.runner.cycle = *cycle; self.runner.peek_memory_write(&MemoryWriteEvent { mask: mask.clone(), data: data.clone(), @@ -47,11 +42,9 @@ impl Difftest { }) } JsonEvents::LsuEnq { enq, cycle } => { - self.runner.cycle = *cycle; self.runner.update_lsu_idx(&LsuEnqEvent { enq: *enq, cycle: *cycle }) } JsonEvents::VrfWrite { issue_idx, vd, offset, mask, data, lane, cycle } => { - self.runner.cycle = *cycle; self.runner.peek_vrf_write(&VrfWriteEvent { issue_idx: *issue_idx, vd: *vd, @@ -63,12 +56,10 @@ impl Difftest { }) } JsonEvents::CheckRd { data, issue_idx, cycle } => { - self.runner.cycle = *cycle; self.runner.check_rd(&CheckRdEvent { data: *data, issue_idx: *issue_idx, cycle: *cycle }) } - JsonEvents::VrfScoreboardReport { count, issue_idx, cycle } => { - self.runner.cycle = *cycle; - self.runner.vrf_scoreboard_report(&VrfScoreboardReportEvent { + JsonEvents::VrfScoreboard { count, issue_idx, cycle } => { + self.runner.vrf_scoreboard(&VrfScoreboardEvent { count: *count, issue_idx: *issue_idx, cycle: *cycle, diff --git a/difftest/offline_t1rocketemu/src/difftest.rs b/difftest/offline_t1rocketemu/src/difftest.rs index 23fd39f24..7c31e8e93 100644 --- a/difftest/offline_t1rocketemu/src/difftest.rs +++ b/difftest/offline_t1rocketemu/src/difftest.rs @@ -25,10 +25,7 @@ impl Difftest { let event = self.dut.step()?; match event { - JsonEvents::SimulationStart { cycle } => { - self.runner.cycle = *cycle; - Ok(()) - } + JsonEvents::SimulationStart { cycle } => Ok(()), JsonEvents::SimulationStop { reason, cycle } => { anyhow::bail!("error: simulation stopped at cycle {cycle}, reason {reason}") } @@ -36,27 +33,21 @@ impl Difftest { anyhow::bail!("simulation quit successfullly cycle {cycle}"); } JsonEvents::RegWrite { idx, data, cycle } => { - self.runner.cycle = *cycle; self.runner.peek_reg_write(&RegWriteEvent { idx: *idx, data: *data, cycle: *cycle }) } JsonEvents::RegWriteWait { idx, cycle } => { - self.runner.cycle = *cycle; self.runner.peek_reg_write_wait(&RegWriteWaitEvent { idx: *idx, cycle: *cycle }) } JsonEvents::FregWrite { idx, data, cycle } => { - self.runner.cycle = *cycle; self.runner.peek_freg_write(&RegWriteEvent { idx: *idx, data: *data, cycle: *cycle }) } JsonEvents::FregWriteWait { idx, cycle } => { - self.runner.cycle = *cycle; self.runner.peek_freg_write_wait(&RegWriteWaitEvent { idx: *idx, cycle: *cycle }) } JsonEvents::Issue { idx, cycle } => { - self.runner.cycle = *cycle; self.runner.peek_issue(&IssueEvent { idx: *idx, cycle: *cycle }) } JsonEvents::MemoryWrite { mask, data, lsu_idx, address, cycle } => { - self.runner.cycle = *cycle; self.runner.peek_memory_write(&MemoryWriteEvent { mask: mask.clone(), data: data.clone(), @@ -66,11 +57,9 @@ impl Difftest { }) } JsonEvents::LsuEnq { enq, cycle } => { - self.runner.cycle = *cycle; self.runner.update_lsu_idx(&LsuEnqEvent { enq: *enq, cycle: *cycle }) } JsonEvents::VrfWrite { issue_idx, vd, offset, mask, data, lane, cycle } => { - self.runner.cycle = *cycle; self.runner.peek_vrf_write(&VrfWriteEvent { issue_idx: *issue_idx, vd: *vd, @@ -82,11 +71,9 @@ impl Difftest { }) } JsonEvents::CheckRd { data, issue_idx, cycle } => { - self.runner.cycle = *cycle; self.runner.check_rd(&CheckRdEvent { data: *data, issue_idx: *issue_idx, cycle: *cycle }) } JsonEvents::VrfScoreboard { count, issue_idx, cycle } => { - self.runner.cycle = *cycle; self.runner.vrf_scoreboard(&VrfScoreboardEvent { count: *count, issue_idx: *issue_idx, diff --git a/difftest/spike_rs/src/runner.rs b/difftest/spike_rs/src/runner.rs index e96722307..73a198fe1 100644 --- a/difftest/spike_rs/src/runner.rs +++ b/difftest/spike_rs/src/runner.rs @@ -35,12 +35,6 @@ pub struct SpikeRunner { pub vlen: u32, pub dlen: u32, - /// implement the get_t() for mcycle csr update - pub cycle: u64, - - /// for mcycle csr update - pub spike_cycle: u64, - pub do_log_vrf: bool, // register file scoreboard @@ -125,8 +119,6 @@ impl SpikeRunner { float_queue: VecDeque::new(), vlen: args.vlen, dlen: args.dlen, - cycle: 0, - spike_cycle: 0, do_log_vrf, rf_board: vec![None; 32], frf_board: vec![None; 32], @@ -157,7 +149,6 @@ impl SpikeRunner { let proc = self.spike.get_proc(); let state = proc.get_state(); - let mcycle = (self.cycle + self.spike_cycle) as usize; state.set_mcycle(0); let mut event = SpikeEvent::new(spike, self.do_log_vrf); @@ -166,7 +157,7 @@ impl SpikeRunner { let new_pc = if event.is_v() || event.is_exit() { // inst is v / quit debug!( - "SpikeStep: spike run vector insn ({}), mcycle={mcycle}", + "SpikeStep: spike run vector insn ({})", event.describe_insn(), ); event.pre_log_arch_changes(spike, self.vlen).unwrap(); @@ -176,7 +167,7 @@ impl SpikeRunner { } else { // inst is scalar debug!( - "SpikeStep: spike run scalar insn ({}), mcycle={mcycle}", + "SpikeStep: spike run scalar insn ({})", event.describe_insn(), ); let new_pc_ = proc.func(); @@ -187,8 +178,6 @@ impl SpikeRunner { state.handle_pc(new_pc).unwrap(); - self.spike_cycle += 1; - event } From 1f41e7560d28773d460a83fb30009922bc4368ce Mon Sep 17 00:00:00 2001 From: Clo91eaf Date: Mon, 4 Nov 2024 17:26:19 +0800 Subject: [PATCH 2/4] [t1emu] refactor t1 testbench --- difftest/offline_t1emu/src/json_events.rs | 10 +++---- .../offline_t1rocketemu/src/json_events.rs | 2 +- t1emu/src/TestBench.scala | 27 +++++++++---------- 3 files changed, 19 insertions(+), 20 deletions(-) diff --git a/difftest/offline_t1emu/src/json_events.rs b/difftest/offline_t1emu/src/json_events.rs index 60bf8a388..21afcd273 100644 --- a/difftest/offline_t1emu/src/json_events.rs +++ b/difftest/offline_t1emu/src/json_events.rs @@ -87,7 +87,7 @@ pub(crate) enum JsonEvents { issue_idx: u8, cycle: u64, }, - VrfScoreboardReport { + VrfScoreboard { count: u32, issue_idx: u8, cycle: u64, @@ -122,7 +122,7 @@ pub struct MemoryWriteEvent { pub cycle: u64, } -pub struct VrfScoreboardReportEvent { +pub struct VrfScoreboardEvent { pub count: u32, pub issue_idx: u8, pub cycle: u64, @@ -141,7 +141,7 @@ pub(crate) trait JsonEventRunner { fn peek_vrf_write(&mut self, vrf_write: &VrfWriteEvent) -> anyhow::Result<()>; - fn vrf_scoreboard_report(&mut self, report: &VrfScoreboardReportEvent) -> anyhow::Result<()>; + fn vrf_scoreboard(&mut self, report: &VrfScoreboardEvent) -> anyhow::Result<()>; fn peek_memory_write(&mut self, memory_write: &MemoryWriteEvent) -> anyhow::Result<()>; @@ -314,7 +314,7 @@ impl JsonEventRunner for SpikeRunner { panic!("[{cycle}] cannot find se with instruction lsu_idx={lsu_idx}") } - fn vrf_scoreboard_report(&mut self, report: &VrfScoreboardReportEvent) -> anyhow::Result<()> { + fn vrf_scoreboard(&mut self, report: &VrfScoreboardEvent) -> anyhow::Result<()> { let count = report.count; let issue_idx = report.issue_idx; let cycle = report.cycle; @@ -336,7 +336,7 @@ impl JsonEventRunner for SpikeRunner { se.vrf_access_record.unretired_writes = Some(count - se.vrf_access_record.retired_writes); info!( - "[{cycle}] VrfScoreboardReport: count={count}, issue_idx={issue_idx}, retired={} ({})", + "[{cycle}] VrfScoreboard: count={count}, issue_idx={issue_idx}, retired={} ({})", se.vrf_access_record.retired_writes, se.describe_insn() ); diff --git a/difftest/offline_t1rocketemu/src/json_events.rs b/difftest/offline_t1rocketemu/src/json_events.rs index ed2589805..ca1bbfa4c 100644 --- a/difftest/offline_t1rocketemu/src/json_events.rs +++ b/difftest/offline_t1rocketemu/src/json_events.rs @@ -510,7 +510,7 @@ impl JsonEventRunner for SpikeRunner { se.vrf_access_record.unretired_writes = Some(count - se.vrf_access_record.retired_writes); info!( - "[{cycle}] VrfScoreboardReport: count={count}, issue_idx={issue_idx}, retired={} ({})", + "[{cycle}] VrfScoreboard: count={count}, issue_idx={issue_idx}, retired={} ({})", se.vrf_access_record.retired_writes, se.describe_insn() ); diff --git a/t1emu/src/TestBench.scala b/t1emu/src/TestBench.scala index d43b91c5a..883588c62 100644 --- a/t1emu/src/TestBench.scala +++ b/t1emu/src/TestBench.scala @@ -153,25 +153,24 @@ class TestBench(val parameter: T1Parameter) agent.io.gateWrite := false.B } - // Events for difftest and performance modeling - - // Probes - val laneProbes = t1Probe.laneProbes.zipWithIndex.map { case (lane, i) => - lane.suggestName(s"lane${i}Probe") + // probes + val lsuProbe = t1Probe.lsuProbe.suggestName("lsuProbe") + val laneProbes = t1Probe.laneProbes.zipWithIndex.map { case (p, idx) => + val wire = WireDefault(p).suggestName(s"lane${idx}Probe") + wire + } + val laneVrfProbes = t1Probe.laneProbes.map(_.vrfProbe).zipWithIndex.map { case (p, idx) => + val wire = WireDefault(p).suggestName(s"lane${idx}VrfProbe") + wire } - - val lsuProbe = t1Probe.lsuProbe.suggestName("lsuProbe") - val storeUnitProbe = lsuProbe.storeUnitProbe.suggestName("storeUnitProbe") - val otherUnitProbe = lsuProbe.otherUnitProbe.suggestName("otherUnitProbe") // vrf write - laneProbes.zipWithIndex.foreach { case (lane, i) => - val vrf = lane.vrfProbe.suggestName(s"lane${i}VrfProbe") - when(vrf.valid)( + laneVrfProbes.zipWithIndex.foreach { case (lane, i) => + when(lane.valid)( printf( - cf"""{"event":"VrfWrite","issue_idx":${vrf.requestInstruction},"vd":${vrf.requestVd},"offset":${vrf.requestOffset},"mask":"${vrf.requestMask}%x","data":"${vrf.requestData}%x","lane":$i,"cycle":${simulationTime}}\n""" + cf"""{"event":"VrfWrite","issue_idx":${lane.requestInstruction},"vd":${lane.requestVd},"offset":${lane.requestOffset},"mask":"${lane.requestMask}%x","data":"${lane.requestData}%x","lane":$i,"cycle":${simulationTime}}\n""" ) ) } @@ -227,7 +226,7 @@ class TestBench(val parameter: T1Parameter) scoreboard.bits := scoreboard.bits + PopCount(writeEnq) when(scoreboard.valid && !instructionValid(tag)) { printf( - cf"""{"event":"VrfScoreboardReport","count":${scoreboard.bits},"issue_idx":${tag},"cycle":${simulationTime}}\n""" + cf"""{"event":"VrfScoreboard","count":${scoreboard.bits},"issue_idx":${tag},"cycle":${simulationTime}}\n""" ) scoreboard.valid := false.B } From 2efd2a2622022e8b2ce7e71f3d797f702103638f Mon Sep 17 00:00:00 2001 From: Clo91eaf Date: Fri, 8 Nov 2024 22:33:20 +0800 Subject: [PATCH 3/4] [difftest] use `t1_max_commit_interval_coefficient` instead of `t1_timeout` --- difftest/dpi_t1emu/src/dpi.rs | 4 ---- difftest/dpi_t1emu/src/drive.rs | 12 ++++++++---- difftest/dpi_t1emu/src/lib.rs | 24 ++++++++++++++---------- difftest/dpi_t1rocketemu/src/drive.rs | 8 ++++---- difftest/dpi_t1rocketemu/src/lib.rs | 17 ++++++++++------- script/emu/src/Main.scala | 6 +++--- t1rocketemu/vsrc/ClockGen.sv | 2 +- 7 files changed, 40 insertions(+), 33 deletions(-) diff --git a/difftest/dpi_t1emu/src/dpi.rs b/difftest/dpi_t1emu/src/dpi.rs index 9ee11666a..74004db96 100644 --- a/difftest/dpi_t1emu/src/dpi.rs +++ b/difftest/dpi_t1emu/src/dpi.rs @@ -87,10 +87,6 @@ pub static ISSUE_VALID: u32 = 1; pub static ISSUE_FENCE: u32 = 2; pub static ISSUE_EXIT: u32 = 3; -pub static WATCHDOG_CONTINUE: u8 = 0; -pub static WATCHDOG_TIMEOUT: u8 = 1; -pub static WATCHDOG_QUIT: u8 = 255; - #[repr(C, packed)] pub(crate) struct Retire { pub vxsat: u32, diff --git a/difftest/dpi_t1emu/src/drive.rs b/difftest/dpi_t1emu/src/drive.rs index ce9b71067..4653679a1 100644 --- a/difftest/dpi_t1emu/src/drive.rs +++ b/difftest/dpi_t1emu/src/drive.rs @@ -105,7 +105,7 @@ pub(crate) struct Driver { pub(crate) dlen: u32, - timeout: u64, + max_commit_interval: u64, // driver state last_commit_cycle: u64, @@ -134,7 +134,7 @@ impl Driver { success: false, dlen: args.dlen, - timeout: args.timeout, + max_commit_interval: args.max_commit_interval, last_commit_cycle: 0, issued: 0, @@ -204,6 +204,10 @@ impl Driver { } pub(crate) fn watchdog(&mut self) -> u8 { + const WATCHDOG_CONTINUE: u8 = 0; + const WATCHDOG_TIMEOUT: u8 = 1; + const WATCHDOG_QUIT: u8 = 255; + let tick = get_t(); if self.success { @@ -211,9 +215,9 @@ impl Driver { return WATCHDOG_QUIT; } - if tick - self.last_commit_cycle > self.timeout { + if tick - self.last_commit_cycle > self.max_commit_interval { error!( - "[{tick}] watchdog timeout (last_commit_cycle={})", + "[{tick}] watchdog timeout since last commit (last_commit_cycle={})", self.last_commit_cycle ); return WATCHDOG_TIMEOUT; diff --git a/difftest/dpi_t1emu/src/lib.rs b/difftest/dpi_t1emu/src/lib.rs index b2b0344e6..946ed257c 100644 --- a/difftest/dpi_t1emu/src/lib.rs +++ b/difftest/dpi_t1emu/src/lib.rs @@ -21,25 +21,29 @@ pub(crate) struct OnlineArgs { /// ISA config pub set: String, - // default to TIMEOUT_DEFAULT - pub timeout: u64, + // default to max_commit_interval * vlen / dlen + pub max_commit_interval: u64, } -const TIMEOUT_DEFAULT: u64 = 100000000; +const MAX_COMMIT_INTERVAL_COEFFICIENT: u64 = 10_0000; impl OnlineArgs { pub fn from_plusargs(matcher: &PlusArgMatcher) -> Self { + let vlen = env!("DESIGN_VLEN").parse().unwrap(); + let dlen = env!("DESIGN_DLEN").parse().unwrap(); + let max_commit_interval_coefficient = matcher + .try_match("t1_max_commit_interval_coefficient") + .map(|x| x.parse().unwrap()) + .unwrap_or(MAX_COMMIT_INTERVAL_COEFFICIENT); + let max_commit_interval = max_commit_interval_coefficient * ((vlen / dlen) as u64); + Self { elf_file: matcher.match_("t1_elf_file").into(), log_file: matcher.try_match("t1_log_file").map(|x| x.into()), - - vlen: env!("DESIGN_VLEN").parse().unwrap(), - dlen: env!("DESIGN_DLEN").parse().unwrap(), + vlen, + dlen, set: env!("SPIKE_ISA_STRING").parse().unwrap(), - timeout: matcher - .try_match("t1_timeout") - .map(|x| x.parse().unwrap()) - .unwrap_or(TIMEOUT_DEFAULT), + max_commit_interval, } } } diff --git a/difftest/dpi_t1rocketemu/src/drive.rs b/difftest/dpi_t1rocketemu/src/drive.rs index b20fb46c3..a9b643115 100644 --- a/difftest/dpi_t1rocketemu/src/drive.rs +++ b/difftest/dpi_t1rocketemu/src/drive.rs @@ -32,7 +32,7 @@ pub(crate) struct Driver { pub(crate) dlen: u32, pub(crate) e_entry: u64, - timeout: u64, + max_commit_interval: u64, last_commit_cycle: u64, shadow_bus: ShadowBus, @@ -53,7 +53,7 @@ impl Driver { dlen: args.dlen, e_entry, - timeout: args.timeout, + max_commit_interval: args.max_commit_interval, last_commit_cycle: 0, shadow_bus, @@ -254,9 +254,9 @@ impl Driver { return WATCHDOG_QUIT; } - if tick - self.last_commit_cycle > self.timeout { + if tick - self.last_commit_cycle > self.max_commit_interval { error!( - "[{tick}] watchdog timeout (last_commit_cycle={})", + "[{tick}] watchdog timeout since last commit (last_commit_cycle={})", self.last_commit_cycle ); return WATCHDOG_TIMEOUT; diff --git a/difftest/dpi_t1rocketemu/src/lib.rs b/difftest/dpi_t1rocketemu/src/lib.rs index 8709fbd2c..bc7e0ae84 100644 --- a/difftest/dpi_t1rocketemu/src/lib.rs +++ b/difftest/dpi_t1rocketemu/src/lib.rs @@ -13,21 +13,24 @@ pub(crate) struct OnlineArgs { /// dlen config pub dlen: u32, - // default to TIMEOUT_DEFAULT - pub timeout: u64, + // default to max_commit_interval + pub max_commit_interval: u64, } -const TIMEOUT_DEFAULT: u64 = 100000000; +const MAX_COMMIT_INTERVAL_COEFFICIENT: u64 = 10_0000; impl OnlineArgs { pub fn from_plusargs(matcher: &PlusArgMatcher) -> Self { + let max_commit_interval_coefficient = matcher + .try_match("t1_max_commit_interval_coefficient") + .map(|x| x.parse().unwrap()) + .unwrap_or(MAX_COMMIT_INTERVAL_COEFFICIENT); + let max_commit_interval = max_commit_interval_coefficient; + Self { elf_file: matcher.match_("t1_elf_file").into(), dlen: env!("DESIGN_DLEN").parse().unwrap(), - timeout: matcher - .try_match("t1_timeout") - .map(|x| x.parse().unwrap()) - .unwrap_or(TIMEOUT_DEFAULT), + max_commit_interval, } } } diff --git a/script/emu/src/Main.scala b/script/emu/src/Main.scala index 4fc68e5d8..fc4de7426 100644 --- a/script/emu/src/Main.scala +++ b/script/emu/src/Main.scala @@ -174,9 +174,9 @@ object Main: doc = "Print the final emulator command line and exit" ) dryRun: Flag = Flag(false), @arg( - name = "timeout", + name = "max-commit-interval-coefficient", doc = "Specify maximum cycle count limit" - ) timeout: Option[Int] = None, + ) maxCommitIntervalCoefficient: Option[Int] = None, leftOver: Leftover[String] ): Unit = if leftOver.value.isEmpty then Logger.fatal("No test case name") @@ -219,7 +219,7 @@ object Main: emulator.toString(), s"+t1_elf_file=${caseElfPath}" ) - ++ optionals(timeout.isDefined, Seq(s"+t1_timeout=${timeout.getOrElse("unreachable")}")) + ++ optionals(maxCommitIntervalCoefficient.isDefined, Seq(s"+t1_max_commit_interval_coefficient=${maxCommitIntervalCoefficient.getOrElse("unreachable")}")) ++ optionals(isTrace, Seq(s"+t1_wave_path=${outputPath / "wave.fsdb"}")) ++ optionals(isCover, Seq(s"-cm assert")) ++ optionals(!leftOverArguments.isEmpty, leftOverArguments) diff --git a/t1rocketemu/vsrc/ClockGen.sv b/t1rocketemu/vsrc/ClockGen.sv index 5d80dab4e..be2d13b41 100644 --- a/t1rocketemu/vsrc/ClockGen.sv +++ b/t1rocketemu/vsrc/ClockGen.sv @@ -43,7 +43,7 @@ module ClockGen( // Args: // +t1_elf_file=... : path of elf file - // +t1_timeout=... : (optional) max interval of inst commit, counted in cycle + // +t1_max_commit_interval_coefficient=... : (optional) max interval of inst commit, counted in cycle t1_cosim_init(); `ifdef T1_ENABLE_TRACE From 138a0241221bab54b3ff27f5dfde3ca3b5358366 Mon Sep 17 00:00:00 2001 From: Clo91eaf Date: Sat, 9 Nov 2024 10:46:05 +0800 Subject: [PATCH 4/4] [difftest] add `t1_cosim_refresh` dpi to support refresh the last commit cycle controled by rtl --- difftest/dpi_t1emu/src/dpi.rs | 7 +++++++ difftest/dpi_t1emu/src/drive.rs | 3 ++- difftest/dpi_t1rocketemu/src/dpi.rs | 8 ++++++++ difftest/dpi_t1rocketemu/src/drive.rs | 8 +++++++- 4 files changed, 24 insertions(+), 2 deletions(-) diff --git a/difftest/dpi_t1emu/src/dpi.rs b/difftest/dpi_t1emu/src/dpi.rs index 74004db96..e39922adc 100644 --- a/difftest/dpi_t1emu/src/dpi.rs +++ b/difftest/dpi_t1emu/src/dpi.rs @@ -241,6 +241,13 @@ unsafe extern "C" fn t1_cosim_watchdog() -> u8 { TARGET.with(|driver| driver.watchdog()) } +#[no_mangle] +unsafe extern "C" fn t1_cosim_refresh() { + TARGET.with(|driver| { + driver.last_commit_cycle = crate::get_t(); + }) +} + /// evaluate at instruction queue is not empty /// arg issue will be type cast from a struct to svBitVecVal*(uint32_t*) #[no_mangle] diff --git a/difftest/dpi_t1emu/src/drive.rs b/difftest/dpi_t1emu/src/drive.rs index 4653679a1..e0ef6ee18 100644 --- a/difftest/dpi_t1emu/src/drive.rs +++ b/difftest/dpi_t1emu/src/drive.rs @@ -108,7 +108,7 @@ pub(crate) struct Driver { max_commit_interval: u64, // driver state - last_commit_cycle: u64, + pub(crate) last_commit_cycle: u64, issued: u64, vector_lsu_count: u8, @@ -325,6 +325,7 @@ impl Driver { self.shadow_mem.apply_writes(&se.mem_access_record); self.spike_runner.commit_queue.pop_back(); + // TODO: use t1_cosim_refresh instead self.last_commit_cycle = get_t(); } diff --git a/difftest/dpi_t1rocketemu/src/dpi.rs b/difftest/dpi_t1rocketemu/src/dpi.rs index b5a42ada1..5b392fd30 100644 --- a/difftest/dpi_t1rocketemu/src/dpi.rs +++ b/difftest/dpi_t1rocketemu/src/dpi.rs @@ -313,6 +313,14 @@ unsafe extern "C" fn t1_cosim_watchdog() -> u8 { TARGET.with(|driver| driver.watchdog()) } +/// update last_commit_cycle to current cycle +#[no_mangle] +unsafe extern "C" fn t1_cosim_refresh() { + TARGET.with(|driver| { + driver.last_commit_cycle = crate::get_t(); + }) +} + #[no_mangle] unsafe extern "C" fn get_resetvector(resetvector: *mut c_longlong) { TARGET.with_optional(|driver| { diff --git a/difftest/dpi_t1rocketemu/src/drive.rs b/difftest/dpi_t1rocketemu/src/drive.rs index a9b643115..74ce17e81 100644 --- a/difftest/dpi_t1rocketemu/src/drive.rs +++ b/difftest/dpi_t1rocketemu/src/drive.rs @@ -33,7 +33,7 @@ pub(crate) struct Driver { pub(crate) e_entry: u64, max_commit_interval: u64, - last_commit_cycle: u64, + pub(crate) last_commit_cycle: u64, shadow_bus: ShadowBus, @@ -134,6 +134,7 @@ impl Driver { let size = 1 << arsize; let data = self.shadow_bus.read_mem_axi(addr, size, self.dlen / 8); let data_hex = hex::encode(&data); + // TODO: use t1_cosim_refresh instead self.last_commit_cycle = get_t(); trace!( "[{}] axi_read_high_bandwidth (addr={addr:#x}, size={size}, data={data_hex})", @@ -152,6 +153,7 @@ impl Driver { let size = 1 << awsize; self.shadow_bus.write_mem_axi(addr, size, self.dlen / 8, &strobe, data); let data_hex = hex::encode(data); + // TODO: use t1_cosim_refresh instead self.last_commit_cycle = get_t(); trace!( "[{}] axi_write_high_bandwidth (addr={addr:#x}, size={size}, data={data_hex})", @@ -164,6 +166,7 @@ impl Driver { assert!(size <= 4); let data = self.shadow_bus.read_mem_axi(addr, size, 4); let data_hex = hex::encode(&data); + // TODO: use t1_cosim_refresh instead self.last_commit_cycle = get_t(); trace!( "[{}] axi_read_high_outstanding (addr={addr:#x}, size={size}, data={data_hex})", @@ -182,6 +185,7 @@ impl Driver { let size = 1 << awsize; self.shadow_bus.write_mem_axi(addr, size, 4, strobe, data); let data_hex = hex::encode(data); + // TODO: use t1_cosim_refresh instead self.last_commit_cycle = get_t(); trace!( "[{}] axi_write_high_outstanding (addr={addr:#x}, size={size}, data={data_hex})", @@ -194,6 +198,7 @@ impl Driver { let bus_size = if size == 32 { 32 } else { 4 }; let data = self.shadow_bus.read_mem_axi(addr, size, bus_size); let data_hex = hex::encode(&data); + // TODO: use t1_cosim_refresh instead self.last_commit_cycle = get_t(); trace!( "[{}] axi_read_load_store (addr={addr:#x}, size={size}, data={data_hex})", @@ -213,6 +218,7 @@ impl Driver { let bus_size = if size == 32 { 32 } else { 4 }; self.shadow_bus.write_mem_axi(addr, size, bus_size, strobe, data); let data_hex = hex::encode(data); + // TODO: use t1_cosim_refresh instead self.last_commit_cycle = get_t(); trace!(