diff --git a/.github/cases/blastoise/perf.json b/.github/cases/blastoise/perf.json deleted file mode 100644 index b75990ed7..000000000 --- a/.github/cases/blastoise/perf.json +++ /dev/null @@ -1,9 +0,0 @@ -{ - "mlir.conv": 0, - "mlir.matmul": 0, - "mlir.stripmining": 26732, - "intrinsic.conv2d_less_m2": 2087, - "intrinsic.linear_normalization": 2878, - "intrinsic.matmul": 0, - "intrinsic.softmax": 7437 -} \ No newline at end of file diff --git a/.github/cases/machamp/perf.json b/.github/cases/machamp/perf.json deleted file mode 100644 index 9f0fc6695..000000000 --- a/.github/cases/machamp/perf.json +++ /dev/null @@ -1,5 +0,0 @@ -{ - "mlir.conv": 0, - "mlir.matmul": 0, - "mlir.stripmining": 14447 -} \ No newline at end of file diff --git a/.github/cases/psyduck/perf.json b/.github/cases/psyduck/perf.json deleted file mode 100644 index 3527224f9..000000000 --- a/.github/cases/psyduck/perf.json +++ /dev/null @@ -1,9 +0,0 @@ -{ - "mlir.conv": 0, - "mlir.matmul": 0, - "mlir.stripmining": 0, - "intrinsic.conv2d_less_m2": 0, - "intrinsic.linear_normalization": 0, - "intrinsic.matmul": 0, - "intrinsic.softmax": 0 -} diff --git a/.github/cases/sandslash/perf.json b/.github/cases/sandslash/perf.json deleted file mode 100644 index a63d11557..000000000 --- a/.github/cases/sandslash/perf.json +++ /dev/null @@ -1,5 +0,0 @@ -{ - "mlir.conv": 0, - "mlir.matmul": 0, - "mlir.stripmining": 15253 -} \ No newline at end of file diff --git a/.github/cases/blastoise/default.json b/.github/designs/blastoise/t1emu.json similarity index 99% rename from .github/cases/blastoise/default.json rename to .github/designs/blastoise/t1emu.json index eb0890659..d508dcf3e 100644 --- a/.github/cases/blastoise/default.json +++ b/.github/designs/blastoise/t1emu.json @@ -2,7 +2,6 @@ "pytorch.demo": 76, "pytorch.lenet": 394687, "pytorch.matmul": 14497, - "pytorch.mobilenet": 15139469, "mlir.rvv_vp_intrinsic_add": 435, "mlir.rvv_vp_intrinsic_add_scalable": 583, "mlir.hello": 145, @@ -514,4 +513,5 @@ "rvv_bench.poly1305": 3, "rvv_bench.strlen": 30374, "rvv_bench.utf8_count": 204907 -} \ No newline at end of file +} + diff --git a/.github/cases/machamp/default.json b/.github/designs/machamp/t1emu.json similarity index 99% rename from .github/cases/machamp/default.json rename to .github/designs/machamp/t1emu.json index e76f92645..5213575fe 100644 --- a/.github/cases/machamp/default.json +++ b/.github/designs/machamp/t1emu.json @@ -445,4 +445,4 @@ "rvv_bench.poly1305": 3, "rvv_bench.strlen": 23510, "rvv_bench.utf8_count": 185060 -} \ No newline at end of file +} diff --git a/.github/cases/psyduck/default.json b/.github/designs/psyduck/t1emu.json similarity index 99% rename from .github/cases/psyduck/default.json rename to .github/designs/psyduck/t1emu.json index b208cb21b..377189103 100644 --- a/.github/cases/psyduck/default.json +++ b/.github/designs/psyduck/t1emu.json @@ -526,4 +526,4 @@ "rvv_bench.poly1305": 3, "rvv_bench.strlen": 30374, "rvv_bench.utf8_count": 204907 -} \ No newline at end of file +} diff --git a/.github/cases/sandslash/default.json b/.github/designs/sandslash/t1emu.json similarity index 99% rename from .github/cases/sandslash/default.json rename to .github/designs/sandslash/t1emu.json index 6a555068a..390a0ca68 100644 --- a/.github/cases/sandslash/default.json +++ b/.github/designs/sandslash/t1emu.json @@ -445,4 +445,4 @@ "rvv_bench.poly1305": 3, "rvv_bench.strlen": 19386, "rvv_bench.utf8_count": 154750 -} \ No newline at end of file +} diff --git a/.github/designs/t1rocket/t1rocketemu.json b/.github/designs/t1rocket/t1rocketemu.json new file mode 100644 index 000000000..d508dcf3e --- /dev/null +++ b/.github/designs/t1rocket/t1rocketemu.json @@ -0,0 +1,517 @@ +{ + "pytorch.demo": 76, + "pytorch.lenet": 394687, + "pytorch.matmul": 14497, + "mlir.rvv_vp_intrinsic_add": 435, + "mlir.rvv_vp_intrinsic_add_scalable": 583, + "mlir.hello": 145, + "mlir.stripmining": 26790, + "asm.mmm": 92623, + "asm.smoke": 4922, + "intrinsic.conv2d_less_m2": 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"codegen.vfcvt_rtz_xu_f_v": 6560, + "codegen.vfcvt_rtz_x_f_v": 6579, + "codegen.vfcvt_f_xu_v": 6559, + "codegen.vfcvt_f_x_v": 6565, + "codegen.vfredosum_vs": 160996, + "codegen.vfredusum_vs": 122757, + "codegen.vfredmax_vs": 122757, + "codegen.vfredmin_vs": 122757, + "rvv_bench.ascii_to_utf16": 39155, + "rvv_bench.ascii_to_utf32": 11277, + "rvv_bench.byteswap": 114251, + "rvv_bench.chacha20": 3, + "rvv_bench.mandelbrot": 257255, + "rvv_bench.memcpy": 43841, + "rvv_bench.memset": 14569, + "rvv_bench.mergelines": 89486, + "rvv_bench.poly1305": 3, + "rvv_bench.strlen": 30374, + "rvv_bench.utf8_count": 204907 +} + diff --git a/.github/readme.md b/.github/readme.md new file mode 100644 index 000000000..54cb10074 --- /dev/null +++ b/.github/readme.md @@ -0,0 +1,22 @@ +Current test flow +----------------- + +```mermaid +stateDiagram-v2 + state "GitHub CI Action" as github_ci + state generateTestPlan { + state "read .github/designs/**/*.json" as read_config + state "parse config info" as parse_config + read_config --> parse_config + } + parse_config --> github_ci + state "Build emulator before test" as prebuild_emulator + github_ci --> prebuild_emulator + state "Generate test matrix" as generate_matrix + prebuild_emulator --> generate_matrix + generate_matrix --> github_ci + state "Dispatch tests to machine" as run_test + github_ci --> run_test + state "Collect results" as report + run_test --> report +``` diff --git a/.github/t1rocket-cases/t1rocket/default.json b/.github/t1rocket-cases/t1rocket/default.json deleted file mode 100644 index c2e69d073..000000000 --- a/.github/t1rocket-cases/t1rocket/default.json +++ /dev/null @@ -1,514 +0,0 @@ -{ - "pytorch.demo": 31505, - "mlir.rvv_vp_intrinsic_add": 468, - "mlir.rvv_vp_intrinsic_add_scalable": 696, - "mlir.hello": 140, - "mlir.stripmining": 14002, - "asm.mmm": 94317, - "asm.smoke": 8222, - "intrinsic.conv2d_less_m2": 2499, - "intrinsic.linear_normalization": 3032, - "intrinsic.softmax": 6759, - "codegen.vaadd_vv": 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"codegen.vfcvt_rtz_xu_f_v": 7919, - "codegen.vfcvt_rtz_x_f_v": 7919, - "codegen.vfcvt_f_xu_v": 7919, - "codegen.vfcvt_f_x_v": 7919, - "codegen.vfredosum_vs": 211132, - "codegen.vfredusum_vs": 142775, - "codegen.vfredmax_vs": 142775, - "codegen.vfredmin_vs": 142775, - "rvv_bench.ascii_to_utf16": 702249, - "rvv_bench.ascii_to_utf32": 232728, - "rvv_bench.byteswap": 489291, - "rvv_bench.chacha20": 40015, - "rvv_bench.mandelbrot": 544616, - "rvv_bench.memcpy": 674613, - "rvv_bench.memset": 289499, - "rvv_bench.mergelines": 627690, - "rvv_bench.poly1305": 40015, - "rvv_bench.strlen": 224207, - "rvv_bench.utf8_count": 2304651 -} \ No newline at end of file diff --git a/.github/t1rocket-cases/t1rocket/perf.json b/.github/t1rocket-cases/t1rocket/perf.json deleted file mode 100644 index b75990ed7..000000000 --- a/.github/t1rocket-cases/t1rocket/perf.json +++ /dev/null @@ -1,9 +0,0 @@ -{ - "mlir.conv": 0, - "mlir.matmul": 0, - "mlir.stripmining": 26732, - "intrinsic.conv2d_less_m2": 2087, - "intrinsic.linear_normalization": 2878, - "intrinsic.matmul": 0, - "intrinsic.softmax": 7437 -} \ No newline at end of file diff --git a/.github/workflows/pd.yml b/.github/workflows/pd.yml index 8b8af45db..b152176be 100644 --- a/.github/workflows/pd.yml +++ b/.github/workflows/pd.yml @@ -28,15 +28,18 @@ jobs: ref: ${{ github.event.pull_request.head.sha }} - name: "Test elaborate" run: | - configArray=( $(ls configgen/generated | sed 's/\.json$//') ) + configArray=( $(ls .github/designs) ) + ipArray=( "t1emu" "t1rocketemu" ) for cfg in "${configArray[@]}"; do - echo "Building .#t1.${cfg}.ip.rtl" - if ! nix build ".#t1.${cfg}.ip.rtl" -L; then - failed_rtl_configs+=("${cfg}.ip") - fi - if ! nix run ".#ci-helper" -- runOMTests --config ${cfg}; then - failed_om+=("${cfg}") - fi + for ip in "${ipArray[@]}"; do + echo "Building .#t1.${cfg}.${ip}.rtl" + if ! nix build ".#t1.${cfg}.${ip}.rtl" -L; then + failed_rtl_configs+=("${cfg}.${ip}") + fi + if ! nix run ".#ci-helper" -- runOMTests --config ${cfg}; then + failed_om+=("${cfg}") + fi + done done if [ -n "${failed_rtl_configs[*]}" ]; then echo -e "## Failed RTL\n" >> "$GITHUB_STEP_SUMMARY" diff --git a/.github/workflows/t1rocket.yml b/.github/workflows/t1rocket.yml index a5b24f4f0..bb510c03f 100644 --- a/.github/workflows/t1rocket.yml +++ b/.github/workflows/t1rocket.yml @@ -1,4 +1,4 @@ -name: VCS Test (T1 w/ Rocket) +name: T1RocketEmu VCS Test on: pull_request: types: @@ -9,6 +9,7 @@ on: - labeled env: USER: runner + EMU_TOP: t1rocketemu # Cancel the current workflow when new commit pushed concurrency: @@ -27,10 +28,10 @@ jobs: with: ref: ${{ github.event.pull_request.head.sha }} - id: "get-all-configs" - run: echo "out=$(nix run .#ci-helper -- generateTestPlan --testType t1rocket)" > $GITHUB_OUTPUT + run: echo "out=$(nix run .#ci-helper -- generateTestPlan --top ${{ env.EMU_TOP }})" > $GITHUB_OUTPUT build-emulators: - name: "Build VCS Emulators w/ Rocket" + name: "Build VCS Emulators" needs: [gen-test-plan] runs-on: [self-hosted, linux, nixos, BIGRAM] strategy: @@ -42,10 +43,10 @@ jobs: ref: ${{ github.event.pull_request.head.sha }} - name: "Build vcs emulator" run: | - nix build '.#t1.${{ matrix.config }}.ip.vcs-emu' --impure --no-link --cores 64 + nix build '.#t1.${{ matrix.config }}.${{ env.EMU_TOP }}.vcs-emu' --impure --no-link - name: "Build all testcases" run: | - nix build ".#t1.${{ matrix.config }}.ip.cases._all" --max-jobs auto --no-link --cores 64 + nix build ".#t1.${{ matrix.config }}.${{ env.EMU_TOP }}.cases._all" --max-jobs auto --no-link --cores 64 gen-matrix: name: "Prepare for running testcases" @@ -66,10 +67,10 @@ jobs: name: "Generate test matrix" run: | echo -n matrix= >> "$GITHUB_OUTPUT" - nix run ".#ci-helper" -- generateCiMatrix --caseDir t1rocket-cases --runnersAmount "$RUNNERS" >> "$GITHUB_OUTPUT" + nix run ".#ci-helper" -- generateCiMatrix --top ${{ env.EMU_TOP }} --runnersAmount "$RUNNERS" >> "$GITHUB_OUTPUT" run-testcases: - name: "Run VCS w/ Rocket" + name: "Run VCS" needs: [gen-matrix] strategy: fail-fast: false @@ -81,10 +82,10 @@ jobs: ref: ${{ github.event.pull_request.head.sha }} - name: "Run testcases" run: | - nix run ".#ci-helper" -- runTests --jobs "${{ matrix.jobs }}" --testType "vcs" + nix run ".#ci-helper" -- runTests --jobs "${{ matrix.jobs }}" --emuLib "vcs" --top ${{ env.EMU_TOP }} report: - name: "Report VCS (w/ Rocket) CI result" + name: "Report VCS CI result" # Don't run report when: # - user cancel ( we don't need report at this case ) # - PR from outside repository ( we don't have permission to push commit into fork repository ) @@ -101,23 +102,26 @@ jobs: - name: "Print step summary" run: | nix run ".#ci-helper" -- postCI \ - --case-dir t1rocket-cases \ - --failed-tests-file-path ./failed-tests.md \ + --urg-report-file-path ./urg-report.md \ --cycle-update-file-path ./cycle-update.md \ - --emu-type vcs - cat ./failed-tests.md >> $GITHUB_STEP_SUMMARY + --failed-tests-file-path ./failed-tests.md \ + --emu-lib "vcs" \ + --top ${{ env.EMU_TOP }} + cat ./urg-report.md >> $GITHUB_STEP_SUMMARY echo >> $GITHUB_STEP_SUMMARY cat ./cycle-update.md >> $GITHUB_STEP_SUMMARY + echo >> $GITHUB_STEP_SUMMARY + cat ./failed-tests.md >> $GITHUB_STEP_SUMMARY - name: "Commit cycle updates" run: | git config user.name github-actions git config user.email github-actions@github.com - changed_cases=$(git diff --name-only '.github/**/default.json') + changed_cases=$(git diff --name-only '.github/designs/**/*.json') if [ -n "$changed_cases" ]; then echo "changed cases: $changed_cases" git add '.github/**/default.json' - git commit -m "[ci] update t1rocket test case cycle data" + git commit -m "[ci] update t1 test case cycle data" git push origin ${{ github.head_ref }} else echo "No cycle change detect" diff --git a/.github/workflows/trace.yml b/.github/workflows/trace.yml index a7efb8e16..27d9fd627 100644 --- a/.github/workflows/trace.yml +++ b/.github/workflows/trace.yml @@ -16,9 +16,9 @@ concurrency: cancel-in-progress: true jobs: - gen-test-plan: + gen-test-plan-for-t1emu: if: '! github.event.pull_request.draft' - name: "Generate test plan" + name: "[T1EMU] Generate test plan" runs-on: [self-hosted, linux, nixos] outputs: testplan: ${{ steps.get-all-configs.outputs.out }} @@ -27,19 +27,47 @@ jobs: with: ref: ${{ github.event.pull_request.head.sha }} - id: "get-all-configs" - run: echo "out=$(nix run .#ci-helper generateTestPlan)" > $GITHUB_OUTPUT + run: echo "out=$(nix run .#ci-helper -- generateTestPlan --top t1emu)" > $GITHUB_OUTPUT - build-vcs-emulators: - name: "Build VCS trace emulators" - needs: [gen-test-plan] + build-t1emu-vcs-emulators: + name: "[T1EMU] Build VCS trace emulators" + needs: [gen-test-plan-for-t1emu] runs-on: [self-hosted, linux, nixos, BIGRAM] strategy: fail-fast: false - matrix: ${{ fromJSON(needs.gen-test-plan.outputs.testplan) }} + matrix: ${{ fromJSON(needs.gen-test-plan-for-t1emu.outputs.testplan) }} steps: - uses: actions/checkout@v4 with: ref: ${{ github.event.pull_request.head.sha }} - - name: "Build vcs emulator" + - name: "Build T1Emu vcs emulator" run: | - nix build '.#t1.${{ matrix.config }}.ip.vcs-emu-trace' --impure --no-link --cores 64 \ No newline at end of file + nix build '.#t1.${{ matrix.config }}.t1emu.vcs-emu-trace' --impure --no-link --cores 64 + + gen-test-plan-for-t1rocketemu: + if: '! github.event.pull_request.draft' + name: "[T1ROCKETEMU] Generate test plan" + runs-on: [self-hosted, linux, nixos] + outputs: + testplan: ${{ steps.get-all-configs.outputs.out }} + steps: + - uses: actions/checkout@v4 + with: + ref: ${{ github.event.pull_request.head.sha }} + - id: "get-all-configs" + run: echo "out=$(nix run .#ci-helper -- generateTestPlan --top t1rocketemu)" > $GITHUB_OUTPUT + + build-t1rocketemu-vcs-emulators: + name: "[T1EMU] Build VCS trace emulators" + needs: [gen-test-plan-for-t1rocketemu] + runs-on: [self-hosted, linux, nixos, BIGRAM] + strategy: + fail-fast: false + matrix: ${{ fromJSON(needs.gen-test-plan-for-t1rocketemu.outputs.testplan) }} + steps: + - uses: actions/checkout@v4 + with: + ref: ${{ github.event.pull_request.head.sha }} + - name: "Build T1RocketEmu vcs emulator" + run: | + nix build '.#t1.${{ matrix.config }}.t1rocketemu.vcs-emu-trace' --impure --no-link --cores 64 diff --git a/.github/workflows/vcs.yml b/.github/workflows/vcs.yml index 1b36c6c2f..5a8da0c62 100644 --- a/.github/workflows/vcs.yml +++ b/.github/workflows/vcs.yml @@ -1,4 +1,4 @@ -name: VCS Test +name: T1Emu VCS Test on: pull_request: types: @@ -9,6 +9,7 @@ on: - labeled env: USER: runner + EMU_TOP: t1emu # Cancel the current workflow when new commit pushed concurrency: @@ -27,7 +28,7 @@ jobs: with: ref: ${{ github.event.pull_request.head.sha }} - id: "get-all-configs" - run: echo "out=$(nix run .#ci-helper generateTestPlan)" > $GITHUB_OUTPUT + run: echo "out=$(nix run .#ci-helper -- generateTestPlan --top ${{ env.EMU_TOP }})" > $GITHUB_OUTPUT build-emulators: name: "Build VCS Emulators" @@ -42,10 +43,10 @@ jobs: ref: ${{ github.event.pull_request.head.sha }} - name: "Build vcs emulator" run: | - nix build '.#t1.${{ matrix.config }}.ip.vcs-emu' --impure --no-link --cores 64 + nix build '.#t1.${{ matrix.config }}.${{ env.EMU_TOP }}.vcs-emu' --impure --no-link - name: "Build all testcases" run: | - nix build ".#t1.${{ matrix.config }}.ip.cases._all" --max-jobs auto --no-link --cores 64 + nix build ".#t1.${{ matrix.config }}.${{ env.EMU_TOP }}.cases._all" --max-jobs auto --no-link --cores 64 gen-matrix: name: "Prepare for running testcases" @@ -66,7 +67,7 @@ jobs: name: "Generate test matrix" run: | echo -n matrix= >> "$GITHUB_OUTPUT" - nix run ".#ci-helper" -- generateCiMatrix --runnersAmount "$RUNNERS" >> "$GITHUB_OUTPUT" + nix run ".#ci-helper" -- generateCiMatrix --top ${{ env.EMU_TOP }} --runnersAmount "$RUNNERS" >> "$GITHUB_OUTPUT" run-testcases: name: "Run VCS" @@ -81,7 +82,7 @@ jobs: ref: ${{ github.event.pull_request.head.sha }} - name: "Run testcases" run: | - nix run ".#ci-helper" -- runTests --jobs "${{ matrix.jobs }}" --testType "vcs" + nix run ".#ci-helper" -- runTests --jobs "${{ matrix.jobs }}" --emuLib "vcs" --top ${{ env.EMU_TOP }} report: name: "Report VCS CI result" @@ -104,7 +105,8 @@ jobs: --urg-report-file-path ./urg-report.md \ --cycle-update-file-path ./cycle-update.md \ --failed-tests-file-path ./failed-tests.md \ - --emu-type vcs + --emu-lib "vcs" \ + --top ${{ env.EMU_TOP }} cat ./urg-report.md >> $GITHUB_STEP_SUMMARY echo >> $GITHUB_STEP_SUMMARY cat ./cycle-update.md >> $GITHUB_STEP_SUMMARY @@ -114,7 +116,7 @@ jobs: run: | git config user.name github-actions git config user.email github-actions@github.com - changed_cases=$(git diff --name-only '.github/**/default.json') + changed_cases=$(git diff --name-only '.github/designs/**/*.json') if [ -n "$changed_cases" ]; then echo "changed cases: $changed_cases" diff --git a/.github/workflows/verilator.yml b/.github/workflows/verilator.yml index cfe7eb774..19089533c 100644 --- a/.github/workflows/verilator.yml +++ b/.github/workflows/verilator.yml @@ -1,9 +1,12 @@ -name: Verilator Daily Regression +name: T1Emu Verilator Daily Regression on: schedule: # Run this job everyday at 6:30 AM UTC+8 - cron: '30 22 * * *' +env: + EMU_TOP: t1emu + jobs: gen-test-plan: name: "Generate test plan" @@ -15,7 +18,7 @@ jobs: with: ref: ${{ github.event.pull_request.head.sha }} - id: "get-all-configs" - run: echo "out=$(nix run .#ci-helper generateTestPlan)" > $GITHUB_OUTPUT + run: echo "out=$(nix run .#ci-helper -- generateTestPlan --top ${{ env.EMU_TOP }})" > $GITHUB_OUTPUT build-verilator-emulators: name: "Build Verilator Emulators" @@ -30,11 +33,11 @@ jobs: ref: ${{ github.event.pull_request.head.sha }} - name: "Build verilator emulator" run: | - nix build '.#t1.${{ matrix.config }}.ip.verilator-emu' -L --no-link --cores 64 + nix build '.#t1.${{ matrix.config }}.${{ env.EMU_TOP }}.verilator-emu' -L --no-link --cores 64 - name: "Build all testcases" run: | # Build testcases with vlen 1024 and vlen 4096 - nix build ".#t1.${{ matrix.config }}.ip.cases._all" --max-jobs auto -L --no-link --cores 64 + nix build ".#t1.${{ matrix.config }}.${{ env.EMU_TOP }}.cases._all" --max-jobs auto -L --no-link --cores 64 # In the future, we may choose Verdi for trace, and left verilator trace only for performance evaluation build-verilator-trace-emulators: @@ -49,7 +52,7 @@ jobs: with: ref: ${{ github.event.pull_request.head.sha }} - name: "Build verilator emulator with trace" - run: nix build '.#t1.${{ matrix.config }}.ip.verilator-emu-trace' -L --no-link --cores 64 + run: nix build '.#t1.${{ matrix.config }}.${{ env.EMU_TOP }}.verilator-emu-trace' -L --no-link --cores 64 gen-matrix: name: "Prepare for running testcases" @@ -70,7 +73,7 @@ jobs: name: "Generate test matrix" run: | echo -n matrix= >> "$GITHUB_OUTPUT" - nix run ".#ci-helper" -- generateCiMatrix --runnersAmount "$RUNNERS" >> "$GITHUB_OUTPUT" + nix run ".#ci-helper" -- generateCiMatrix --top ${{ env.EMU_TOP }} --runnersAmount "$RUNNERS" >> "$GITHUB_OUTPUT" run-testcases: name: "Run testcases" @@ -85,7 +88,7 @@ jobs: ref: ${{ github.event.pull_request.head.sha }} - name: "Run testcases" run: | - nix run ".#ci-helper" -- runTests --jobs "${{ matrix.jobs }}" + nix run ".#ci-helper" -- runTests --jobs "${{ matrix.jobs }}" --emuLib "verilator" --top ${{ env.EMU_TOP }} report: name: "Report CI result" @@ -107,20 +110,8 @@ jobs: nix run ".#ci-helper" -- postCI \ --failed-tests-file-path ./failed-tests.md \ --cycle-update-file-path ./cycle-update.md + --emu-lib "verilator" \ + --top ${{ env.EMU_TOP }} cat ./failed-tests.md >> $GITHUB_STEP_SUMMARY echo >> $GITHUB_STEP_SUMMARY cat ./cycle-update.md >> $GITHUB_STEP_SUMMARY - - name: "Commit cycle updates" - run: | - git config user.name github-actions - git config user.email github-actions@github.com - changed_cases=$(git diff --name-only '.github/**/default.json') - - if [ -n "$changed_cases" ]; then - echo "changed cases: $changed_cases" - git add '.github/**/default.json' - git commit -m "[ci] update test case cycle data" - git push origin ${{ github.head_ref }} - else - echo "No cycle change detect" - fi diff --git a/configgen/generated/blastoise.json b/configgen/generated/blastoise.json deleted file mode 100644 index 290ef86c1..000000000 --- a/configgen/generated/blastoise.json +++ /dev/null @@ -1,174 +0,0 @@ -{ - "parameter": { - "vLen": 512, - "dLen": 256, - "extensions": [ - "Zve32f" - ], - "t1customInstructions": [], - "vrfBankSize": 1, - "vrfRamType": "org.chipsalliance.t1.rtl.vrf.RamType.p0rwp1rw", - "vfuInstantiateParameter": { - "slotCount": 4, - "logicModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.MaskedLogic" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "aluModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneAdder" - }, - [ - 0 - ] - ], - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneAdder" - }, - [ - 1 - ] - ], - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneAdder" - }, - [ - 2 - ] - ], - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneAdder" - }, - [ - 3 - ] - ] - ], - "shifterModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneShifter" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "mulModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 2 - }, - "generator": "org.chipsalliance.t1.rtl.LaneMul" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "divModuleParameters": [], - "divfpModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneDivFP" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "otherModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "vlMaxBits": 10, - "groupNumberBits": 4, - "laneNumberBits": 3, - "dataPathByteWidth": 4, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.OtherUnit" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "floatModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 3 - }, - "generator": "org.chipsalliance.t1.rtl.LaneFloat" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "zvbbModuleParameters": [] - } - }, - "generator": "org.chipsalliance.t1.rtl.T1" -} \ No newline at end of file diff --git a/configgen/generated/machamp.json b/configgen/generated/machamp.json deleted file mode 100644 index ceeaf5e59..000000000 --- a/configgen/generated/machamp.json +++ /dev/null @@ -1,158 +0,0 @@ -{ - "parameter": { - "vLen": 1024, - "dLen": 512, - "extensions": [ - "Zve32x" - ], - "t1customInstructions": [], - "vrfBankSize": 2, - "vrfRamType": "org.chipsalliance.t1.rtl.vrf.RamType.p0rp1w", - "vfuInstantiateParameter": { - "slotCount": 4, - "logicModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.MaskedLogic" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "aluModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneAdder" - }, - [ - 0 - ] - ], - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneAdder" - }, - [ - 1 - ] - ], - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneAdder" - }, - [ - 2 - ] - ], - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneAdder" - }, - [ - 3 - ] - ] - ], - "shifterModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneShifter" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "mulModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 2 - }, - "generator": "org.chipsalliance.t1.rtl.LaneMul" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "divModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneDiv" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "divfpModuleParameters": [], - "otherModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "vlMaxBits": 11, - "groupNumberBits": 4, - "laneNumberBits": 4, - "dataPathByteWidth": 4, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.OtherUnit" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "floatModuleParameters": [], - "zvbbModuleParameters": [] - } - }, - "generator": "org.chipsalliance.t1.rtl.T1" -} \ No newline at end of file diff --git a/configgen/generated/psyduck.json b/configgen/generated/psyduck.json deleted file mode 100644 index 04a2f3572..000000000 --- a/configgen/generated/psyduck.json +++ /dev/null @@ -1,191 +0,0 @@ -{ - "parameter": { - "vLen": 512, - "dLen": 256, - "extensions": [ - "Zve32f", - "Zvbb" - ], - "t1customInstructions": [], - "vrfBankSize": 1, - "vrfRamType": "org.chipsalliance.t1.rtl.vrf.RamType.p0rwp1rw", - "vfuInstantiateParameter": { - "slotCount": 4, - "logicModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.MaskedLogic" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "aluModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneAdder" - }, - [ - 0 - ] - ], - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneAdder" - }, - [ - 1 - ] - ], - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneAdder" - }, - [ - 2 - ] - ], - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneAdder" - }, - [ - 3 - ] - ] - ], - "shifterModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneShifter" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "mulModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 2 - }, - "generator": "org.chipsalliance.t1.rtl.LaneMul" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "divModuleParameters": [], - "divfpModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneDivFP" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "otherModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "vlMaxBits": 10, - "groupNumberBits": 4, - "laneNumberBits": 3, - "dataPathByteWidth": 4, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.OtherUnit" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "floatModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 3 - }, - "generator": "org.chipsalliance.t1.rtl.LaneFloat" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "zvbbModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 3 - }, - "generator": "org.chipsalliance.t1.rtl.LaneZvbb" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ] - } - }, - "generator": "org.chipsalliance.t1.rtl.T1" -} \ No newline at end of file diff --git a/configgen/generated/sandslash.json b/configgen/generated/sandslash.json deleted file mode 100644 index 688085fe1..000000000 --- a/configgen/generated/sandslash.json +++ /dev/null @@ -1,158 +0,0 @@ -{ - "parameter": { - "vLen": 4096, - "dLen": 1024, - "extensions": [ - "Zve32x" - ], - "t1customInstructions": [], - "vrfBankSize": 4, - "vrfRamType": "org.chipsalliance.t1.rtl.vrf.RamType.p0rw", - "vfuInstantiateParameter": { - "slotCount": 4, - "logicModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.MaskedLogic" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "aluModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneAdder" - }, - [ - 0 - ] - ], - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneAdder" - }, - [ - 1 - ] - ], - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneAdder" - }, - [ - 2 - ] - ], - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneAdder" - }, - [ - 3 - ] - ] - ], - "shifterModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneShifter" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "mulModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 2 - }, - "generator": "org.chipsalliance.t1.rtl.LaneMul" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "divModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.LaneDiv" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "divfpModuleParameters": [], - "otherModuleParameters": [ - [ - { - "parameter": { - "datapathWidth": 32, - "vlMaxBits": 13, - "groupNumberBits": 5, - "laneNumberBits": 5, - "dataPathByteWidth": 4, - "latency": 1 - }, - "generator": "org.chipsalliance.t1.rtl.OtherUnit" - }, - [ - 0, - 1, - 2, - 3 - ] - ] - ], - "floatModuleParameters": [], - "zvbbModuleParameters": [] - } - }, - "generator": "org.chipsalliance.t1.rtl.T1" -} \ No newline at end of file diff --git a/configgen/src/Main.scala b/configgen/src/Main.scala deleted file mode 100644 index 1c4a468ba..000000000 --- a/configgen/src/Main.scala +++ /dev/null @@ -1,270 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileCopyrightText: 2022 Jiuyang Liu - -package org.chipsalliance.t1.configgen - -import chisel3.experimental.SerializableModuleGenerator -import chisel3.util.{log2Ceil, BitPat} -import chisel3.util.experimental.BitSet -import mainargs._ -import org.chipsalliance.t1.rtl._ -import org.chipsalliance.t1.rtl.decoder.T1CustomInstruction -import org.chipsalliance.t1.rtl.vrf.RamType - -import java.util.LinkedHashMap - -object Main { - implicit object PathRead extends TokensReader.Simple[os.Path] { - def shortName = "path" - def read(strs: Seq[String]): Either[String, os.Path] = Right(os.Path(strs.head, os.pwd)) - } - implicit class EmitVParameter(p: T1Parameter) { - def emit(targetFile: os.Path) = os.write( - targetFile, - upickle.default.write(SerializableModuleGenerator(classOf[T1], p), indent = 2) - ) - } - - @main def listConfigs( - @arg(name = "project-dir", short = 't') projectDir: os.Path = os.pwd - ): Unit = { - val declaredMethods = - Main.getClass().getDeclaredMethods().filter(m => m.getParameterTypes().mkString(", ") == "class os.Path, boolean") - - import scala.io.AnsiColor._ - - declaredMethods.foreach(configgen => { - val param = configgen.invoke(Main, os.root / "dev" / "null", false) - println(s"""${BOLD}${MAGENTA_B} ${configgen.getName()} ${RESET} - | ${param.toString()}""".stripMargin) - }) - } - - @main def updateConfigs( - @arg(name = "project-dir", short = 't') projectDir: os.Path = os.pwd - ): Unit = { - val declaredMethods = - Main.getClass().getDeclaredMethods().filter(m => m.getParameterTypes().mkString(", ") == "class os.Path, boolean") - - import scala.io.AnsiColor._ - - val generatedDir = projectDir / "configgen" / "generated" - os.list(generatedDir).foreach(f => os.remove(f)) - - declaredMethods.foreach(configgen => { - val configName = configgen.getName() - configgen.invoke(Main, generatedDir / s"$configName.json", true) - }) - } - - // DLEN256 VLEN256; FP; VRF p0rw,p1rw bank1; LSU bank8 beatbyte 8 - @main def blastoise( - @arg(name = "target-file", short = 't') targetFile: os.Path, - @arg(name = "emit", short = 'e', doc = "emit config") doEmit: Boolean = true - ): T1Parameter = { - val vLen = 512 - val dLen = 256 - val param = T1Parameter( - vLen, - dLen, - extensions = Seq("Zve32f"), - t1customInstructions = Nil, - vrfBankSize = 1, - vrfRamType = RamType.p0rwp1rw, - vfuInstantiateParameter = VFUInstantiateParameter( - slotCount = 4, - logicModuleParameters = Seq( - (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(0, 1, 2, 3)) - ), - aluModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(0)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(1)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(2)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(3)) - ), - shifterModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(0, 1, 2, 3)) - ), - mulModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneMul], LaneMulParam(32, 2)), Seq(0, 1, 2, 3)) - ), - divModuleParameters = Seq(), - divfpModuleParameters = - Seq((SerializableModuleGenerator(classOf[LaneDivFP], LaneDivFPParam(32, 1)), Seq(0, 1, 2, 3))), - otherModuleParameters = Seq( - ( - SerializableModuleGenerator( - classOf[OtherUnit], - OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) - ), - Seq(0, 1, 2, 3) - ) - ), - floatModuleParameters = - Seq((SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(0, 1, 2, 3))), - zvbbModuleParameters = Seq() - ) - ) - if (doEmit) param.emit(targetFile) - param - } - - // DLEN256 VLEN256; FP; VRF p0rw,p1rw bank1; LSU bank8 beatbyte 8; Zvbb - @main def psyduck( - @arg(name = "target-file", short = 't') targetFile: os.Path, - @arg(name = "emit", short = 'e', doc = "emit config") doEmit: Boolean = true - ): T1Parameter = { - val vLen = 512 - val dLen = 256 - val param = T1Parameter( - vLen, - dLen, - extensions = Seq("Zve32f", "Zvbb"), - t1customInstructions = Nil, - vrfBankSize = 1, - vrfRamType = RamType.p0rwp1rw, - vfuInstantiateParameter = VFUInstantiateParameter( - slotCount = 4, - logicModuleParameters = Seq( - (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(0, 1, 2, 3)) - ), - aluModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(0)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(1)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(2)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(3)) - ), - shifterModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(0, 1, 2, 3)) - ), - mulModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneMul], LaneMulParam(32, 2)), Seq(0, 1, 2, 3)) - ), - divModuleParameters = Seq(), - divfpModuleParameters = - Seq((SerializableModuleGenerator(classOf[LaneDivFP], LaneDivFPParam(32, 1)), Seq(0, 1, 2, 3))), - otherModuleParameters = Seq( - ( - SerializableModuleGenerator( - classOf[OtherUnit], - OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) - ), - Seq(0, 1, 2, 3) - ) - ), - floatModuleParameters = - Seq((SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(0, 1, 2, 3))), - zvbbModuleParameters = - Seq((SerializableModuleGenerator(classOf[LaneZvbb], LaneZvbbParam(32, 3)), Seq(0, 1, 2, 3))) - ) - ) - if (doEmit) param.emit(targetFile) - param - } - - // DLEN512 VLEN1K ; NOFP; VRF p0r,p1w bank2; LSU bank8 beatbyte 16 - @main def machamp( - @arg(name = "target-file", short = 't') targetFile: os.Path, - @arg(name = "emit", short = 'e', doc = "emit config") doEmit: Boolean = true - ): T1Parameter = { - val vLen = 1024 - val dLen = 512 - val param = T1Parameter( - vLen, - dLen, - extensions = Seq("Zve32x"), - t1customInstructions = Nil, - vrfBankSize = 2, - vrfRamType = RamType.p0rp1w, - vfuInstantiateParameter = VFUInstantiateParameter( - slotCount = 4, - logicModuleParameters = Seq( - (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(0, 1, 2, 3)) - ), - aluModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(0)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(1)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(2)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(3)) - ), - shifterModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(0, 1, 2, 3)) - ), - mulModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneMul], LaneMulParam(32, 2)), Seq(0, 1, 2, 3)) - ), - divModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneDiv], LaneDivParam(32, 1)), Seq(0, 1, 2, 3)) - ), - divfpModuleParameters = Seq(), - otherModuleParameters = Seq( - ( - SerializableModuleGenerator( - classOf[OtherUnit], - OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) - ), - Seq(0, 1, 2, 3) - ) - ), - floatModuleParameters = Seq(), - zvbbModuleParameters = Seq() // TODO - ) - ) - if (doEmit) param.emit(targetFile) - param - } - - // DLEN1K VLEN4K ; NOFP; VRF p0rw bank4; LSU bank16 beatbyte 16 - @main def sandslash( - @arg(name = "target-file", short = 't') targetFile: os.Path, - @arg(name = "emit", short = 'e', doc = "emit config") doEmit: Boolean = true - ): T1Parameter = { - val vLen = 4096 - val dLen = 1024 - val param = T1Parameter( - vLen, - dLen, - extensions = Seq("Zve32x"), - t1customInstructions = Nil, - vrfBankSize = 4, - vrfRamType = RamType.p0rw, - vfuInstantiateParameter = VFUInstantiateParameter( - slotCount = 4, - logicModuleParameters = Seq( - (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(0, 1, 2, 3)) - ), - aluModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(0)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(1)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(2)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(3)) - ), - shifterModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(0, 1, 2, 3)) - ), - mulModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneMul], LaneMulParam(32, 2)), Seq(0, 1, 2, 3)) - ), - divModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneDiv], LaneDivParam(32, 1)), Seq(0, 1, 2, 3)) - ), - divfpModuleParameters = Seq(), - otherModuleParameters = Seq( - ( - SerializableModuleGenerator( - classOf[OtherUnit], - OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) - ), - Seq(0, 1, 2, 3) - ) - ), - floatModuleParameters = Seq(), - zvbbModuleParameters = Seq() // TODO - ) - ) - if (doEmit) param.emit(targetFile) - param - } - - def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) -} diff --git a/designs/org.chipsalliance.t1.elaborator.t1.T1.toml b/designs/org.chipsalliance.t1.elaborator.t1.T1.toml new file mode 100644 index 000000000..fb43bf724 --- /dev/null +++ b/designs/org.chipsalliance.t1.elaborator.t1.T1.toml @@ -0,0 +1,8 @@ +[blastoise] +cmdopt = "--dLen 256 --extensions zvl512b --extensions zve32f --vrfBankSize 1 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" +[machamp] +cmdopt = "--dLen 512 --extensions zvl1024b --extensions zve32x --vrfBankSize 2 --vrfRamType p0rp1w --vfuInstantiateParameter small" +[psyduck] +cmdopt = "--dLen 256 --extensions zvl512b --extensions zve32f --extensions zvbb --vrfBankSize 1 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" +[sandslash] +cmdopt = "--dLen 1024 --extensions zvl4096b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter small" diff --git a/designs/org.chipsalliance.t1.elaborator.t1emu.Testbench.toml b/designs/org.chipsalliance.t1.elaborator.t1emu.Testbench.toml new file mode 100644 index 000000000..fb43bf724 --- /dev/null +++ b/designs/org.chipsalliance.t1.elaborator.t1emu.Testbench.toml @@ -0,0 +1,8 @@ +[blastoise] +cmdopt = "--dLen 256 --extensions zvl512b --extensions zve32f --vrfBankSize 1 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" +[machamp] +cmdopt = "--dLen 512 --extensions zvl1024b --extensions zve32x --vrfBankSize 2 --vrfRamType p0rp1w --vfuInstantiateParameter small" +[psyduck] +cmdopt = "--dLen 256 --extensions zvl512b --extensions zve32f --extensions zvbb --vrfBankSize 1 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" +[sandslash] +cmdopt = "--dLen 1024 --extensions zvl4096b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter small" diff --git a/designs/org.chipsalliance.t1.elaborator.t1rocketemu.T1RocketTile.toml b/designs/org.chipsalliance.t1.elaborator.t1rocketemu.T1RocketTile.toml new file mode 100644 index 000000000..9aaa75f46 --- /dev/null +++ b/designs/org.chipsalliance.t1.elaborator.t1rocketemu.T1RocketTile.toml @@ -0,0 +1,2 @@ +[t1rocket] +cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_f --instructionSets rv_v --instructionSets zve32f --instructionSets zvl1024b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 2 --vrfRamType p0rp1w --vfuInstantiateParameter small" diff --git a/designs/org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile.toml b/designs/org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile.toml new file mode 100644 index 000000000..9aaa75f46 --- /dev/null +++ b/designs/org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile.toml @@ -0,0 +1,2 @@ +[t1rocket] +cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_f --instructionSets rv_v --instructionSets zve32f --instructionSets zvl1024b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 2 --vrfRamType p0rp1w --vfuInstantiateParameter small" diff --git a/difftest/Cargo.toml b/difftest/Cargo.toml index 06f733a27..60efa77ef 100644 --- a/difftest/Cargo.toml +++ b/difftest/Cargo.toml @@ -2,10 +2,10 @@ resolver = "2" members = [ "spike_rs", - "offline_t1", - "offline_t1rocket", - "dpi_t1", - "dpi_t1rocket", + "offline_t1emu", + "offline_t1rocketemu", + "dpi_t1emu", + "dpi_t1rocketemu", "dpi_common", ] exclude = [ diff --git a/difftest/default.nix b/difftest/default.nix index 38a672186..dc7f760d0 100644 --- a/difftest/default.nix +++ b/difftest/default.nix @@ -13,9 +13,9 @@ }: assert let - available = [ "dpi_t1" "dpi_t1rocket" "offline_t1" "offline_t1rocket" ]; + available = [ "dpi_t1emu" "dpi_t1rocketemu" "offline_t1emu" "offline_t1rocketemu" ]; in -lib.assertMsg (lib.elem moduleType available) "emuType is not in ${lib.concatStringsSep ", " available}"; +lib.assertMsg (lib.elem moduleType available) "moduleType is not in ${lib.concatStringsSep ", " available}"; # if emuType is empty, then moduleType must be offline-*, or user should give valid emuType assert lib.assertMsg ((emuType == "" && lib.hasPrefix "offline" moduleType) || (lib.elem emuType [ "verilator" "vcs" ])) "emuType is either 'vcs' nor 'verilator'"; @@ -25,11 +25,11 @@ rustPlatform.buildRustPackage { root = ./.; fileset = unions [ ./spike_rs - ./offline_t1 - ./offline_t1rocket + ./offline_t1emu + ./offline_t1rocketemu ./dpi_common - ./dpi_t1 - ./dpi_t1rocket + ./dpi_t1emu + ./dpi_t1rocketemu ./Cargo.lock ./Cargo.toml ./.rustfmt.toml diff --git a/difftest/dpi_t1/Cargo.toml b/difftest/dpi_t1emu/Cargo.toml similarity index 95% rename from difftest/dpi_t1/Cargo.toml rename to difftest/dpi_t1emu/Cargo.toml index b25a52139..ddd501d99 100644 --- a/difftest/dpi_t1/Cargo.toml +++ b/difftest/dpi_t1emu/Cargo.toml @@ -1,5 +1,5 @@ [package] -name = "dpi_t1" +name = "dpi_t1emu" edition = "2021" version.workspace = true diff --git a/difftest/dpi_t1/src/dpi.rs b/difftest/dpi_t1emu/src/dpi.rs similarity index 100% rename from difftest/dpi_t1/src/dpi.rs rename to difftest/dpi_t1emu/src/dpi.rs diff --git a/difftest/dpi_t1/src/drive.rs b/difftest/dpi_t1emu/src/drive.rs similarity index 100% rename from difftest/dpi_t1/src/drive.rs rename to difftest/dpi_t1emu/src/drive.rs diff --git a/difftest/dpi_t1/src/lib.rs b/difftest/dpi_t1emu/src/lib.rs similarity index 100% rename from difftest/dpi_t1/src/lib.rs rename to difftest/dpi_t1emu/src/lib.rs diff --git a/difftest/dpi_t1rocket/Cargo.toml b/difftest/dpi_t1rocketemu/Cargo.toml similarity index 94% rename from difftest/dpi_t1rocket/Cargo.toml rename to difftest/dpi_t1rocketemu/Cargo.toml index 45253a8d3..cfc80aef7 100644 --- a/difftest/dpi_t1rocket/Cargo.toml +++ b/difftest/dpi_t1rocketemu/Cargo.toml @@ -1,5 +1,5 @@ [package] -name = "dpi_t1rocket" +name = "dpi_t1rocketemu" edition = "2021" version.workspace = true diff --git a/difftest/dpi_t1rocket/src/dpi.rs b/difftest/dpi_t1rocketemu/src/dpi.rs similarity index 100% rename from difftest/dpi_t1rocket/src/dpi.rs rename to difftest/dpi_t1rocketemu/src/dpi.rs diff --git a/difftest/dpi_t1rocket/src/drive.rs b/difftest/dpi_t1rocketemu/src/drive.rs similarity index 100% rename from difftest/dpi_t1rocket/src/drive.rs rename to difftest/dpi_t1rocketemu/src/drive.rs diff --git a/difftest/dpi_t1rocket/src/lib.rs b/difftest/dpi_t1rocketemu/src/lib.rs similarity index 100% rename from difftest/dpi_t1rocket/src/lib.rs rename to difftest/dpi_t1rocketemu/src/lib.rs diff --git a/difftest/offline_t1/Cargo.toml b/difftest/offline_t1emu/Cargo.toml similarity index 94% rename from difftest/offline_t1/Cargo.toml rename to difftest/offline_t1emu/Cargo.toml index 8d77199be..8013827fa 100644 --- a/difftest/offline_t1/Cargo.toml +++ b/difftest/offline_t1emu/Cargo.toml @@ -1,5 +1,5 @@ [package] -name = "offline_t1" +name = "offline_t1emu" version = "0.1.0" edition = "2021" diff --git a/difftest/offline_t1/src/difftest.rs b/difftest/offline_t1emu/src/difftest.rs similarity index 100% rename from difftest/offline_t1/src/difftest.rs rename to difftest/offline_t1emu/src/difftest.rs diff --git a/difftest/offline_t1/src/dut.rs b/difftest/offline_t1emu/src/dut.rs similarity index 100% rename from difftest/offline_t1/src/dut.rs rename to difftest/offline_t1emu/src/dut.rs diff --git a/difftest/offline_t1/src/json_events.rs b/difftest/offline_t1emu/src/json_events.rs similarity index 100% rename from difftest/offline_t1/src/json_events.rs rename to difftest/offline_t1emu/src/json_events.rs diff --git a/difftest/offline_t1/src/main.rs b/difftest/offline_t1emu/src/main.rs similarity index 100% rename from difftest/offline_t1/src/main.rs rename to difftest/offline_t1emu/src/main.rs diff --git a/difftest/offline_t1rocket/Cargo.toml b/difftest/offline_t1rocketemu/Cargo.toml similarity index 92% rename from difftest/offline_t1rocket/Cargo.toml rename to difftest/offline_t1rocketemu/Cargo.toml index 19aa68c01..37c749d35 100644 --- a/difftest/offline_t1rocket/Cargo.toml +++ b/difftest/offline_t1rocketemu/Cargo.toml @@ -1,5 +1,5 @@ [package] -name = "offline_t1rocket" +name = "offline_t1rocketemu" version = "0.1.0" edition = "2021" diff --git a/difftest/offline_t1rocket/src/difftest.rs b/difftest/offline_t1rocketemu/src/difftest.rs similarity index 100% rename from difftest/offline_t1rocket/src/difftest.rs rename to difftest/offline_t1rocketemu/src/difftest.rs diff --git a/difftest/offline_t1rocket/src/dut.rs b/difftest/offline_t1rocketemu/src/dut.rs similarity index 100% rename from difftest/offline_t1rocket/src/dut.rs rename to difftest/offline_t1rocketemu/src/dut.rs diff --git a/difftest/offline_t1rocket/src/json_events.rs b/difftest/offline_t1rocketemu/src/json_events.rs similarity index 100% rename from difftest/offline_t1rocket/src/json_events.rs rename to difftest/offline_t1rocketemu/src/json_events.rs diff --git a/difftest/offline_t1rocket/src/main.rs b/difftest/offline_t1rocketemu/src/main.rs similarity index 100% rename from difftest/offline_t1rocket/src/main.rs rename to difftest/offline_t1rocketemu/src/main.rs diff --git a/elaborator/src/Elaborator.scala b/elaborator/src/Elaborator.scala deleted file mode 100644 index ab9bcb434..000000000 --- a/elaborator/src/Elaborator.scala +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileCopyrightText: 2024 Jiuyang Liu -package org.chipsalliance.t1.elaborator - -import chisel3.RawModule -import chisel3.experimental.{SerializableModule, SerializableModuleGenerator, SerializableModuleParameter} -import mainargs.TokensReader - -import scala.reflect.runtime.universe -import scala.reflect.runtime.universe.{runtimeMirror, typeOf} - -// TODO: this will be upstreamed to Chisel -trait Elaborator { - implicit object PathRead extends TokensReader.Simple[os.Path] { - def shortName = "path" - def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) - } - - def configImpl[P <: SerializableModuleParameter: universe.TypeTag]( - parameter: P - )( - implicit rwP: upickle.default.Writer[P] - ) = os.write.over( - os.pwd / s"${getClass.getSimpleName.replace("$", "")}.json", - upickle.default.write(parameter) - ) - - def designImpl[M <: SerializableModule[P]: universe.TypeTag, P <: SerializableModuleParameter: universe.TypeTag]( - parameter: os.Path, - runFirtool: Boolean - )( - implicit - rwP: upickle.default.Reader[P] - ) = { - var fir: firrtl.ir.Circuit = null - val annos = Seq( - new chisel3.stage.phases.Elaborate, - new chisel3.stage.phases.Convert - ).foldLeft( - Seq( - chisel3.stage.ChiselGeneratorAnnotation(() => - SerializableModuleGenerator( - runtimeMirror(getClass.getClassLoader) - .runtimeClass(typeOf[M].typeSymbol.asClass) - .asInstanceOf[Class[M]], - upickle.default.read[P](os.read(parameter)) - ).module().asInstanceOf[RawModule] - ) - ): firrtl.AnnotationSeq - ) { case (annos, stage) => stage.transform(annos) } - .flatMap { - case firrtl.stage.FirrtlCircuitAnnotation(circuit) => - fir = circuit - None - case _: chisel3.stage.DesignAnnotation[_] => None - case _: chisel3.stage.ChiselCircuitAnnotation => None - case a => Some(a) - } - val annoJsonFile = os.pwd / s"${fir.main}.anno.json" - val firFile = os.pwd / s"${fir.main}.fir" - val svFile = os.pwd / s"${fir.main}.sv" - os.write.over(firFile, fir.serialize) - os.write.over( - annoJsonFile, - firrtl.annotations.JsonProtocol.serializeRecover(annos) - ) - if (runFirtool) { - os.proc( - "firtool", - s"--annotation-file=${annoJsonFile}", - s"${firFile}", - s"-o", - s"${svFile}", - "--strip-debug-info", - "--verification-flavor=sva", - "--extract-test-code" - ).call(os.pwd) - } - } -} diff --git a/elaborator/src/Main.scala b/elaborator/src/Main.scala deleted file mode 100644 index 260151a47..000000000 --- a/elaborator/src/Main.scala +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileCopyrightText: 2022 Jiuyang Liu - -package org.chipsalliance.t1.elaborator - -import mainargs._ -import org.chipsalliance.t1.rtl.T1Parameter -import org.chipsalliance.rocketv.RocketTileParameter -import chisel3.panamalib.option._ -import org.chipsalliance.t1.tile.T1RocketTileParameter - -object Main { - implicit object PathRead extends TokensReader.Simple[os.Path] { - def shortName = "path" - def read(strs: Seq[String]): Either[String, os.Path] = Right(os.Path(strs.head, os.pwd)) - } - - @main - case class ElaborateConfig( - @arg(name = "target-dir", short = 't') targetDir: os.Path, - @arg(name = "binder-mlirbc-out") binderMlirbcOut: Option[String] = None) { - def elaborate(gen: () => chisel3.RawModule): Unit = { - var fir: firrtl.ir.Circuit = null - var panamaCIRCTConverter: chisel3.panamaconverter.PanamaCIRCTConverter = null - - val annos = Seq( - new chisel3.stage.phases.Elaborate, - if (binderMlirbcOut.isEmpty) new chisel3.stage.phases.Convert else chisel3.panamaconverter.stage.Convert - ).foldLeft( - Seq( - chisel3.stage.ChiselGeneratorAnnotation(gen), - chisel3.panamaconverter.stage.FirtoolOptionsAnnotation( - FirtoolOptions( - Set( - BuildMode(BuildModeDebug), - PreserveValues(PreserveValuesModeNamed), - DisableUnknownAnnotations(true) - ) - ) - ) - ): firrtl.AnnotationSeq - ) { case (annos, stage) => stage.transform(annos) } - .flatMap { - case firrtl.stage.FirrtlCircuitAnnotation(circuit) => - if (binderMlirbcOut.isEmpty) fir = circuit - None - case chisel3.panamaconverter.stage.PanamaCIRCTConverterAnnotation(converter) => - if (binderMlirbcOut.nonEmpty) panamaCIRCTConverter = converter - None - case _: chisel3.panamaconverter.stage.FirtoolOptionsAnnotation => None - case _: chisel3.stage.DesignAnnotation[_] => None - case _: chisel3.stage.ChiselCircuitAnnotation => None - case a => Some(a) - } - - binderMlirbcOut match { - case Some(outFile) => - os.write(targetDir / s"$outFile.mlirbc", panamaCIRCTConverter.mlirBytecodeStream) - case None => - os.write(targetDir / s"${fir.main}.fir", fir.serialize) - os.write(targetDir / s"${fir.main}.anno.json", firrtl.annotations.JsonProtocol.serialize(annos)) - } - } - } - - implicit def elaborateConfig: ParserForClass[ElaborateConfig] = ParserForClass[ElaborateConfig] - - case class IPConfig( - @arg(name = "ip-config", short = 'c') ipConfig: os.Path) { - def generator = upickle.default - .read[chisel3.experimental.SerializableModuleGenerator[ - org.chipsalliance.t1.rtl.T1, - org.chipsalliance.t1.rtl.T1Parameter - ]](ujson.read(os.read(ipConfig))) - def parameter: T1Parameter = generator.parameter - } - - case class RocketConfig( - @arg(name = "rocket-config", short = 'c') rocketConfig: os.Path) { - def generator = upickle.default - .read[chisel3.experimental.SerializableModuleGenerator[ - org.chipsalliance.rocketv.RocketTile, - org.chipsalliance.rocketv.RocketTileParameter - ]](ujson.read(os.read(rocketConfig))) - def parameter: RocketTileParameter = generator.parameter - } - - case class T1RocketConfig( - @arg(name = "t1rocket-config", short = 'c') rocketConfig: os.Path) { - def generator = upickle.default - .read[chisel3.experimental.SerializableModuleGenerator[ - org.chipsalliance.t1.tile.T1RocketTile, - org.chipsalliance.t1.tile.T1RocketTileParameter - ]](ujson.read(os.read(rocketConfig))) - def parameter: T1RocketTileParameter = generator.parameter - } - - implicit def ipConfig: ParserForClass[IPConfig] = ParserForClass[IPConfig] - implicit def rocketConfig: ParserForClass[RocketConfig] = ParserForClass[RocketConfig] - implicit def t1RocketConfig: ParserForClass[T1RocketConfig] = ParserForClass[T1RocketConfig] - - @main def ip(elaborateConfig: ElaborateConfig, ipConfig: IPConfig): Unit = - elaborateConfig.elaborate(() => ipConfig.generator.module()) - - @main def t1emu(elaborateConfig: ElaborateConfig, ipConfig: IPConfig): Unit = - elaborateConfig.elaborate(() => new org.chipsalliance.t1.t1emu.TestBench(ipConfig.generator)) - - @main def rocketemu(elaborateConfig: ElaborateConfig, rocketConfig: RocketConfig): Unit = - elaborateConfig.elaborate(() => new org.chipsalliance.t1.rocketv.TestBench(rocketConfig.generator)) - - @main def t1rocketemu(elaborateConfig: ElaborateConfig, t1rocketConfig: T1RocketConfig): Unit = - elaborateConfig.elaborate(() => new org.chipsalliance.t1.t1rocketemu.TestBench(t1rocketConfig.generator)) - - def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) -} diff --git a/elaborator/src/rocketv/ALU.scala b/elaborator/src/rocketv/ALU.scala index 05ad596b5..2f81705fa 100644 --- a/elaborator/src/rocketv/ALU.scala +++ b/elaborator/src/rocketv/ALU.scala @@ -2,25 +2,39 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import mainargs._ import org.chipsalliance.rocketv.{ALU, ALUParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object ALU extends Elaborator { +object ALU extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = ALU + type P = ALUParameter + type M = ALUParameterMain + @main case class ALUParameterMain( @arg(name = "xLen") xLen: Int) { - def convert: ALUParameter = ALUParameter(xLen) + def convert: P = ALUParameter(xLen) } - implicit def ALUParameterMainParser: ParserForClass[ALUParameterMain] = ParserForClass[ALUParameterMain] + implicit def ALUParameterMainParser: ParserForClass[M] = ParserForClass[M] @main - def config(@arg(name = "parameter") parameter: ALUParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[ALU, ALUParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/AMOALU.scala b/elaborator/src/rocketv/AMOALU.scala index 148936db5..21265f7c0 100644 --- a/elaborator/src/rocketv/AMOALU.scala +++ b/elaborator/src/rocketv/AMOALU.scala @@ -2,11 +2,21 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import mainargs._ import org.chipsalliance.rocketv.{AMOALU, AMOALUParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object AMOALU extends Elaborator { +object AMOALU extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = AMOALU + type P = AMOALUParameter + type M = AMOALUParameterMain + @main case class AMOALUParameterMain( @arg(name = "operandBits") operandBits: Int) { @@ -16,11 +26,15 @@ object AMOALU extends Elaborator { implicit def AMOALUParameterMainParser: ParserForClass[AMOALUParameterMain] = ParserForClass[AMOALUParameterMain] @main - def config(@arg(name = "parameter") parameter: AMOALUParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[AMOALU, AMOALUParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/BTB.scala b/elaborator/src/rocketv/BTB.scala index 97118a2ad..4056382d0 100644 --- a/elaborator/src/rocketv/BTB.scala +++ b/elaborator/src/rocketv/BTB.scala @@ -2,11 +2,21 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import mainargs._ import org.chipsalliance.rocketv.{BHTParameter, BTB, BTBParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object BTB extends Elaborator { +object BTB extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = BTB + type P = BTBParameter + type M = BTBParameterMain + @main case class BHTParameterMain( @arg(name = "nEntries") nEntries: Int, @@ -67,11 +77,15 @@ object BTB extends Elaborator { implicit def BTBParameterMainParser: ParserForClass[BTBParameterMain] = ParserForClass[BTBParameterMain] @main - def config(@arg(name = "parameter") parameter: BTBParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[BTB, BTBParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/BreakpointUnit.scala b/elaborator/src/rocketv/BreakpointUnit.scala index 445f1a2e7..1165ec657 100644 --- a/elaborator/src/rocketv/BreakpointUnit.scala +++ b/elaborator/src/rocketv/BreakpointUnit.scala @@ -2,11 +2,21 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import mainargs._ import org.chipsalliance.rocketv.{BreakpointUnit, BreakpointUnitParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object BreakpointUnit extends Elaborator { +object BreakpointUnit extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = BreakpointUnit + type P = BreakpointUnitParameter + type M = BreakpointUnitParameterMain + @main case class BreakpointUnitParameterMain( @arg(name = "nBreakpoints") nBreakpoints: Int, @@ -23,11 +33,15 @@ object BreakpointUnit extends Elaborator { ParserForClass[BreakpointUnitParameterMain] @main - def config(@arg(name = "parameter") parameter: BreakpointUnitParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[BreakpointUnit, BreakpointUnitParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/CSR.scala b/elaborator/src/rocketv/CSR.scala index c00fe13e2..ced7b4699 100644 --- a/elaborator/src/rocketv/CSR.scala +++ b/elaborator/src/rocketv/CSR.scala @@ -2,11 +2,21 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import mainargs._ import org.chipsalliance.rocketv.{CSR, CSRParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object CSR extends Elaborator { +object CSR extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = CSR + type P = CSRParameter + type M = CSRParameterMain + @main case class CSRParameterMain( @arg(name = "useAsyncReset") useAsyncReset: Boolean, @@ -60,11 +70,15 @@ object CSR extends Elaborator { implicit def CSRParameterMainParser: ParserForClass[CSRParameterMain] = ParserForClass[CSRParameterMain] @main - def config(@arg(name = "parameter") parameter: CSRParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[CSR, CSRParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/DCache.scala b/elaborator/src/rocketv/DCache.scala index 8a6244b89..8a0ab6d69 100644 --- a/elaborator/src/rocketv/DCache.scala +++ b/elaborator/src/rocketv/DCache.scala @@ -2,13 +2,23 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import chisel3.util.BitPat import chisel3.util.experimental.BitSet import mainargs._ import org.chipsalliance.rocketv.{HellaCache, HellaCacheParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object DCache extends Elaborator { +object DCache extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = HellaCache + type P = HellaCacheParameter + type M = DCacheParameterMain + implicit object BitSetRead extends TokensReader.Simple[BitSet] { def shortName = "bitset" def read(strs: Seq[String]) = { @@ -96,11 +106,15 @@ object DCache extends Elaborator { implicit def DCacheParameterMainParser: ParserForClass[DCacheParameterMain] = ParserForClass[DCacheParameterMain] @main - def config(@arg(name = "parameter") parameter: DCacheParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[HellaCache, HellaCacheParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/Decoder.scala b/elaborator/src/rocketv/Decoder.scala index 059449e2d..8fab91114 100644 --- a/elaborator/src/rocketv/Decoder.scala +++ b/elaborator/src/rocketv/Decoder.scala @@ -2,11 +2,21 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import mainargs._ import org.chipsalliance.rocketv.{Decoder, DecoderParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object Decoder extends Elaborator { +object Decoder extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = Decoder + type P = DecoderParameter + type M = DecoderParameterMain + @main case class DecoderParameterMain( @arg(name = "instructionSets") instructionSets: Set[String], @@ -22,11 +32,15 @@ object Decoder extends Elaborator { implicit def DecoderParameterMainParser: ParserForClass[DecoderParameterMain] = ParserForClass[DecoderParameterMain] @main - def config(@arg(name = "parameter") parameter: DecoderParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[Decoder, DecoderParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/FPToFP.scala b/elaborator/src/rocketv/FPToFP.scala index e29ad7089..267fed13f 100644 --- a/elaborator/src/rocketv/FPToFP.scala +++ b/elaborator/src/rocketv/FPToFP.scala @@ -2,11 +2,21 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import mainargs._ import org.chipsalliance.rocketv.{FPToFP, FPToFPParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object FPToFP extends Elaborator { +object FPToFP extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = FPToFP + type P = FPToFPParameter + type M = FPToFPParameterMain + @main case class FPToFPParameterMain( useAsyncReset: Boolean, @@ -26,11 +36,15 @@ object FPToFP extends Elaborator { implicit def FPToFPParameterMainParser: ParserForClass[FPToFPParameterMain] = ParserForClass[FPToFPParameterMain] @main - def config(@arg(name = "parameter") parameter: FPToFPParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[FPToFP, FPToFPParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/FPToInt.scala b/elaborator/src/rocketv/FPToInt.scala index 9cae363de..63676930b 100644 --- a/elaborator/src/rocketv/FPToInt.scala +++ b/elaborator/src/rocketv/FPToInt.scala @@ -2,11 +2,21 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import mainargs._ import org.chipsalliance.rocketv.{FPToInt, FPToIntParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object FPToInt extends Elaborator { +object FPToInt extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = FPToInt + type P = FPToIntParameter + type M = FPToIntParameterMain + @main case class FPToIntParameterMain( @arg(name = "useAsyncReset") useAsyncReset: Boolean, @@ -24,11 +34,15 @@ object FPToInt extends Elaborator { implicit def FPToIntParameterMainParser: ParserForClass[FPToIntParameterMain] = ParserForClass[FPToIntParameterMain] @main - def config(@arg(name = "parameter") parameter: FPToIntParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[FPToInt, FPToIntParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/FPU.scala b/elaborator/src/rocketv/FPU.scala index 720eb4059..e0ed9e0ec 100644 --- a/elaborator/src/rocketv/FPU.scala +++ b/elaborator/src/rocketv/FPU.scala @@ -2,11 +2,21 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import mainargs._ import org.chipsalliance.rocketv.{FPU, FPUParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object FPU extends Elaborator { +object FPU extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = FPU + type P = FPUParameter + type M = FPUParameterMain + @main case class FPUParameterMain( @arg(name = "useAsyncReset") useAsyncReset: Boolean, @@ -34,11 +44,15 @@ object FPU extends Elaborator { implicit def FPUParameterMainParser: ParserForClass[FPUParameterMain] = ParserForClass[FPUParameterMain] @main - def config(@arg(name = "parameter") parameter: FPUParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[FPU, FPUParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/FPUFMAPipe.scala b/elaborator/src/rocketv/FPUFMAPipe.scala index 71fad27de..c65413339 100644 --- a/elaborator/src/rocketv/FPUFMAPipe.scala +++ b/elaborator/src/rocketv/FPUFMAPipe.scala @@ -2,11 +2,21 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import mainargs._ import org.chipsalliance.rocketv.{FPUFMAPipe, FPUFMAPipeParameter, FType} -import org.chipsalliance.t1.elaborator.Elaborator -object FPUFMAPipe extends Elaborator { +object FPUFMAPipe extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = FPUFMAPipe + type P = FPUFMAPipeParameter + type M = FPUFMAPipeParameterMain + @main case class FPUFMAPipeParameterMain( useAsyncReset: Boolean, @@ -35,11 +45,15 @@ object FPUFMAPipe extends Elaborator { ParserForClass[FPUFMAPipeParameterMain] @main - def config(@arg(name = "parameter") parameter: FPUFMAPipeParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[FPUFMAPipe, FPUFMAPipeParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/Frontend.scala b/elaborator/src/rocketv/Frontend.scala index d5fb53113..b341bf08d 100644 --- a/elaborator/src/rocketv/Frontend.scala +++ b/elaborator/src/rocketv/Frontend.scala @@ -2,13 +2,23 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import chisel3.util.BitPat import chisel3.util.experimental.BitSet import mainargs._ import org.chipsalliance.rocketv.{BHTParameter, Frontend, FrontendParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object Frontend extends Elaborator { +object Frontend extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = Frontend + type P = FrontendParameter + type M = FrontendParameterMain + implicit object BitSetRead extends TokensReader.Simple[BitSet] { def shortName = "bitset" def read(strs: Seq[String]) = { @@ -127,11 +137,15 @@ object Frontend extends Elaborator { ParserForClass[FrontendParameterMain] @main - def config(@arg(name = "parameter") parameter: FrontendParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[Frontend, FrontendParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/IBuf.scala b/elaborator/src/rocketv/IBuf.scala index 26111c4c5..3117b4e54 100644 --- a/elaborator/src/rocketv/IBuf.scala +++ b/elaborator/src/rocketv/IBuf.scala @@ -2,11 +2,21 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import mainargs._ import org.chipsalliance.rocketv.{IBuf, IBufParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object IBuf extends Elaborator { +object IBuf extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = IBuf + type P = IBufParameter + type M = IBufParameterMain + @main case class IBufParameterMain( @arg(name = "useAsyncReset") useAsyncReset: Boolean, @@ -34,11 +44,15 @@ object IBuf extends Elaborator { implicit def IBufParameterMainParser: ParserForClass[IBufParameterMain] = ParserForClass[IBufParameterMain] @main - def config(@arg(name = "parameter") parameter: IBufParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[IBuf, IBufParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/ICache.scala b/elaborator/src/rocketv/ICache.scala index e85757574..2edcc6c8d 100644 --- a/elaborator/src/rocketv/ICache.scala +++ b/elaborator/src/rocketv/ICache.scala @@ -2,11 +2,21 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import mainargs._ import org.chipsalliance.rocketv.{ICache, ICacheParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object ICache extends Elaborator { +object ICache extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = ICache + type P = ICacheParameter + type M = ICacheParameterMain + @main case class ICacheParameterMain( @arg(name = "useAsyncReset") useAsyncReset: Boolean, @@ -32,11 +42,15 @@ object ICache extends Elaborator { implicit def ICacheParameterMainParser: ParserForClass[ICacheParameterMain] = ParserForClass[ICacheParameterMain] @main - def config(@arg(name = "parameter") parameter: ICacheParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[ICache, ICacheParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/IntToFP.scala b/elaborator/src/rocketv/IntToFP.scala index fa64282be..198668411 100644 --- a/elaborator/src/rocketv/IntToFP.scala +++ b/elaborator/src/rocketv/IntToFP.scala @@ -2,11 +2,21 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import mainargs._ import org.chipsalliance.rocketv.{IntToFP, IntToFPParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object IntToFP extends Elaborator { +object IntToFP extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = IntToFP + type P = IntToFPParameter + type M = IntToFPParameterMain + @main case class IntToFPParameterMain( @arg(name = "useAsyncReset") useAsyncReset: Boolean, @@ -26,11 +36,15 @@ object IntToFP extends Elaborator { implicit def IntToFPParameterMainParser: ParserForClass[IntToFPParameterMain] = ParserForClass[IntToFPParameterMain] @main - def config(@arg(name = "parameter") parameter: IntToFPParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[IntToFP, IntToFPParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/MulAddRecFNPipe.scala b/elaborator/src/rocketv/MulAddRecFNPipe.scala index bc8ace996..50c6bd52e 100644 --- a/elaborator/src/rocketv/MulAddRecFNPipe.scala +++ b/elaborator/src/rocketv/MulAddRecFNPipe.scala @@ -2,11 +2,21 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import mainargs._ import org.chipsalliance.rocketv.{MulAddRecFNPipe, MulAddRecFNPipeParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object MulAddRecFNPipe extends Elaborator { +object MulAddRecFNPipe extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = MulAddRecFNPipe + type P = MulAddRecFNPipeParameter + type M = MulAddRecFNPipeParameterMain + @main case class MulAddRecFNPipeParameterMain( @arg(name = "useAsyncReset") useAsyncReset: Boolean, @@ -20,11 +30,15 @@ object MulAddRecFNPipe extends Elaborator { ParserForClass[MulAddRecFNPipeParameterMain] @main - def config(@arg(name = "parameter") parameter: MulAddRecFNPipeParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[MulAddRecFNPipe, MulAddRecFNPipeParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/MulDiv.scala b/elaborator/src/rocketv/MulDiv.scala index c97533591..bc5dd1628 100644 --- a/elaborator/src/rocketv/MulDiv.scala +++ b/elaborator/src/rocketv/MulDiv.scala @@ -2,11 +2,21 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import mainargs._ import org.chipsalliance.rocketv.{DecoderParameter, MulDiv, MulDivParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object MulDiv extends Elaborator { +object MulDiv extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = MulDiv + type P = MulDivParameter + type M = MulDivParameterMain + @main case class MulDivParameterMain( @arg(name = "useAsyncReset") useAsyncReset: Boolean, @@ -41,11 +51,15 @@ object MulDiv extends Elaborator { implicit def MulDivParameterMainParser: ParserForClass[MulDivParameterMain] = ParserForClass[MulDivParameterMain] @main - def config(@arg(name = "parameter") parameter: MulDivParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[MulDiv, MulDivParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/PMAChecker.scala b/elaborator/src/rocketv/PMAChecker.scala index f23d22eaa..8fbd557b3 100644 --- a/elaborator/src/rocketv/PMAChecker.scala +++ b/elaborator/src/rocketv/PMAChecker.scala @@ -2,13 +2,22 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import chisel3.util.BitPat import chisel3.util.experimental.BitSet import mainargs._ import org.chipsalliance.rocketv.{PMAChecker, PMACheckerParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object PMAChecker extends Elaborator { +object PMAChecker extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = PMAChecker + type P = PMACheckerParameter + type M = PMACheckerParameterMain implicit object BitSetRead extends TokensReader.Simple[BitSet] { def shortName = "bitset" @@ -67,11 +76,15 @@ object PMAChecker extends Elaborator { ParserForClass[PMACheckerParameterMain] @main - def config(@arg(name = "parameter") parameter: PMACheckerParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[PMAChecker, PMACheckerParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/PMP.scala b/elaborator/src/rocketv/PMP.scala index f7dd45515..f767b58ee 100644 --- a/elaborator/src/rocketv/PMP.scala +++ b/elaborator/src/rocketv/PMP.scala @@ -2,11 +2,21 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import mainargs._ import org.chipsalliance.rocketv.{PMPChecker, PMPCheckerParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object PMPChecker extends Elaborator { +object PMPChecker extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = PMPChecker + type P = PMPCheckerParameter + type M = PMPCheckerParameterMain + @main case class PMPCheckerParameterMain( @arg(name = "nPMPs") nPMPs: Int, @@ -25,11 +35,15 @@ object PMPChecker extends Elaborator { ParserForClass[PMPCheckerParameterMain] @main - def config(@arg(name = "parameter") parameter: PMPCheckerParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[PMPChecker, PMPCheckerParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/PTW.scala b/elaborator/src/rocketv/PTW.scala index 7b8cb19d7..e067a04e0 100644 --- a/elaborator/src/rocketv/PTW.scala +++ b/elaborator/src/rocketv/PTW.scala @@ -2,11 +2,21 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import mainargs._ import org.chipsalliance.rocketv.{PTW, PTWParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object PTW extends Elaborator { +object PTW extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = PTW + type P = PTWParameter + type M = PTWParameterMain + @main case class PTWParameterMain( @arg(name = "useAsyncReset") useAsyncReset: Boolean, @@ -42,11 +52,15 @@ object PTW extends Elaborator { implicit def PTWParameterMainParser: ParserForClass[PTWParameterMain] = ParserForClass[PTWParameterMain] @main - def config(@arg(name = "parameter") parameter: PTWParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[PTW, PTWParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/PipelinedMultiplier.scala b/elaborator/src/rocketv/PipelinedMultiplier.scala index 59d06cde3..01f7c94f4 100644 --- a/elaborator/src/rocketv/PipelinedMultiplier.scala +++ b/elaborator/src/rocketv/PipelinedMultiplier.scala @@ -2,11 +2,21 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import mainargs._ import org.chipsalliance.rocketv.{PipelinedMultiplier, PipelinedMultiplierParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object PipelinedMultiplier extends Elaborator { +object PipelinedMultiplier extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = PipelinedMultiplier + type P = PipelinedMultiplierParameter + type M = PipelinedMultiplierParameterMain + @main case class PipelinedMultiplierParameterMain( @arg(name = "useAsyncReset") useAsyncReset: Boolean, @@ -23,11 +33,15 @@ object PipelinedMultiplier extends Elaborator { ParserForClass[PipelinedMultiplierParameterMain] @main - def config(@arg(name = "parameter") parameter: PipelinedMultiplierParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[PipelinedMultiplier, PipelinedMultiplierParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/RVCExpander.scala b/elaborator/src/rocketv/RVCExpander.scala index df6e9ce5d..8d492b887 100644 --- a/elaborator/src/rocketv/RVCExpander.scala +++ b/elaborator/src/rocketv/RVCExpander.scala @@ -2,11 +2,21 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import mainargs._ import org.chipsalliance.rocketv.{RVCExpander, RVCExpanderParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object RVCExpander extends Elaborator { +object RVCExpander extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = RVCExpander + type P = RVCExpanderParameter + type M = RVCExpanderParameterMain + @main case class RVCExpanderParameterMain( @arg(name = "xLen") xLen: Int, @@ -21,11 +31,15 @@ object RVCExpander extends Elaborator { ParserForClass[RVCExpanderParameterMain] @main - def config(@arg(name = "parameter") parameter: RVCExpanderParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[RVCExpander, RVCExpanderParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/Rocket.scala b/elaborator/src/rocketv/Rocket.scala index 183e9fe0e..3ed392466 100644 --- a/elaborator/src/rocketv/Rocket.scala +++ b/elaborator/src/rocketv/Rocket.scala @@ -2,11 +2,21 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import mainargs._ import org.chipsalliance.rocketv.{Rocket, RocketParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object Rocket extends Elaborator { +object Rocket extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = Rocket + type P = RocketParameter + type M = RocketParameterMain + @main case class RocketParameterMain( @arg(name = "useAsyncReset") useAsyncReset: Boolean, @@ -70,11 +80,15 @@ object Rocket extends Elaborator { implicit def RocketParameterMainParser: ParserForClass[RocketParameterMain] = ParserForClass[RocketParameterMain] @main - def config(@arg(name = "parameter") parameter: RocketParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[Rocket, RocketParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/RocketTile.scala b/elaborator/src/rocketv/RocketTile.scala index 514eb0388..390c5febe 100644 --- a/elaborator/src/rocketv/RocketTile.scala +++ b/elaborator/src/rocketv/RocketTile.scala @@ -2,15 +2,25 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import chisel3.util.BitPat import chisel3.util.experimental.BitSet import mainargs._ import org.chipsalliance.rocketv.{BHTParameter, RocketTile, RocketTileParameter} -import org.chipsalliance.t1.elaborator.Elaborator // --useAsyncReset true --clockGate true --instructionSets rv32_i --priv m --hartIdLen 4 --useBPWatch false --mcontextWidth 0 --scontextWidth 0 --asidBits 0 --resetVectorBits 32 --nBreakpoints 0 --dtlbNWays 0 --dtlbNSets 0 --itlbNSets 0 --itlbNWays 0 --itlbNSectors 0 --itlbNSuperpageEntries 0 --nPTECacheEntries 0 --nL2TLBWays 0 --nL2TLBEntries 0 --paddrBits 32 --cacheBlockBytes 32 --nPMPs 8 --legal 00000000-ffffffff --cacheable 80000000-ffffffff --read 00000000-ffffffff --write 00000000-ffffffff --putPartial 00000000-ffffffff --logic 0 --arithmetic 0 --exec 80000000-ffffffff --sideEffects 00000000-3fffffff --btbEntries 28 --btbNMatchBits 14 --btbUpdatesOutOfOrder false --nPages 6 --nRAS 6 --bhtNEntries 512 --bhtCounterLength 1 --bhtHistoryLength 8 --bhtHistoryBits 3 --mulDivLatency 2 --divUnroll 1 --divEarlyOut false --divEarlyOutGranularity 0 --mulUnroll 1 --mulEarlyOut false --sfmaLatency 3 --dfmaLatency 3 --divSqrt true --flushOnFenceI true --fastLoadByte false --fastLoadWord false --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --maxUncachedInFlight 1 --separateUncachedResp false --iCacheNSets 64 --iCacheNWays 4 --iCachePrefetch false -object RocketTile extends Elaborator { +object RocketTile extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = RocketTile + type P = RocketTileParameter + type M = RocketTileParameterMain + implicit object BitSetRead extends TokensReader.Simple[BitSet] { def shortName = "bitset" def read(strs: Seq[String]) = { @@ -181,11 +191,15 @@ object RocketTile extends Elaborator { ParserForClass[RocketTileParameterMain] @main - def config(@arg(name = "parameter") parameter: RocketTileParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[RocketTile, RocketTileParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/rocketv/TLB.scala b/elaborator/src/rocketv/TLB.scala index c7a2e4ef4..14f09d56e 100644 --- a/elaborator/src/rocketv/TLB.scala +++ b/elaborator/src/rocketv/TLB.scala @@ -2,13 +2,23 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.rocketv +import chisel3.experimental.util.SerializableModuleElaborator import chisel3.util.BitPat import chisel3.util.experimental.BitSet import mainargs._ import org.chipsalliance.rocketv.{TLB, TLBParameter} -import org.chipsalliance.t1.elaborator.Elaborator -object TLB extends Elaborator { +object TLB extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = TLB + type P = TLBParameter + type M = TLBParameterMain + implicit object BitSetRead extends TokensReader.Simple[BitSet] { def shortName = "bitset" def read(strs: Seq[String]) = { @@ -103,11 +113,15 @@ object TLB extends Elaborator { implicit def TLBParameterMainParser: ParserForClass[TLBParameterMain] = ParserForClass[TLBParameterMain] @main - def config(@arg(name = "parameter") parameter: TLBParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[TLB, TLBParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/t1/T1.scala b/elaborator/src/t1/T1.scala new file mode 100644 index 000000000..dad8f2633 --- /dev/null +++ b/elaborator/src/t1/T1.scala @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2024 Jiuyang Liu +package org.chipsalliance.t1.elaborator.t1 + +import chisel3.experimental.util.SerializableModuleElaborator +import mainargs._ +import org.chipsalliance.t1.rtl.vrf.RamType +import org.chipsalliance.t1.rtl.vrf.RamType.{p0rp1w, p0rw, p0rwp1rw} +import org.chipsalliance.t1.rtl.{T1, T1Parameter, VFUInstantiateParameter} + +object T1 extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = T1 + type P = T1Parameter + type M = T1ParameterMain + + implicit object RamTypeRead extends TokensReader.Simple[RamType] { + def shortName = "ramtype" + def read(strs: Seq[String]) = { + Right( + strs.head match { + case "p0rw" => p0rw + case "p0rp1w" => p0rp1w + case "p0rwp1rw" => p0rwp1rw + } + ) + } + } + + @main + case class T1ParameterMain( + @arg(name = "dLen") dLen: Int, + @arg(name = "extensions") extensions: Seq[String], + @arg(name = "vrfBankSize") vrfBankSize: Int, + @arg(name = "vrfRamType") vrfRamType: RamType, + @arg(name = "vfuInstantiateParameter") vfuInstantiateParameter: String) { + def convert: P = { + val fp = extensions.contains("zve32f") + val zvbb = extensions.contains("zvbb") + def vLen: Int = extensions.collectFirst { case s"zvl${vlen}b" => + vlen.toInt + }.get + + T1Parameter( + dLen, + extensions, + vrfBankSize, + vrfRamType, + VFUInstantiateParameter.parse(vLen = vLen, dLen = dLen, preset = vfuInstantiateParameter, fp = fp, zvbb = zvbb) + ) + } + } + + implicit def T1ParameterMainParser: ParserForClass[M] = ParserForClass[M] + + @main + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) + + @main + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } + + def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) +} diff --git a/elaborator/src/t1emu/Testbench.scala b/elaborator/src/t1emu/Testbench.scala new file mode 100644 index 000000000..8ef0cf01f --- /dev/null +++ b/elaborator/src/t1emu/Testbench.scala @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2024 Jiuyang Liu +package org.chipsalliance.t1.elaborator.t1emu + +import chisel3.experimental.util.SerializableModuleElaborator +import mainargs._ +import org.chipsalliance.t1.rtl.vrf.RamType +import org.chipsalliance.t1.rtl.vrf.RamType.{p0rp1w, p0rw, p0rwp1rw} +import org.chipsalliance.t1.rtl.{T1Parameter, VFUInstantiateParameter} +import org.chipsalliance.t1.t1emu.TestBench + +object Testbench extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = TestBench + type P = T1Parameter + type M = T1ParameterMain + + implicit object RamTypeRead extends TokensReader.Simple[RamType] { + def shortName = "ramtype" + def read(strs: Seq[String]) = { + Right( + strs.head match { + case "p0rw" => p0rw + case "p0rp1w" => p0rp1w + case "p0rwp1rw" => p0rwp1rw + } + ) + } + } + + @main + case class T1ParameterMain( + @arg(name = "dLen") dLen: Int, + @arg(name = "extensions") extensions: Seq[String], + @arg(name = "vrfBankSize") vrfBankSize: Int, + @arg(name = "vrfRamType") vrfRamType: RamType, + @arg(name = "vfuInstantiateParameter") vfuInstantiateParameter: String) { + def convert: P = { + val fp = extensions.contains("zve32f") + val zvbb = extensions.contains("zvbb") + def vLen: Int = extensions.collectFirst { case s"zvl${vlen}b" => + vlen.toInt + }.get + + T1Parameter( + dLen, + extensions, + vrfBankSize, + vrfRamType, + VFUInstantiateParameter.parse(vLen = vLen, dLen = dLen, preset = vfuInstantiateParameter, fp = fp, zvbb = zvbb) + ) + } + } + + implicit def T1ParameterMainParser: ParserForClass[M] = ParserForClass[M] + + @main + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) + + @main + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } + + def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) +} diff --git a/elaborator/src/t1rocket/T1RocketTile.scala b/elaborator/src/t1rocket/T1RocketTile.scala index c618fd7f2..fb7032dcc 100644 --- a/elaborator/src/t1rocket/T1RocketTile.scala +++ b/elaborator/src/t1rocket/T1RocketTile.scala @@ -2,16 +2,27 @@ // SPDX-FileCopyrightText: 2024 Jiuyang Liu package org.chipsalliance.t1.elaborator.t1rocketv +import chisel3.experimental.util.SerializableModuleElaborator import chisel3.util.BitPat import chisel3.util.experimental.BitSet import mainargs._ -import org.chipsalliance.t1.elaborator.Elaborator +import org.chipsalliance.t1.rtl.VFUInstantiateParameter import org.chipsalliance.t1.rtl.vrf.RamType import org.chipsalliance.t1.rtl.vrf.RamType.{p0rp1w, p0rw, p0rwp1rw} import org.chipsalliance.t1.tile.{T1RocketTile, T1RocketTileParameter} // --instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --instructionSets Zve32x --instructionSets zvl1024b --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 2 --vrfRamType p0rp1w -object T1RocketTile extends Elaborator { +object T1RocketTile extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = T1RocketTile + type P = T1RocketTileParameter + type M = T1RocketTileParameterMain + implicit object BitSetRead extends TokensReader.Simple[BitSet] { def shortName = "bitset" def read(strs: Seq[String]) = { @@ -68,34 +79,48 @@ object T1RocketTile extends Elaborator { @arg(name = "iCachePrefetch") iCachePrefetch: Boolean, @arg(name = "dLen") dLen: Int, @arg(name = "vrfBankSize") vrfBankSize: Int, - @arg(name = "vrfRamType") vrfRamType: RamType) { - def convert: T1RocketTileParameter = T1RocketTileParameter( - instructionSets: Seq[String], - cacheBlockBytes: Int, - nPMPs: Int, - cacheable: BitSet, - sideEffects: BitSet, - dcacheNSets: Int, - dcacheNWays: Int, - dcacheRowBits: Int, - iCacheNSets: Int, - iCacheNWays: Int, - iCachePrefetch: Boolean, - dLen: Int, - vrfBankSize: Int, - vrfRamType: RamType - ) + @arg(name = "vrfRamType") vrfRamType: RamType, + @arg(name = "vfuInstantiateParameter") vfuInstantiateParameter: String) { + def convert: T1RocketTileParameter = { + val vLen = instructionSets.collectFirst { case s"zvl${vlen}b" => + vlen.toInt + }.get + val fp = instructionSets.contains("zve32f") + val zvbb = instructionSets.contains("zvbb") + + T1RocketTileParameter( + instructionSets: Seq[String], + cacheBlockBytes: Int, + nPMPs: Int, + cacheable: BitSet, + sideEffects: BitSet, + dcacheNSets: Int, + dcacheNWays: Int, + dcacheRowBits: Int, + iCacheNSets: Int, + iCacheNWays: Int, + iCachePrefetch: Boolean, + dLen: Int, + vrfBankSize: Int, + vrfRamType: RamType, + VFUInstantiateParameter.parse(vLen = vLen, dLen = dLen, preset = vfuInstantiateParameter, fp = fp, zvbb = zvbb) + ) + } } implicit def T1RocketTileParameterMainParser: ParserForClass[T1RocketTileParameterMain] = ParserForClass[T1RocketTileParameterMain] @main - def config(@arg(name = "parameter") parameter: T1RocketTileParameterMain) = configImpl(parameter.convert) + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) @main - def design(@arg(name = "parameter") parameter: os.Path, @arg(name = "run-firtool") runFirtool: mainargs.Flag) = - designImpl[T1RocketTile, T1RocketTileParameter](parameter, runFirtool.value) + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) } diff --git a/elaborator/src/t1rocketemu/Testbench.scala b/elaborator/src/t1rocketemu/Testbench.scala new file mode 100644 index 000000000..45371867c --- /dev/null +++ b/elaborator/src/t1rocketemu/Testbench.scala @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2024 Jiuyang Liu +package org.chipsalliance.t1.elaborator.t1rocketemu + +import chisel3.experimental.util.SerializableModuleElaborator +import chisel3.util.BitPat +import chisel3.util.experimental.BitSet +import mainargs._ +import org.chipsalliance.t1.rtl.VFUInstantiateParameter +import org.chipsalliance.t1.rtl.vrf.RamType +import org.chipsalliance.t1.rtl.vrf.RamType.{p0rp1w, p0rw, p0rwp1rw} +import org.chipsalliance.t1.t1rocketemu.TestBench +import org.chipsalliance.t1.tile.T1RocketTileParameter + +// --instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --instructionSets Zve32x --instructionSets zvl1024b --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 2 --vrfRamType p0rp1w +object T1RocketTile extends SerializableModuleElaborator { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]) = Right(os.Path(strs.head, os.pwd)) + } + + val className: String = getClass.getSimpleName.replace("$", "") + type D = TestBench + type P = T1RocketTileParameter + type M = T1RocketTileParameterMain + + implicit object BitSetRead extends TokensReader.Simple[BitSet] { + def shortName = "bitset" + def read(strs: Seq[String]) = { + Right( + strs.head + .split(",") + .map { opt => + if (opt.contains("-")) { + val range = opt.split("-") + require(range.size == 2) + val from = BigInt(range.head, 16) + val to = BigInt(range.last, 16) + 1 + BitSet.fromRange(from, to - from, range.head.length * 4) + } else if (opt.contains("+")) { + val range = opt.split("\\+") + require(range.size == 2) + val from = BigInt(range.head, 16) + val length = BigInt(range.last, 16) + BitSet.fromRange(from, length, range.head.length * 4) + } else { + BitPat(s"b$opt") + } + } + .reduce(_.union(_)) + ) + } + } + + implicit object RamTypeRead extends TokensReader.Simple[RamType] { + def shortName = "ramtype" + def read(strs: Seq[String]) = { + Right( + strs.head match { + case "p0rw" => p0rw + case "p0rp1w" => p0rp1w + case "p0rwp1rw" => p0rwp1rw + } + ) + } + } + + @main + case class T1RocketTileParameterMain( + @arg(name = "instructionSets") instructionSets: Seq[String], + @arg(name = "cacheBlockBytes") cacheBlockBytes: Int, + @arg(name = "nPMPs") nPMPs: Int, + @arg(name = "cacheable") cacheable: BitSet, + @arg(name = "sideEffects") sideEffects: BitSet, + @arg(name = "dcacheNSets") dcacheNSets: Int, + @arg(name = "dcacheNWays") dcacheNWays: Int, + @arg(name = "dcacheRowBits") dcacheRowBits: Int, + @arg(name = "iCacheNSets") iCacheNSets: Int, + @arg(name = "iCacheNWays") iCacheNWays: Int, + @arg(name = "iCachePrefetch") iCachePrefetch: Boolean, + @arg(name = "dLen") dLen: Int, + @arg(name = "vrfBankSize") vrfBankSize: Int, + @arg(name = "vrfRamType") vrfRamType: RamType, + @arg(name = "vfuInstantiateParameter") vfuInstantiateParameter: String) { + def convert: T1RocketTileParameter = { + val vLen = instructionSets.collectFirst { case s"zvl${vlen}b" => + vlen.toInt + }.get + val fp = instructionSets.contains("zve32f") + val zvbb = instructionSets.contains("zvbb") + + T1RocketTileParameter( + instructionSets: Seq[String], + cacheBlockBytes: Int, + nPMPs: Int, + cacheable: BitSet, + sideEffects: BitSet, + dcacheNSets: Int, + dcacheNWays: Int, + dcacheRowBits: Int, + iCacheNSets: Int, + iCacheNWays: Int, + iCachePrefetch: Boolean, + dLen: Int, + vrfBankSize: Int, + vrfRamType: RamType, + VFUInstantiateParameter.parse(vLen = vLen, dLen = dLen, preset = vfuInstantiateParameter, fp = fp, zvbb = zvbb) + ) + } + } + + implicit def T1RocketTileParameterMainParser: ParserForClass[T1RocketTileParameterMain] = + ParserForClass[T1RocketTileParameterMain] + + @main + def config(@arg(name = "parameter") parameter: M) = + os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) + + @main + def design(@arg(name = "parameter") parameter: os.Path) = { + val (firrtl, annos) = designImpl[D, P](os.read.stream(parameter)) + os.write.over(os.pwd / s"$className.fir", firrtl) + os.write.over(os.pwd / s"$className.json", annos) + } + + def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) +} diff --git a/nix/t1/conversion/chisel-to-mlirbc.nix b/nix/t1/conversion/chisel-to-mlirbc.nix index 10a643c6b..04568c69b 100644 --- a/nix/t1/conversion/chisel-to-mlirbc.nix +++ b/nix/t1/conversion/chisel-to-mlirbc.nix @@ -8,38 +8,40 @@ }: { outputName -, elaboratorArgs ? null +, generatorClassName +, elaboratorArgs }: -assert lib.assertMsg (elaboratorArgs != null) "elaborateArgs is not set"; -assert lib.assertMsg (builtins.typeOf elaboratorArgs == "list") "elaborateArgs is not a list"; -assert lib.assertMsg (!(lib.elem "--target-dir" elaboratorArgs)) "--target-dir is set internally, please remove it from top scope"; +assert lib.assertMsg (builtins.typeOf elaboratorArgs == "string") "elaborateArgs should be string"; +assert lib.assertMsg (builtins.typeOf generatorClassName == "string") "arg `generator` should be string"; +assert lib.assertMsg (lib.hasPrefix "org.chipsalliance.t1" generatorClassName) "Wrong generator name ${generatorClassName}"; +assert lib.assertMsg (!(lib.hasInfix generatorClassName elaboratorArgs)) "Duplicated generator name in elaboratorArgs"; -let - elaborateArgStr = lib.escapeShellArgs elaboratorArgs; -in stdenvNoCC.mkDerivation { name = outputName; nativeBuildInputs = [ espresso circt ]; - elaborateOutDir = "elaborate"; buildCommand = '' - mkdir -p "$out" "$elaborateOutDir" + mkdir -p "$out" - # --------------------------------------------------------------------------------- - # Run elaborator - # --------------------------------------------------------------------------------- - elaborateProc="${elaborator}/bin/elaborator ${elaborateArgStr} --target-dir $elaborateOutDir" - echo "[nix] running elaborator: $elaborateProc" - $builder -c "$elaborateProc" + mkdir stage1 && pushd stage1 + + elaborateProc="${elaborator}/bin/elaborator ${generatorClassName} ${elaboratorArgs}" + echo "[nix] Generating config with cmd opt: $elaborateProc" + eval "$elaborateProc" + popd + + mkdir stage2 && pushd stage2 + echo "[nix] Elaborating with generated config" + ${elaborator}/bin/elaborator ${generatorClassName} design --parameter ../stage1/*.json # --------------------------------------------------------------------------------- # Run circt toolchain # --------------------------------------------------------------------------------- echo "[nix] elaborate finish, parsing output with firtool" - firtool elaborate/*.fir \ - --annotation-file elaborate/*.anno.json \ + firtool *.fir \ + --annotation-file *.json \ --emit-bytecode \ --parse-only \ -o $out/$name diff --git a/nix/t1/default.nix b/nix/t1/default.nix index 01c91d11c..b176e0177 100644 --- a/nix/t1/default.nix +++ b/nix/t1/default.nix @@ -8,16 +8,35 @@ let moldStdenv = useMoldLinker stdenv; - t1ConfigsDir = ../../configgen/generated; + t1DesignsConfigsDir = ../../designs; - # allConfigs is a (configName -> configJsonPath) map - allConfigs = lib.mapAttrs' - (fileName: fileType: - assert fileType == "regular" && lib.hasSuffix ".json" fileName; - lib.nameValuePair - (lib.removeSuffix ".json" fileName) - (lib.path.append t1ConfigsDir fileName)) - (builtins.readDir t1ConfigsDir); + allConfigs = lib.pipe t1DesignsConfigsDir [ + builtins.readDir + # => { "filename" -> "filetype" } + (lib.mapAttrs' + (fileName: fileType: + assert fileType == "regular" && lib.hasSuffix ".toml" fileName; + lib.nameValuePair + (lib.removeSuffix ".toml" fileName) + (lib.path.append t1DesignsConfigsDir fileName))) + # => { "filename without .toml suffix, use as generator className" -> "realpath to config" } + (lib.mapAttrs + (_: filePath: with builtins; fromTOML (readFile filePath))) + # => { "generator className" -> { "elaborator configName" -> "elaborator cmd opt" } } + lib.attrsToList + # => [ { name: "generator className", value: { "configName": { "cmd opt": } } }, ... ] + (map + (kv: lib.mapAttrs' + (configName: configData: + lib.nameValuePair configName { "${kv.name}" = configData; }) + kv.value)) + # => [ { "configName": { "generator className" = { cmdopt: ; }; } }, ... ] + (lib.foldl + (accum: item: + lib.recursiveUpdate accum item) + { }) + # => { "configName A": { "generator A" = { cmdopt }, "generator B" = { cmdopt } }; "configName B" = ...; ... } + ]; in lib.makeScope newScope (t1Scope: @@ -32,7 +51,7 @@ lib.makeScope newScope # --------------------------------------------------------------------------------- _t1MillModules = t1Scope.callPackage ./mill-modules.nix { }; elaborator = t1Scope._t1MillModules.elaborator // { meta.mainProgram = "elaborator"; }; - configgen = t1Scope._t1MillModules.configgen // { meta.mainProgram = "configgen"; }; + omreader-unwrapped = t1Scope._t1MillModules.omreader // { meta.mainProgram = "omreader"; }; t1package = t1Scope._t1MillModules.t1package; # --------------------------------------------------------------------------------- @@ -82,16 +101,6 @@ lib.makeScope newScope # sv-to-vcs-simulator will compile the given rtl, link with path specified in vcsLinksLibs to produce a VCS emulator. # enableTrace is false by default; sv-to-vcs-simulator = t1Scope.callPackage ./conversion/sv-to-vcs-simulator.nix { }; - - # --------------------------------------------------------------------------------- - # Grouped emulator packages - # --------------------------------------------------------------------------------- - # Nix specification for t1rocket (with rocket-chip as Scalar core) emulator - t1rocket = t1Scope.callPackage ./t1rocket.nix { }; - # Nix specification for rocket (rocket-chip only) emulator - rocketv = t1Scope.callPackage ../../rocketemu { }; - - omreader-unwrapped = t1Scope.callPackage ./omreader.nix { }; } # Nix specification for t1 (with spike only) emulator # We don't expect extra scope for t1 stuff, so here we merge the t1 at t1Scope level. diff --git a/nix/t1/mill-modules.nix b/nix/t1/mill-modules.nix index 058e6690c..00f1c193e 100644 --- a/nix/t1/mill-modules.nix +++ b/nix/t1/mill-modules.nix @@ -29,7 +29,6 @@ let ./../../omreaderlib ./../../t1emu/src ./../../elaborator - ./../../configgen/src ./../../rocketv ./../../t1rocket/src ./../../t1rocketemu/src @@ -80,16 +79,16 @@ let env = { CIRCT_INSTALL_PATH = circt-full; JEXTRACT_INSTALL_PATH = jextract-21; + JAVA_TOOL_OPTIONS = "--enable-preview"; }; - outputs = [ "out" "configgen" "elaborator" "t1package" ]; + outputs = [ "out" "omreader" "elaborator" "t1package" ]; # Check code format before starting build, so that we can enforce all developer run reformat before build. configurePhase = '' runHook preConfigure _targetsToCheck=( - "configgen" "elaborator" "omreader" "omreaderlib" @@ -129,22 +128,30 @@ let add-determinism $@ >/dev/null } add-determinism-q out/elaborator/assembly.dest/out.jar - add-determinism-q out/configgen/assembly.dest/out.jar + add-determinism-q out/omreader/assembly.dest/out.jar add-determinism-q out/t1package/assembly.dest/out.jar add-determinism-q out/t1package/sourceJar.dest/out.jar add-determinism-q out/t1package/chiselPluginJar.dest/out.jar - mv out/configgen/assembly.dest/out.jar $out/share/java/configgen.jar mv out/elaborator/assembly.dest/out.jar $out/share/java/elaborator.jar + mv out/omreader/assembly.dest/out.jar "$out"/share/java/omreader.jar mkdir -p $t1package/share/java mv out/t1package/sourceJar.dest/out.jar $t1package/share/java/t1package-sources.jar mv out/t1package/assembly.dest/out.jar $t1package/share/java/t1package.jar mv out/t1package/chiselPluginJar.dest/out.jar $t1package/share/java/chiselPluginJar.jar - mkdir -p $configgen/bin $elaborator/bin - makeWrapper ${jdk21}/bin/java $configgen/bin/configgen --add-flags "-jar $out/share/java/configgen.jar" - makeWrapper ${jdk21}/bin/java $elaborator/bin/elaborator --add-flags "--enable-preview -Djava.library.path=${circt-full}/lib -cp $out/share/java/elaborator.jar org.chipsalliance.t1.elaborator.Main" + mkdir -p $elaborator/bin + makeWrapper ${jdk21}/bin/java $elaborator/bin/elaborator \ + --add-flags "--enable-preview -Djava.library.path=${circt-full}/lib" \ + --add-flags "-cp $out/share/java/elaborator.jar" + + mkdir -p $omreader/bin + makeWrapper ${jdk21}/bin/java "$omreader"/bin/omreader \ + --add-flags "--enable-preview" \ + --add-flags "--enable-native-access=ALL-UNNAMED" \ + --add-flags "-Djava.library.path=${circt-full}/lib" \ + --add-flags "-cp $out/share/java/omreader.jar" ''; }; in diff --git a/nix/t1/omreader.nix b/nix/t1/omreader.nix deleted file mode 100644 index 6e9d496a6..000000000 --- a/nix/t1/omreader.nix +++ /dev/null @@ -1,104 +0,0 @@ -{ lib -, stdenv -, runCommand -, fetchMillDeps -, makeWrapper -, jdk21 - - # chisel deps -, mill -, git -, circt-full -, jextract-21 -, strip-nondeterminism - -, dependencies -}: - -let - self = stdenv.mkDerivation rec { - name = "omreader"; - - src = with lib.fileset; toSource { - root = ./../..; - fileset = unions [ - ./../../build.sc - ./../../common.sc - ./../../omreader - ./../../omreaderlib - ]; - }; - - passthru.millDeps = fetchMillDeps { - inherit name; - src = with lib.fileset; toSource { - root = ./../..; - fileset = unions [ - ./../../build.sc - ./../../common.sc - ./../../.scalafmt.conf - ]; - }; - millDepsHash = "sha256-pixG96IxJsYlgIU+DVxGHky6G5nMfHXphEq5A/xLP7Q="; - nativeBuildInputs = [ dependencies.setupHook ]; - }; - - passthru = { - editable = self.overrideAttrs (_: { - shellHook = '' - setupSubmodulesEditable - mill mill.bsp.BSP/install 0 - ''; - }); - - mkWrapper = { mlirbc }: runCommand "wrap-omreader" - { nativeBuildInputs = [ makeWrapper ]; meta.mainProgram = "omreader"; } - '' - mkdir -p "$out/bin" - mlirbc=$(find ${mlirbc}/ -type f) - makeWrapper ${self}/bin/omreader "$out/bin/omreader" --append-flags "--mlirbc-file $mlirbc" - ''; - }; - - shellHook = '' - setupSubmodules - ''; - - nativeBuildInputs = [ - mill - jextract-21 - strip-nondeterminism - circt-full - git - - makeWrapper - passthru.millDeps.setupHook - - dependencies.setupHook - ]; - - env = { - JEXTRACT_INSTALL_PATH = jextract-21; - CIRCT_INSTALL_PATH = circt-full; - JAVA_TOOL_OPTIONS = "--enable-preview"; - }; - - buildPhase = '' - mill -i 'omreader.assembly' - ''; - - installPhase = '' - mkdir -p "$out"/bin "$out"/share/java - strip-nondeterminism out/omreader/assembly.dest/out.jar - mv out/omreader/assembly.dest/out.jar "$out"/share/java/omreader.jar - makeWrapper ${jdk21}/bin/java "$out"/bin/omreader --add-flags "--enable-preview --enable-native-access=ALL-UNNAMED -Djava.library.path=${circt-full}/lib -jar $out/share/java/omreader.jar" - echo "$(cat "$out"/bin/omreader) 2> /dev/null" > "$out"/bin/omreader - ''; - - meta = { - description = "CLI reads OM properties from MLIR bytecodes"; - mainProgram = "omreader"; - }; - }; -in -self diff --git a/nix/t1/run/default.nix b/nix/t1/run/default.nix index c41454131..8ef0d509c 100644 --- a/nix/t1/run/default.nix +++ b/nix/t1/run/default.nix @@ -7,6 +7,7 @@ , vcs-emu-trace , cases , configName +, topName }: let runVerilatorEmu = callPackage ./run-verilator-emu.nix { }; @@ -41,7 +42,7 @@ let _getAllResult = emuType: let testPlan = builtins.fromJSON - (lib.readFile ../../../.github/${if configName == "t1rocket" then "t1rocket-cases" else "cases"}/${configName}/default.json); + (lib.readFile ../../../.github/designs/${configName}/${topName}.json); # flattern the attr set to a list of test case derivations # AttrSet (AttrSet Derivation) -> List Derivation allCasesResult = lib.pipe emuAttrs [ diff --git a/nix/t1/t1.nix b/nix/t1/t1.nix index 3f6daa337..7f1111539 100644 --- a/nix/t1/t1.nix +++ b/nix/t1/t1.nix @@ -2,171 +2,135 @@ # return attribute set with following hierarchy: # { -# "blastoise": { ip = { mlirbc = ...; vcs-emu = ...; ... } } -# "...": { ip = { mlirbc = ...; vcs-emu = ...; ... } } +# "blastoise": { generatorName = { mlirbc = ...; vcs-emu = ...; ... } } +# "...": { generatorName = { mlirbc = ...; vcs-emu = ...; ... } } # } lib.mapAttrs - (configName: configPath: - # by using makeScope, callPackage can send the following attributes to package parameters - lib.makeScope t1Scope.newScope (cfgScope: rec { - recurseForDerivations = true; - - # For package name concatenate - inherit configName; - - elaborateConfigJson = configPath; - elaborateConfig = builtins.fromJSON (lib.readFile configPath); - - ip = lib.makeScope cfgScope.newScope (ipScope: { - recurseForDerivations = true; - - cases = ipScope.callPackage ../../tests { }; - - # --------------------------------------------------------------------------------- - # T1 only, without test bench - # --------------------------------------------------------------------------------- - mlirbc = t1Scope.chisel-to-mlirbc { - outputName = "t1-non-testbench.mlirbc"; - elaboratorArgs = [ - "ip" - "--ip-config" - "${elaborateConfigJson}" - ]; - }; - - lowered-mlirbc = t1Scope.finalize-mlirbc { - outputName = "lowered-" + ipScope.mlirbc.name; - mlirbc = ipScope.mlirbc; - }; - - rtl = t1Scope.mlirbc-to-sv { - outputName = "t1-non-testbench-rtl"; - mlirbc = ipScope.lowered-mlirbc; - mfcArgs = [ - "-O=release" - "--disable-all-randomization" - "--split-verilog" - "--preserve-values=all" - "--strip-debug-info" - "--strip-fir-debug-info" - "--verification-flavor=sva" - "--lowering-options=verifLabels,omitVersionComment,emittedLineLength=240,locationInfoStyle=none" - ]; - }; - - omreader = t1Scope.omreader-unwrapped.mkWrapper { mlirbc = ipScope.lowered-mlirbc; }; - - # --------------------------------------------------------------------------------- - # T1 with test bench - # --------------------------------------------------------------------------------- - emu-mlirbc = t1Scope.chisel-to-mlirbc { - outputName = "t1-emu.mlirbc"; - elaboratorArgs = [ "t1emu" "--ip-config" "${elaborateConfigJson}" ]; - }; - - lowered-emu-mlirbc = t1Scope.finalize-mlirbc { - outputName = "lowered" + ipScope.emu-mlirbc.outputName; - mlirbc = ipScope.emu-mlirbc; - }; - - emu-rtl = t1Scope.mlirbc-to-sv { - outputName = "t1-emu-rtl"; - mlirbc = ipScope.lowered-emu-mlirbc; - mfcArgs = [ - "-O=release" - "--split-verilog" - "--preserve-values=all" - "--verification-flavor=if-else-fatal" - "--lowering-options=verifLabels,omitVersionComment" - "--strip-debug-info" - ]; - }; - - emu-omreader = t1Scope.omreader-unwrapped.mkWrapper { mlirbc = ipScope.lowered-emu-mlirbc; }; - omGet = args: lib.toLower (lib.fileContents (runCommand "get-${args}" { } '' - ${ipScope.emu-omreader}/bin/omreader ${args} > $out - '')); - rtlDesignMetadata = with ipScope; rec { - march = omGet "march"; - extensions = builtins.fromJSON (omGet "extensionsJson"); - vlen = omGet "vlen"; - dlen = omGet "dlen"; - xlen = if (lib.hasPrefix "rv32" march) then 32 else 64; - }; - - # --------------------------------------------------------------------------------- - # VERILATOR - # --------------------------------------------------------------------------------- - makeDifftest = ipScope.callPackage ../../difftest { }; - - verilator-dpi-lib = ipScope.makeDifftest { - outputName = "t1-verilator-dpi-lib"; - emuType = "verilator"; - moduleType = "dpi_t1"; - }; - verilator-dpi-lib-trace = ipScope.makeDifftest { - outputName = "t1-verilator-trace-dpi-lib"; - emuType = "verilator"; - moduleType = "dpi_t1"; - enableTrace = true; - }; - - verilator-emu = t1Scope.sv-to-verilator-emulator { - mainProgram = "t1-verilated-simulator"; - rtl = ipScope.emu-rtl; - extraVerilatorArgs = [ "${ipScope.verilator-dpi-lib}/lib/libdpi_t1.a" ]; - }; - verilator-emu-trace = t1Scope.sv-to-verilator-emulator { - mainProgram = "t1-verilated-trace-simulator"; - rtl = ipScope.emu-rtl; - enableTrace = true; - extraVerilatorArgs = [ "${ipScope.verilator-dpi-lib-trace}/lib/libdpi_t1.a" ]; - }; - - # --------------------------------------------------------------------------------- - # VCS - # --------------------------------------------------------------------------------- - vcs-dpi-lib = ipScope.makeDifftest { - outputName = "t1-vcs-dpi-lib"; - emuType = "vcs"; - moduleType = "dpi_t1"; - }; - vcs-dpi-lib-trace = ipScope.makeDifftest { - outputName = "t1-vcs-dpi-trace-lib"; - emuType = "vcs"; - enableTrace = true; - moduleType = "dpi_t1"; - }; - - offline-checker = ipScope.makeDifftest { - outputName = "t1-offline-checker"; - moduleType = "offline_t1"; - }; - - vcs-emu = t1Scope.sv-to-vcs-simulator { - mainProgram = "t1-vcs-simulator"; - rtl = ipScope.emu-rtl; - vcsLinkLibs = [ "${ipScope.vcs-dpi-lib}/lib/libdpi_t1.a" ]; - }; - vcs-emu-trace = t1Scope.sv-to-vcs-simulator { - mainProgram = "t1-vcs-trace-simulator"; - rtl = ipScope.emu-rtl; - enableTrace = true; - vcsLinkLibs = [ "${ipScope.vcs-dpi-lib-trace}/lib/libdpi_t1.a" ]; - }; - - run = ipScope.callPackage ./run { }; - }); # end of ipScope - - subsystem = rec { - recurseForDerivations = true; - - elaborate = cfgScope.callPackage ./elaborate.nix { target = "subsystem"; /* use-binder = true; */ }; - mlirbc = cfgScope.callPackage ./mlirbc.nix { inherit elaborate; }; - rtl = cfgScope.callPackage ./rtl.nix { inherit mlirbc; }; - }; - - release = cfgScope.callPackage ./release { }; - }) # end of cfgScope + (configName: allGenerators: + let + strippedGeneratorData = lib.mapAttrs' + (fullClassName: origData: + lib.nameValuePair + (lib.head + (lib.splitString "." + (lib.removePrefix "org.chipsalliance.t1.elaborator." fullClassName))) + (origData // { inherit fullClassName; })) + allGenerators; + in + lib.mapAttrs + (topName: generator: + lib.makeScope t1Scope.newScope + (mostInnerScope: + lib.recurseIntoAttrs { + inherit configName topName; + + cases = mostInnerScope.callPackage ../../tests { }; + + mlirbc = t1Scope.chisel-to-mlirbc { + outputName = "${generator.fullClassName}.mlirbc"; + generatorClassName = generator.fullClassName; + elaboratorArgs = "config ${generator.cmdopt}"; + }; + + lowered-mlirbc = t1Scope.finalize-mlirbc { + outputName = "lowered-" + mostInnerScope.mlirbc.name; + mlirbc = mostInnerScope.mlirbc; + }; + + rtl = t1Scope.mlirbc-to-sv { + outputName = "${generator.fullClassName}-rtl"; + mlirbc = mostInnerScope.lowered-mlirbc; + mfcArgs = [ + "-O=release" + "--disable-all-randomization" + "--split-verilog" + "--preserve-values=all" + "--strip-debug-info" + "--strip-fir-debug-info" + "--verification-flavor=sva" + "--lowering-options=verifLabels,omitVersionComment,emittedLineLength=240,locationInfoStyle=none" + ]; + }; + + omGet = args: lib.toLower (lib.fileContents (runCommand "get-${args}" { } '' + ${t1Scope.omreader-unwrapped}/bin/omreader \ + ${lib.replaceStrings ["elaborator"] ["omreader"] generator.fullClassName} \ + ${args} \ + --mlirbc-file ${mostInnerScope.lowered-mlirbc}/${mostInnerScope.lowered-mlirbc.name} \ + > $out + '')); + rtlDesignMetadata = with mostInnerScope; rec { + march = omGet "march"; + extensions = builtins.fromJSON (omGet "extensionsJson"); + vlen = omGet "vlen"; + dlen = omGet "dlen"; + xlen = if (lib.hasPrefix "rv32" march) then 32 else 64; + }; + + # --------------------------------------------------------------------------------- + # VERILATOR + # --------------------------------------------------------------------------------- + makeDifftest = mostInnerScope.callPackage ../../difftest { }; + + verilator-dpi-lib = mostInnerScope.makeDifftest { + outputName = "${topName}-verilator-dpi-lib"; + emuType = "verilator"; + moduleType = "dpi_${topName}"; + }; + verilator-dpi-lib-trace = mostInnerScope.makeDifftest { + outputName = "${topName}-verilator-trace-dpi-lib"; + emuType = "verilator"; + moduleType = "dpi_${topName}"; + enableTrace = true; + }; + + verilator-emu = t1Scope.sv-to-verilator-emulator { + mainProgram = "${topName}-verilated-simulator"; + rtl = mostInnerScope.rtl; + extraVerilatorArgs = [ "${mostInnerScope.verilator-dpi-lib}/lib/libdpi_${topName}.a" ]; + }; + verilator-emu-trace = t1Scope.sv-to-verilator-emulator { + mainProgram = "${topName}-verilated-trace-simulator"; + rtl = mostInnerScope.rtl; + enableTrace = true; + extraVerilatorArgs = [ "${mostInnerScope.verilator-dpi-lib-trace}/lib/libdpi_${topName}.a" ]; + }; + + # --------------------------------------------------------------------------------- + # VCS + # --------------------------------------------------------------------------------- + vcs-dpi-lib = mostInnerScope.makeDifftest { + outputName = "${topName}-vcs-dpi-lib"; + emuType = "vcs"; + moduleType = "dpi_${topName}"; + }; + vcs-dpi-lib-trace = mostInnerScope.makeDifftest { + outputName = "${topName}-vcs-dpi-trace-lib"; + emuType = "vcs"; + enableTrace = true; + moduleType = "dpi_${topName}"; + }; + + offline-checker = mostInnerScope.makeDifftest { + outputName = "${topName}-offline-checker"; + moduleType = "offline_${topName}"; + }; + + vcs-emu = t1Scope.sv-to-vcs-simulator { + mainProgram = "${topName}-vcs-simulator"; + rtl = mostInnerScope.rtl; + vcsLinkLibs = [ "${mostInnerScope.vcs-dpi-lib}/lib/libdpi_${topName}.a" ]; + }; + vcs-emu-trace = t1Scope.sv-to-vcs-simulator { + mainProgram = "${topName}-vcs-trace-simulator"; + rtl = mostInnerScope.rtl; + enableTrace = true; + vcsLinkLibs = [ "${mostInnerScope.vcs-dpi-lib-trace}/lib/libdpi_${topName}.a" ]; + }; + + run = mostInnerScope.callPackage ./run { }; + }) + ) + strippedGeneratorData ) # end of anonymous lambda allConfigs # end of lib.mapAttrs diff --git a/nix/t1/t1rocket.nix b/nix/t1/t1rocket.nix deleted file mode 100644 index 447171288..000000000 --- a/nix/t1/t1rocket.nix +++ /dev/null @@ -1,145 +0,0 @@ -{ lib -, newScope - -, chisel-to-mlirbc -, finalize-mlirbc -, mlirbc-to-sv -, sv-to-verilator-emulator -, sv-to-vcs-simulator -}: - -{ - ip = lib.makeScope newScope (scope: { - - cases = scope.callPackage ../../tests { }; - run = scope.callPackage ./run { configName = "t1rocket"; }; - - mlirbc = chisel-to-mlirbc { - outputName = "t1rocketemu-parsed.mlirbc"; - elaboratorArgs = [ - "t1rocketemu" - "--t1rocket-config" - "${../../t1rocketemu/configs/default.json}" - ]; - }; - - lowered-mlirbc = finalize-mlirbc { - outputName = "t1rocketemu-lowered.mlirbc"; - mlirbc = scope.mlirbc; - }; - - rtl = mlirbc-to-sv { - outputName = "t1rocketemu-rtl"; - mlirbc = scope.lowered-mlirbc; - mfcArgs = [ - "-O=release" - "--split-verilog" - "--preserve-values=all" - "--verification-flavor=if-else-fatal" - "--lowering-options=verifLabels,omitVersionComment" - "--strip-debug-info" - ]; - }; - - makeDifftest = scope.callPackage ../../difftest { }; - verilator-dpi-lib = scope.makeDifftest { - outputName = "t1rocket-verilator-dpi-lib"; - moduleType = "dpi_t1rocket"; - emuType = "verilator"; - }; - verilator-dpi-lib-trace = scope.makeDifftest { - outputName = "t1rocket-verilator-trace-dpi-lib"; - moduleType = "dpi_t1rocket"; - emuType = "verilator"; - enableTrace = true; - }; - - verilator-emu = sv-to-verilator-emulator { - mainProgram = "t1rocket-verilated-simulator"; - rtl = scope.rtl; - extraVerilatorArgs = [ - "--threads-max-mtasks" - "8000" - "${scope.verilator-dpi-lib}/lib/libdpi_t1rocket.a" - ]; - }; - verilator-emu-trace = sv-to-verilator-emulator { - mainProgram = "t1rocket-verilated-trace-simulator"; - rtl = scope.rtl; - enableTrace = true; - extraVerilatorArgs = [ - "--threads-max-mtasks" - "8000" - "${scope.verilator-dpi-lib}/lib/libdpi_t1rocket.a" - ]; - }; - - vcs-dpi-lib = scope.makeDifftest { - outputName = "t1rocket-vcs-dpi-lib"; - moduleType = "dpi_t1rocket"; - emuType = "vcs"; - }; - vcs-dpi-lib-trace = scope.makeDifftest { - outputName = "t1rocket-vcs-dpi-trace-lib"; - moduleType = "dpi_t1rocket"; - emuType = "vcs"; - enableTrace = true; - }; - - offline-checker = scope.makeDifftest { - outputName = "t1rocket-offline-checker"; - moduleType = "offline_t1rocket"; - }; - - vcs-emu = sv-to-vcs-simulator { - mainProgram = "t1rocket-vcs-simulator"; - rtl = scope.rtl; - vcsLinkLibs = [ "${scope.vcs-dpi-lib}/lib/libdpi_t1rocket.a" ]; - }; - vcs-emu-trace = sv-to-vcs-simulator { - mainProgram = "t1rocket-vcs-trace-simulator"; - rtl = scope.rtl; - enableTrace = true; - vcsLinkLibs = [ "${scope.vcs-dpi-lib-trace}/lib/libdpi_t1rocket.a" ]; - }; - - getVLen = ext: - let - val = builtins.tryEval - (lib.toInt - (lib.removeSuffix "b" - (lib.removePrefix "zvl" - (lib.toLower ext)))); - in - if val.success then - val.value - else - throw "Invalid vlen extension `${ext}` specify, expect Zvl{N}b"; - - # TODO: designConfig should be read from OM - designConfig = with builtins; (fromJSON (readFile ../../t1rocketemu/configs/default.json)).parameter; - - # TODO: We should have a type define, to keep t1 and t1rocket feeds same `rtlDesignMetadata` data structure. - rtlDesignMetadata = rec { - # TODO: `march` and `dlen` should be read from OM - # - # Although the string is already hard-coded in lower case, the toLower function call here is to remind developer that, - # when we switch OM, we should always ensure the march input is lower case. - march = lib.toLower "rv32gc_zve32f_zvl1024b"; - extensions = lib.splitString "_" march; - dlen = scope.designConfig.dLen; - xlen = if (lib.hasPrefix "rv32" march) then 32 else 64; - - # Find "Zvl{N}b" string in march and parse it to vlen. - # Extract earlier so that downstream derivation that relies on this value doesn't have to parse the string multiple times. - vlen = lib.pipe (march) [ - (lib.splitString "_") - (lib.filter (x: lib.hasPrefix "zvl" x)) - (lib.last) - (lib.removePrefix "zvl") - (lib.removeSuffix "b") - (lib.toInt) - ]; - }; - }); -} diff --git a/omreader/src/Main.scala b/omreader/src/Main.scala deleted file mode 100644 index b7a967260..000000000 --- a/omreader/src/Main.scala +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileCopyrightText: 2022 Jiuyang Liu - -package org.chipsalliance.t1.omreader - -import java.io.BufferedInputStream -import mainargs._ -import chisel3.panamaom._ -import org.chipsalliance.t1.omreaderlib._ - -object Main { - implicit object PathRead extends TokensReader.Simple[os.Path] { - def shortName = "path" - def read(strs: Seq[String]): Either[String, os.Path] = Right(os.Path(strs.head, os.pwd)) - } - - @main - def run( - @arg(name = "mlirbc-file") mlirbcFile: Option[os.Path], - @arg(name = "dump-methods") dumpMethods: Flag, - @arg(name = "eval") eval: Option[String] - ) = { - val t1Reader = (mlirbcFile match { - case Some(path) => OMReader.fromFile(path) - case None => - val stdin = new BufferedInputStream(System.in) - val bytes = Stream.continually(stdin.read).takeWhile(_ != -1).map(_.toByte).toArray - OMReader.fromBytes(bytes) - }).t1Reader - - if (eval.nonEmpty) { - println(SimpleInputEval(t1Reader.entry, eval.get)) - } else if (dumpMethods.value) { - t1Reader.dumpMethods() - } else { - t1Reader.dumpAll() - } - } - - @main - def vlen(@arg(name = "mlirbc-file") mlirbcFile: os.Path) = { - println(simplyGetT1Reader(mlirbcFile).vlen) - } - - @main - def dlen(@arg(name = "mlirbc-file") mlirbcFile: os.Path) = { - println(simplyGetT1Reader(mlirbcFile).dlen) - } - - @main - def march(@arg(name = "mlirbc-file") mlirbcFile: os.Path) = { - println(simplyGetT1Reader(mlirbcFile).march) - } - - @main - def extensionsJson(@arg(name = "mlirbc-file") mlirbcFile: os.Path) = { - println(simplyGetT1Reader(mlirbcFile).extensionsJson) - } - - @main - def decoderInstructionsJson(@arg(name = "mlirbc-file") mlirbcFile: os.Path) = { - println(simplyGetT1Reader(mlirbcFile).decoderInstructionsJson) - } - - @main - def decoderInstructionsJsonPretty(@arg(name = "mlirbc-file") mlirbcFile: os.Path) = { - println(simplyGetT1Reader(mlirbcFile).decoderInstructionsJsonPretty) - } - - def simplyGetT1Reader(mlirbcFile: os.Path) = OMReader.fromFile(mlirbcFile).t1Reader - - def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) -} - -object SimpleInputEval { - def apply(entry: PanamaCIRCTOMEvaluatorValue, input: String): PanamaCIRCTOMEvaluatorValue = { - input.split("\\.").foldLeft(entry) { case (obj, field) => - if (field.forall(_.isDigit)) { - obj.asInstanceOf[PanamaCIRCTOMEvaluatorValueList].getElement(field.toLong) - } else { - obj.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject].field(field) - } - } - } -} diff --git a/omreader/src/t1/T1.scala b/omreader/src/t1/T1.scala new file mode 100644 index 000000000..f949e4019 --- /dev/null +++ b/omreader/src/t1/T1.scala @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.omreader.t1 + +import mainargs._ +import org.chipsalliance.t1.omreaderlib.t1.T1 + +object T1 { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]): Either[String, os.Path] = Right(os.Path(strs.head, os.pwd)) + } + @main + def vlen(@arg(name = "mlirbc-file") mlirbcFile: os.Path) = + println(new T1(os.read.bytes(mlirbcFile)).vlen) + + @main + def dlen(@arg(name = "mlirbc-file") mlirbcFile: os.Path) = + println(new T1(os.read.bytes(mlirbcFile)).dlen) + + @main + def instructions(@arg(name = "mlirbc-file") mlirbcFile: os.Path) = + new T1(os.read.bytes(mlirbcFile)).instructions.foreach(println) + + @main + def extensions( + @arg(name = "mlirbc-file") mlirbcFile: os.Path + ) = + println(new T1(os.read.bytes(mlirbcFile)).extensions.mkString("")) + + @main + def march(@arg(name = "mlirbc-file") mlirbcFile: os.Path) = + println(new T1(os.read.bytes(mlirbcFile)).march) + + @main + def sram(@arg(name = "mlirbc-file") mlirbcFile: os.Path) = + new T1(os.read.bytes(mlirbcFile)).sram.foreach(s => println(upickle.default.write(s))) + + @main + def retime(@arg(name = "mlirbc-file") mlirbcFile: os.Path) = + new T1(os.read.bytes(mlirbcFile)).retime.foreach(r => println(upickle.default.write(r))) + + def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) +} diff --git a/omreader/src/t1rocketv/T1RocketTile.scala b/omreader/src/t1rocketv/T1RocketTile.scala new file mode 100644 index 000000000..bd67122c3 --- /dev/null +++ b/omreader/src/t1rocketv/T1RocketTile.scala @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.omreader.t1rocketv + +import mainargs._ +import org.chipsalliance.t1.omreaderlib.t1rocketv.T1RocketTile + +object T1RocketTile { + implicit object PathRead extends TokensReader.Simple[os.Path] { + def shortName = "path" + def read(strs: Seq[String]): Either[String, os.Path] = Right(os.Path(strs.head, os.pwd)) + } + @main + def vlen(@arg(name = "mlirbc-file") mlirbcFile: os.Path) = + println(new T1RocketTile(os.read.bytes(mlirbcFile)).vlen) + + @main + def dlen(@arg(name = "mlirbc-file") mlirbcFile: os.Path) = + println(new T1RocketTile(os.read.bytes(mlirbcFile)).dlen) + + @main + def instructions(@arg(name = "mlirbc-file") mlirbcFile: os.Path) = + new T1RocketTile(os.read.bytes(mlirbcFile)).instructions.foreach(println) + + @main + def extensions( + @arg(name = "mlirbc-file") mlirbcFile: os.Path + ) = + println(new T1RocketTile(os.read.bytes(mlirbcFile)).extensions.mkString("")) + + @main + def march(@arg(name = "mlirbc-file") mlirbcFile: os.Path) = + println(new T1RocketTile(os.read.bytes(mlirbcFile)).march) + + @main + def sram(@arg(name = "mlirbc-file") mlirbcFile: os.Path) = + new T1RocketTile(os.read.bytes(mlirbcFile)).sram.foreach(s => println(upickle.default.write(s))) + + @main + def retime(@arg(name = "mlirbc-file") mlirbcFile: os.Path) = + new T1RocketTile(os.read.bytes(mlirbcFile)).retime.foreach(r => println(upickle.default.write(r))) + + def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args) +} diff --git a/omreaderlib/src/Interface.scala b/omreaderlib/src/Interface.scala deleted file mode 100644 index a882aa952..000000000 --- a/omreaderlib/src/Interface.scala +++ /dev/null @@ -1,102 +0,0 @@ -package org.chipsalliance.t1.omreaderlib - -import scala.reflect.runtime.universe._ -import chisel3.panamalib.option._ -import chisel3.panamaom._ -import chisel3.panamaconverter.PanamaCIRCTConverter - -object OMReader { - def fromFile(mlirbcFile: os.Path): OMReader = { - new OMReader(os.read.bytes(mlirbcFile)) - } - - def fromBytes(mlirbc: Array[Byte]): OMReader = { - new OMReader(mlirbc) - } -} - -class OMReader private (mlirbc: Array[Byte]) { - private val cvt = PanamaCIRCTConverter.newWithMlirBc(mlirbc) - private val om = cvt.om() - private val evaluator = om.evaluator() - - def t1Reader: T1Reader = new T1Reader(evaluator, om.newBasePathEmpty) -} - -class T1Reader private[omreaderlib] (evaluator: PanamaCIRCTOMEvaluator, basePath: PanamaCIRCTOMEvaluatorValueBasePath) { - val (entry, isSubsystem) = { - evaluator.instantiate("T1Subsystem_Class", Seq(basePath)) match { - case Some(subsystem) => (subsystem, true) - case None => (evaluator.instantiate("T1_Class", Seq(basePath)).get, false) - } - } - private val t1 = { - if (isSubsystem) { - entry - .field("om") - .asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] - .field("t1") - .asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] - } else { - entry - .field("om") - .asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] - } - } - - def vlen: Long = t1.field("vlen").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer - def dlen: Long = t1.field("dlen").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer - private def decoderInstructionsJsonImpl: ujson.Value = { - val decoder = t1.field("decoder").asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] - val instructions = decoder.field("instructions").asInstanceOf[PanamaCIRCTOMEvaluatorValueList] - - instructions.elements.map(instruction => { - val instr = instruction.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] - val attributes = instr.field("attributes").asInstanceOf[PanamaCIRCTOMEvaluatorValueList] - - ujson.Obj( - "attributes" -> attributes.elements.map(attribute => { - val attr = attribute.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] - val description = attr.field("description").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString - val identifier = attr.field("identifier").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString - val value = attr.field("value").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString - ujson.Obj( - "description" -> description, - "identifier" -> identifier, - "value" -> value - ) - }) - ) - }) - } - def decoderInstructionsJson: String = ujson.write(decoderInstructionsJsonImpl) - def decoderInstructionsJsonPretty: String = ujson.write(decoderInstructionsJsonImpl, 2) - def extensionsJson: String = { - val extensions = t1.field("extensions").asInstanceOf[PanamaCIRCTOMEvaluatorValueList] - val j = extensions.elements.map(_.asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString) - ujson.write(j) - } - def march: String = t1.field("march").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString - - def dumpMethods(): Unit = { - val mirror = runtimeMirror(getClass.getClassLoader).reflect(this) - val methods = - typeOf[T1Reader].decls.toList.filter(m => m.isPublic && m.isMethod && !m.isConstructor && !m.asMethod.isGetter) - methods.foreach(method => { - if (!method.name.toString.startsWith("dump")) { - var value = mirror.reflectMethod(method.asMethod)().toString.replace("\n", "\\n") - - val displayLength = 80 - if (value.length > displayLength) { - value = value.take(displayLength) + s" (... ${value.length - displayLength} characters)" - } - - println(s"${method.name} = $value") - } - }) - } - - def dumpAll(): Unit = { - entry.foreachField((name, value) => println(s".$name => $value")) - } -} diff --git a/omreaderlib/src/OMReader.scala b/omreaderlib/src/OMReader.scala new file mode 100644 index 000000000..49783c69a --- /dev/null +++ b/omreaderlib/src/OMReader.scala @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.omreaderlib + +import chisel3.panamaconverter.PanamaCIRCTConverter +import chisel3.panamaom._ + +trait OMReader { + val mlirbc: Array[Byte] + val top: String + protected lazy val cvt: PanamaCIRCTConverter = PanamaCIRCTConverter.newWithMlirBc(mlirbc) + protected lazy val om: PanamaCIRCTOM = cvt.om() + protected lazy val evaluator: PanamaCIRCTOMEvaluator = om.evaluator() + protected lazy val basePath: PanamaCIRCTOMEvaluatorValueBasePath = om.newBasePathEmpty() + protected lazy val entry: PanamaCIRCTOMEvaluatorValueObject = evaluator.instantiate(top, Seq(basePath)).get +} diff --git a/omreaderlib/src/T1OMReaderAPI.scala b/omreaderlib/src/T1OMReaderAPI.scala new file mode 100644 index 000000000..0fc21210f --- /dev/null +++ b/omreaderlib/src/T1OMReaderAPI.scala @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.omreaderlib + +import upickle.default.{macroRW, ReadWriter} + +object SRAM { + implicit val rw: ReadWriter[SRAM] = macroRW +} + +/** The SRAM Module to be replaced. */ +case class SRAM( + moduleName: String, + depth: Int, + width: Int, + read: Int, + write: Int, + readwrite: Int, + maskGranularity: Int) + +object Retime { + implicit val rw: ReadWriter[Retime] = macroRW +} + +/** Module to be retimed. */ +case class Retime(moduleName: String) + +object InstructionAttributes { + implicit val rw: ReadWriter[InstructionAttributes] = macroRW +} + +case class InstructionAttributes( + identifier: String, + description: String, + value: String) + +object Instruction { + implicit val rw: ReadWriter[Instruction] = macroRW +} + +case class Instruction( + instructionName: String, + documentation: String, + bitPat: String, + attributes: Seq[InstructionAttributes]) { + override def toString: String = + s"${instructionName} -> ${attributes.map(a => s"${a.identifier}:${a.value}").mkString(",")}" +} + +object Path { + implicit val rw: ReadWriter[Instruction] = macroRW + def parse(str: String): Path = + str match { + case s"OMReferenceTarget:~${top}|${hier}>${local}" => + Path( + top, + hier + .split("/") + .map(i => { + val s = i.split(":") + (s.head, s.last) + }), + Some(local) + ) + case s"OMReferenceTarget:~${top}|${hier}" => + Path( + top, + hier + .split("/") + .map(i => { + val s = i.split(":") + (s.head, s.last) + }), + None + ) + } +} + +case class Path(top: String, hierarchy: Seq[(String, String)], local: Option[String]) { + def module: String = hierarchy.last._2 + def path: String = hierarchy.map(_._1).mkString(".") +} + +/** Public Module under T1 should implement Modules below. */ +trait T1OMReaderAPI extends OMReader { + + def vlen: Int + + def dlen: Int + + /** all supported RISC-V extensions */ + def extensions: Seq[String] + + /** the march needed by compiler */ + def march: String + + /** All SRAMs with its metadata */ + def sram: Seq[SRAM] + + /** All Modules that need to be retimed */ + def retime: Seq[Retime] + + /** All Instructions with all metadata */ + def instructions: Seq[Instruction] +} diff --git a/omreaderlib/src/t1/T1.scala b/omreaderlib/src/t1/T1.scala new file mode 100644 index 000000000..a2418f76d --- /dev/null +++ b/omreaderlib/src/t1/T1.scala @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.omreaderlib.t1 + +import chisel3.panamaom._ +import org.chipsalliance.t1.omreaderlib.{Instruction, InstructionAttributes, Path, Retime, SRAM, T1OMReaderAPI} + +/** OM API for [[org.chipsalliance.t1.rtl.T1OM]] */ +class T1(val mlirbc: Array[Byte]) extends T1OMReaderAPI { + val top: String = "T1_Class" + private val t1: PanamaCIRCTOMEvaluatorValueObject = entry.field("om").asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] + def vlen: Int = t1.field("vlen").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt + def dlen: Int = t1.field("dlen").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt + def instructions: Seq[Instruction] = { + val decoder = t1.field("decoder").asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] + val instructions = decoder.field("instructions").asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + instructions + .elements() + .map(instruction => { + val instr = instruction.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] + val attributes = instr.field("attributes").asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + instr.field("attributes").asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + Instruction( + instr.field("instructionName").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString, + instr.field("documentation").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString, + instr.field("bitPat").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString, + attributes + .elements() + .map(_.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject]) + .map { attr => + InstructionAttributes( + attr.field("identifier").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString, + attr.field("description").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString, + attr.field("value").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString + ) + } + ) + }) + } + def extensions: Seq[String] = { + val extensions = t1.field("extensions").asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + extensions.elements().map(_.asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString) + } + def march: String = t1.field("march").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString + def sram: Seq[SRAM] = t1 + .field("lanes") + .asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + .elements() + .map(_.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject].field("vrf")) + .flatMap { vrf => + val srams = vrf + .asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] + .field("srams") + .asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + srams.elements().map(_.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject]).map { sram => + SRAM( + moduleName = + Path.parse(sram.field("hierarchy").asInstanceOf[PanamaCIRCTOMEvaluatorValuePath].toString).module, + depth = sram.field("depth").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt, + width = sram.field("width").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt, + read = sram.field("read").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt, + write = sram.field("write").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt, + readwrite = sram.field("readwrite").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt, + maskGranularity = sram + .field("maskGranularity") + .asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger] + .integer + .toInt + ) + } + } + .distinct + def retime: Seq[Retime] = { + t1 + .field("lanes") + .asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + .elements() + .map(_.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject].field("vfus")) + .flatMap( + _.asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + .elements() + .map(_.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject]) + .filter(_.field("cycles").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer != 0) + ) + .map(_.field("clock").asInstanceOf[PanamaCIRCTOMEvaluatorValuePath]) + .map(p => Retime(Path.parse(p.toString).module)) + .distinct + } +} diff --git a/omreaderlib/src/t1emu/Testbench.scala b/omreaderlib/src/t1emu/Testbench.scala new file mode 100644 index 000000000..fea02134c --- /dev/null +++ b/omreaderlib/src/t1emu/Testbench.scala @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu +package org.chipsalliance.t1.omreaderlib.t1rocketv + +import chisel3.panamaom._ +import org.chipsalliance.t1.omreaderlib.{Instruction, InstructionAttributes, Retime, SRAM, T1OMReaderAPI} + +/** OM API for [[org.chipsalliance.t1.rtl.T1OM]] */ +class Testbench(val mlirbc: Array[Byte]) extends T1OMReaderAPI { + val top: String = "Testbench_Class" + private val t1: PanamaCIRCTOMEvaluatorValueObject = entry + .field("om") + .asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] + .field("t1") + .asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] + def vlen: Int = t1.field("vlen").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt + def dlen: Int = t1.field("dlen").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt + def extensions: Seq[String] = { + val extensions = t1.field("extensions").asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + extensions.elements().map(_.asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString) + } + def march: String = t1.field("march").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString + def instructions: Seq[Instruction] = { + val decoder = t1.field("decoder").asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] + val instructions = decoder.field("instructions").asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + instructions + .elements() + .map(instruction => { + val instr = instruction.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] + val attributes = instr.field("attributes").asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + instr.field("attributes").asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + Instruction( + instr.field("instructionName").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString, + instr.field("documentation").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString, + instr.field("bitPat").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString, + attributes + .elements() + .map(_.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject]) + .map { attr => + InstructionAttributes( + attr.field("identifier").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString, + attr.field("description").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString, + attr.field("value").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString + ) + } + ) + }) + } + override def sram: Seq[SRAM] = Nil + override def retime: Seq[Retime] = Nil +} diff --git a/omreaderlib/src/t1rocketv/T1RocketTile.scala b/omreaderlib/src/t1rocketv/T1RocketTile.scala new file mode 100644 index 000000000..5688e191c --- /dev/null +++ b/omreaderlib/src/t1rocketv/T1RocketTile.scala @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.omreaderlib.t1rocketv + +import chisel3.panamaom._ +import org.chipsalliance.t1.omreaderlib.{Instruction, InstructionAttributes, Path, Retime, SRAM, T1OMReaderAPI} + +/** OM API for [[org.chipsalliance.t1.rtl.T1OM]] */ +class T1RocketTile(val mlirbc: Array[Byte]) extends T1OMReaderAPI { + val top: String = "T1RocketTile_Class" + private val tile: PanamaCIRCTOMEvaluatorValueObject = entry + .field("om") + .asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] + private val t1: PanamaCIRCTOMEvaluatorValueObject = tile + .field("t1") + .asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] + def vlen: Int = t1.field("vlen").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt + def dlen: Int = t1.field("dlen").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt + def instructions: Seq[Instruction] = { + val decoder = t1.field("decoder").asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] + val instructions = decoder.field("instructions").asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + instructions + .elements() + .map(instruction => { + val instr = instruction.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] + val attributes = instr.field("attributes").asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + instr.field("attributes").asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + Instruction( + instr.field("instructionName").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString, + instr.field("documentation").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString, + instr.field("bitPat").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString, + attributes + .elements() + .map(_.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject]) + .map { attr => + InstructionAttributes( + attr.field("identifier").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString, + attr.field("description").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString, + attr.field("value").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString + ) + } + ) + }) + } + def extensions: Seq[String] = { + val extensions = t1.field("extensions").asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + extensions.elements().map(_.asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString) + } + def march: String = t1.field("march").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveString].toString + def vrf: Seq[SRAM] = t1 + .field("lanes") + .asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + .elements() + .map(_.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject].field("vrf")) + .flatMap { vrf => + val srams = vrf + .asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] + .field("srams") + .asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + srams.elements().map(_.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject]).map { sram => + SRAM( + moduleName = + Path.parse(sram.field("hierarchy").asInstanceOf[PanamaCIRCTOMEvaluatorValuePath].toString).module, + depth = sram.field("depth").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt, + width = sram.field("width").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt, + read = sram.field("read").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt, + write = sram.field("write").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt, + readwrite = sram.field("readwrite").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt, + maskGranularity = sram + .field("maskGranularity") + .asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger] + .integer + .toInt + ) + } + } + .distinct + + def cache: Seq[SRAM] = Seq( + tile + .field("frontend") + .asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] + .field("icache") + .asInstanceOf[PanamaCIRCTOMEvaluatorValueObject], + tile + .field("hellaCache") + .asInstanceOf[PanamaCIRCTOMEvaluatorValueObject] + ) + .flatMap( + _.field("srams") + .asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + .elements() + .map(_.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject]) + .map(sram => + SRAM( + moduleName = + Path.parse(sram.field("hierarchy").asInstanceOf[PanamaCIRCTOMEvaluatorValuePath].toString).module, + depth = sram.field("depth").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt, + width = sram.field("width").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt, + read = sram.field("read").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt, + write = sram.field("write").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt, + readwrite = sram.field("readwrite").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt, + maskGranularity = sram + .field("maskGranularity") + .asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger] + .integer + .toInt + ) + ) + ) + .distinct + + def sram = vrf ++ cache + def vfu: Seq[Retime] = { + t1 + .field("lanes") + .asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + .elements() + .map(_.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject].field("vfus")) + .flatMap( + _.asInstanceOf[PanamaCIRCTOMEvaluatorValueList] + .elements() + .map(_.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject]) + .filter(_.field("cycles").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer != 0) + ) + .map(_.field("clock").asInstanceOf[PanamaCIRCTOMEvaluatorValuePath]) + .map(p => Retime(Path.parse(p.toString).module)) + .distinct + } + def retime = vfu +} diff --git a/rocketv/src/Frontend.scala b/rocketv/src/Frontend.scala index 4aa78514c..2aad99178 100644 --- a/rocketv/src/Frontend.scala +++ b/rocketv/src/Frontend.scala @@ -5,8 +5,9 @@ package org.chipsalliance.rocketv import chisel3._ -import chisel3.experimental.hierarchy.{instantiable, Instantiate} +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import chisel3.experimental.{SerializableModule, SerializableModuleParameter} +import chisel3.properties.{AnyClassType, Class, ClassType, Property} import chisel3.util._ import chisel3.util.circt.ClockGate import chisel3.util.experimental.BitSet @@ -229,8 +230,17 @@ class FrontendInterface(parameter: FrontendParameter) extends Bundle { org.chipsalliance.amba.axi4.bundle.AXI4ROIrrevocable(parameter.instructionFetchParameter) val itimAXI: Option[AXI4RWIrrevocable] = parameter.itimParameter.map(p => Flipped(org.chipsalliance.amba.axi4.bundle.AXI4RWIrrevocable(p))) + val om: Property[ClassType] = Output(Property[AnyClassType]()) } +@instantiable +class FrontendOM extends Class { + @public + val icache = IO(Output(Property[AnyClassType]())) + @public + val icacheIn = IO(Input(Property[AnyClassType]())) + icache := icacheIn +} @instantiable class Frontend(val parameter: FrontendParameter) extends FixedIORawModule(new FrontendInterface(parameter)) @@ -238,8 +248,10 @@ class Frontend(val parameter: FrontendParameter) with Public with ImplicitClock with ImplicitReset { - override protected def implicitClock: Clock = io.clock - override protected def implicitReset: Reset = io.reset + override protected def implicitClock: Clock = io.clock + override protected def implicitReset: Reset = io.reset + val omInstance: Instance[FrontendOM] = Instantiate(new FrontendOM) + io.om := omInstance.getPropertyReference.asAnyClassType def xLen = parameter.xLen def fetchWidth = parameter.fetchWidth @@ -292,6 +304,8 @@ class Frontend(val parameter: FrontendParameter) else ClockGate(clock, clock_en) val icache = Instantiate(new ICache(parameter.icacheParameter)) + omInstance.icacheIn := Property(icache.io.om.asAnyClassType) + icache.io.clock := gated_clock icache.io.reset := io.reset icache.io.clock_enabled := clock_en diff --git a/rocketv/src/HellaCache.scala b/rocketv/src/HellaCache.scala index e1c6a70a3..619affd25 100644 --- a/rocketv/src/HellaCache.scala +++ b/rocketv/src/HellaCache.scala @@ -5,8 +5,9 @@ package org.chipsalliance.rocketv import chisel3._ -import chisel3.experimental.hierarchy.{instantiable, Instance, Instantiate} +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import chisel3.experimental.{SerializableModule, SerializableModuleParameter, SourceInfo} +import chisel3.properties.{AnyClassType, Class, ClassType, Property} import chisel3.util.experimental.{BitSet, InlineInstance} import chisel3.util.{ isPow2, @@ -333,6 +334,16 @@ class HellaCacheInterface(parameter: HellaCacheParameter) extends Bundle { org.chipsalliance.amba.axi4.bundle.AXI4RWIrrevocable(parameter.loadStoreParameter) val dtimAXI: Option[AXI4RWIrrevocable] = parameter.dtimParameter.map(p => Flipped(org.chipsalliance.amba.axi4.bundle.AXI4RWIrrevocable(p))) + val om: Property[ClassType] = Output(Property[AnyClassType]()) +} + +@instantiable +class HellaCacheOM extends Class { + val srams = IO(Output(Property[Seq[AnyClassType]]())) + + @public + val sramsIn = IO(Input(Property[Seq[AnyClassType]]())) + srams := sramsIn } @instantiable @@ -350,6 +361,8 @@ class HellaCache(val parameter: HellaCacheParameter) val amoalus: Option[Seq[Instance[AMOALU]]] = parameter.amoaluParameter.map(amoaluParameter => Seq.tabulate(parameter.coreDataBits / parameter.xLen)(i => Instantiate(new AMOALU(amoaluParameter))) ) + val omInstance: Instance[HellaCacheOM] = Instantiate(new HellaCacheOM) + io.om := omInstance.getPropertyReference.asAnyClassType tlb.io.clock := io.clock tlb.io.reset := io.reset @@ -515,6 +528,7 @@ class HellaCache(val parameter: HellaCacheParameter) numReadwritePorts = 1 ) } + omInstance.sramsIn := Property((dataArrays ++ Some(tag_array)).map(_.description.get.asAnyClassType)) /** Data Arbiter 0: data from pending store buffer 1: data from TL-D refill 2: release to TL-A 3: hit path to CPU */ diff --git a/rocketv/src/ICache.scala b/rocketv/src/ICache.scala index 3238f8f78..0e3f7f2b6 100644 --- a/rocketv/src/ICache.scala +++ b/rocketv/src/ICache.scala @@ -5,8 +5,9 @@ package org.chipsalliance.rocketv import chisel3._ -import chisel3.experimental.hierarchy.instantiable +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import chisel3.experimental.{SerializableModule, SerializableModuleParameter} +import chisel3.properties.{AnyClassType, Class, ClassType, Property} import chisel3.util.random.LFSR import chisel3.util._ import org.chipsalliance.amba.axi4.bundle.{AXI4BundleParameter, AXI4ROIrrevocable, AXI4RWIrrevocable} @@ -130,8 +131,18 @@ class ICacheInterface(parameter: ICacheParameter) extends Bundle { val itimAXI: Option[AXI4RWIrrevocable] = parameter.itimAXIParameter.map(p => Flipped(org.chipsalliance.amba.axi4.bundle.AXI4RWIrrevocable(p))) + + val om: Property[ClassType] = Output(Property[AnyClassType]()) } +@instantiable +class ICacheOM extends Class { + val srams = IO(Output(Property[Seq[AnyClassType]]())) + + @public + val sramsIn = IO(Input(Property[Seq[AnyClassType]]())) + srams := sramsIn +} @instantiable class ICache(val parameter: ICacheParameter) extends FixedIORawModule(new ICacheInterface(parameter)) @@ -139,8 +150,10 @@ class ICache(val parameter: ICacheParameter) with Public with ImplicitClock with ImplicitReset { - override protected def implicitClock: Clock = io.clock - override protected def implicitReset: Reset = io.reset + override protected def implicitClock: Clock = io.clock + override protected def implicitReset: Reset = io.reset + val omInstance: Instance[ICacheOM] = Instantiate(new ICacheOM) + io.om := omInstance.getPropertyReference.asAnyClassType // compatiblity mode object Split { @@ -523,6 +536,7 @@ class ICache(val parameter: ICacheParameter) numReadwritePorts = 1 ) } + omInstance.sramsIn := Property((data_arrays ++ Some(tag_array)).map(_.description.get.asAnyClassType)) for ((data_array, i) <- data_arrays.zipWithIndex) { diff --git a/rocketv/src/RocketCore.scala b/rocketv/src/RocketCore.scala index 52ac45afe..d7d739929 100644 --- a/rocketv/src/RocketCore.scala +++ b/rocketv/src/RocketCore.scala @@ -24,6 +24,7 @@ import chisel3.util.{ RegEnable, Valid } +import chisel3.properties.{AnyClassType, Class, ClassType, Property} import org.chipsalliance.rocketv.rvdecoderdbcompat.Causes import org.chipsalliance.rvdecoderdb.Instruction @@ -372,8 +373,12 @@ class RocketInterface(parameter: RocketParameter) extends Bundle { val wfi = Output(Bool()) val traceStall = Input(Bool()) val rocketProbe = Output(Probe(new RocketProbe(parameter), layers.Verification)) + val om: Property[ClassType] = Output(Property[AnyClassType]()) } +@instantiable +class RocketOM extends Class {} + /** The [[Rocket]] is the next version of the RocketCore, All micro architectures are from the original RocketCore. The * development of [[Rocket]] happens in the T1 project. It will be moved to the standalone pacakge until it get * verified. @@ -404,6 +409,8 @@ class Rocket(val parameter: RocketParameter) val mul: Option[Instance[PipelinedMultiplier]] = parameter.mulParameter.map(p => Instantiate(new PipelinedMultiplier(p))) val t1RetireQueue: Option[Queue[T1RdRetire]] = io.t1.map(t1 => Module(new Queue(chiselTypeOf(t1.retire.rd.bits), 32))) + val omInstance: Instance[RocketOM] = Instantiate(new RocketOM) + io.om := omInstance.getPropertyReference.asAnyClassType // compatibility mode. object rocketParams { diff --git a/script/ci/src/Main.scala b/script/ci/src/Main.scala index 37244550a..cf512d166 100644 --- a/script/ci/src/Main.scala +++ b/script/ci/src/Main.scala @@ -125,11 +125,12 @@ object Main: @main def generateCiMatrix( runnersAmount: Int, - caseDir: String = "cases", - testPlanFile: String = "default.json" + caseDir: String = "designs", + top: String ) = { val testPlans = - os.walk(os.pwd / ".github" / caseDir).filter(_.last == testPlanFile) + os.walk(os.pwd / ".github" / caseDir) + .filter(_.last == s"${top}.json") println(toMatrixJson(scheduleTasks(testPlans, runnersAmount))) } @@ -144,8 +145,9 @@ object Main: // @param: dontBail don't throw exception when test fail. Useful for postpr. @main def runTests( - jobs: String, - testType: String = "verilator" + jobs: String, + top: String, + emuLib: String ): Unit = if jobs == "" then Logger.info("No test found, exiting") @@ -160,17 +162,17 @@ object Main: s"${BOLD}[${index + 1}/${allJobs.length}]${RESET} Simulating test case $caseName with config $config" ) - val testAttr = testType.toLowerCase() match + val testAttr = emuLib.toLowerCase() match case "verilator" => - s".#t1.$config.ip.run.$caseName.verilator-emu" - case "vcs" => s".#t1.$config.ip.run.$caseName.vcs-emu" - case _ => Logger.fatal(s"Invalid test type ${testType}") + s".#t1.$config.$top.run.$caseName.verilator-emu" + case "vcs" => s".#t1.$config.$top.run.$caseName.vcs-emu" + case _ => Logger.fatal(s"Invalid test type ${emuLib}") val testResultPath = try os.Path( nixResolvePath( testAttr, - if testType == "vcs" then Seq("--impure") else Seq() + if emuLib == "vcs" then Seq("--impure") else Seq() ) ) catch @@ -178,7 +180,7 @@ object Main: Logger.error( s"Online driver for config $config, case $caseName fail, please check manually on local machine" ) - Logger.error(s"nix build $testAttr" ++ (if testType == "vcs" then " --impure" else "")) + Logger.error(s"nix build $testAttr" ++ (if emuLib == "vcs" then " --impure" else "")) Logger.fatal("Online Drive run fail, exiting CI") Logger.info("Checking RTL event from event log") @@ -219,13 +221,17 @@ object Main: doc = "specify the urg report markdown file output path" ) urgReportFilePath: Option[String], @arg( - name = "emu-type", - doc = "Specify emulation type" - ) emuType: String = "verilator", + name = "emu-lib", + doc = "Specify emulator library type, verilator or vcs" + ) emuLib: String = "vcs", @arg( - name = "case-dir", - doc = "Specify case directory" - ) caseDir: String = "cases" + name = "top", + doc = "Specify emulator ip top, Eg. t1rocketemu/t1emu..." + ) top: String, + @arg( + name = "top", + doc = "Specify emulator ip top, Eg. t1rocketemu/t1emu..." + ) top: String ) = val failedTestsFile = os.Path(failedTestsFilePath, os.pwd) os.write.over(failedTestsFile, "## Failed Tests\n") @@ -237,8 +243,8 @@ object Main: if urgReportFilePath.nonEmpty then os.write(os.Path(urgReportFilePath.get, os.pwd), "# Coverage report\n") - os.walk(os.pwd / ".github" / caseDir) - .filter(_.last == "default.json") + os.walk(os.pwd / ".github" / "designs") + .filter(_.last == s"${top}.json") .foreach: file => val config = file.segments.toSeq.reverse.apply(1) var cycleRecord = ujson.read(os.read(file)) @@ -246,8 +252,8 @@ object Main: Logger.info("Fetching CI results") val emuResultPath = os.Path( nixResolvePath( - s".#t1.$config.ip.run._${emuType}EmuResult", - if emuType.toLowerCase() == "vcs" then Seq("--impure") + s".#t1.$config.${top}.run._${emuLib}EmuResult", + if emuLib.toLowerCase() == "vcs" then Seq("--impure") else Seq() ) ) @@ -260,7 +266,7 @@ object Main: val caseName = path.segments.toSeq.reverse.drop(1).head os.write.append( failedTestsFile, - s"* ${config} - ${caseName}: `nix build .#t1.$config.ip.$caseName.$emuType-emu -L --impure`\n" + s"* ${config} - ${caseName}: `nix build .#t1.$config.${top}.$caseName.$emuLib-emu -L --impure`\n" ) }) @@ -308,17 +314,11 @@ object Main: end postCI @main - def generateTestPlan(testType: String = "") = - val casePath = testType match - case "t1rocket" => os.pwd / ".github" / "t1rocket-cases" - case _ => os.pwd / ".github" / "cases" - - val allCases = os.walk(casePath).filter(_.last == "default.json") - val testPlans = allCases.map: caseFilePath => - caseFilePath.segments - .dropWhile(!Seq("cases", "t1rocket-cases").contains(_)) - .drop(1) - .next + def generateTestPlan(top: String) = + val testPlans = os + .walk(os.pwd / ".github" / "designs") + .filter(_.last == s"${top}.json") + .map(path => path.segments.toSeq.reverse.drop(1).head) println(ujson.write(Map("config" -> testPlans))) end generateTestPlan @@ -345,8 +345,6 @@ object Main: .filter: path => path.last == "default.json" .map: path => - // We have a list of pwd/.github/cases//default.json string, - // but all we need is the name. path.segments.toSeq.reverse.drop(1).head import scala.util.chaining._ diff --git a/script/default.nix b/script/default.nix index e92e82aea..dbd294d4c 100644 --- a/script/default.nix +++ b/script/default.nix @@ -51,6 +51,8 @@ let ''; }); + passthru.debug = self.overrideAttrs { enableNativeExe = false; }; + nativeBuildInputs = [ mill graalvm-ce @@ -59,16 +61,24 @@ let passthru.millDeps.setupHook ]; + enableNativeExe = true; + buildPhase = '' runHook preBuild - echo "Checking format" - mill -i ${moduleName}.checkFormat + # Not debug build, check source format + if (( $enableNativeExe )); then + echo "Checking format" + mill -i ${moduleName}.checkFormat + fi echo "Building JAR" mill -i ${moduleName}.assembly - echo "Running native-image" - native-image --no-fallback -jar out/${moduleName}/assembly.dest/out.jar "$name.elf" + + if (( $enableNativeExe )); then + echo "Running native-image" + native-image --no-fallback -jar out/${moduleName}/assembly.dest/out.jar "$name.elf" + fi runHook postBuild ''; @@ -77,7 +87,15 @@ let runHook preInstall mkdir -p "$out"/bin - cp "$name.elf" "$out"/bin/"${outName}" + + if (( $enableNativeExe )); then + cp "$name.elf" "$out"/bin/"${outName}" + else + mkdir -p $out/share/java + mv out/${moduleName}/assembly.dest/out.jar $out/share/java/${moduleName}.jar + makeWrapper ${mill.jre}/bin/java $out/bin/${outName} \ + --add-flags "-jar $out/share/java/${moduleName}.jar" + fi runHook postInstall ''; diff --git a/script/emu/src/Main.scala b/script/emu/src/Main.scala index f8bb9e66b..93597f487 100644 --- a/script/emu/src/Main.scala +++ b/script/emu/src/Main.scala @@ -46,6 +46,7 @@ object Main: os.proc(args).call().out.trim() def resolveTestElfPath( + ip: String, config: String, caseName: String, forceX86: Boolean = false @@ -58,7 +59,7 @@ object Main: else ".#" val nixStorePath = resolveNixPath( - s"${caseAttrRoot}t1.${config}.ip.cases.${caseName}" + s"${caseAttrRoot}t1.${config}.${ip}.cases.${caseName}" ) val elfFilePath = os.Path(nixStorePath) / "bin" / s"${caseName}.elf" @@ -66,6 +67,7 @@ object Main: end resolveTestElfPath def resolveTestBenchPath( + ip: String, config: String, emuType: String ): os.Path = @@ -73,8 +75,8 @@ object Main: if (os.exists(emuPath)) then return emuPath val nixStorePath = - if emuType.contains("vcs-") then resolveNixPath(s".#t1.${config}.ip.${emuType}", Seq("--impure")) - else resolveNixPath(s".#t1.${config}.ip.${emuType}") + if emuType.contains("vcs-") then resolveNixPath(s".#t1.${config}.${ip}.${emuType}", Seq("--impure")) + else resolveNixPath(s".#t1.${config}.${ip}.${emuType}") val elfFilePath = os .walk(os.Path(nixStorePath) / "bin") @@ -142,6 +144,11 @@ object Main: if (cond) then input else null @main def run( + @arg( + name = "ip", + short = 'i', + doc = "IP type for emulator, Eg. t1emu, t1rocketemu" + ) ip: Option[String], @arg( name = "emu", short = 'e', @@ -178,6 +185,12 @@ object Main: val caseName = leftOver.value.head if !isValidCaseName(caseName) then Logger.fatal(s"invalid caseName '$caseName', expect 'A.B'") + val finalIp = tryRestoreFromCache("ip", ip) + if finalIp.isEmpty then + Logger.fatal( + s"No cached IP selection nor --ip argument was provided" + ) + val finalEmuType = tryRestoreFromCache("emulator", emuType) if finalEmuType.isEmpty then Logger.fatal( @@ -198,9 +211,9 @@ object Main: ) val caseElfPath = - resolveTestElfPath(finalConfig.get, caseName, forceX86) + resolveTestElfPath(finalIp.get, finalConfig.get, caseName, forceX86) val outputPath = prepareOutputDir(outDir.getOrElse("t1-sim-result")) - val emulator = resolveTestBenchPath(finalConfig.get, finalEmuType.get) + val emulator = resolveTestBenchPath(finalIp.get, finalConfig.get, finalEmuType.get) val leftOverArguments = leftOver.value.dropWhile(arg => arg != "--") @@ -226,7 +239,8 @@ object Main: ujson.Obj( "config" -> finalConfig.get, "elf" -> caseElfPath.toString, - "event" -> rtlEventPath.toString + "event" -> rtlEventPath.toString, + "ip" -> finalIp.get ) ) ) @@ -281,6 +295,11 @@ object Main: @main def check( + @arg( + name = "ip", + short = 'i', + doc = "IP type for emulator, Eg. t1emu, t1rocketemu" + ) ip: Option[String], @arg( name = "config", short = 'c', @@ -316,6 +335,14 @@ object Main: if os.exists(resultPath) then ujson.read(os.read(resultPath / "driver-state.json")) else ujson.Obj() + val finalIp = + if ip.isDefined then ip.get + else + lastState.obj + .get("ip") + .getOrElse(Logger.fatal("No driver-state.json nor --ip")) + .str + val finalConfig = if config.isDefined then config.get else @@ -325,11 +352,11 @@ object Main: .str val offlineChecker = os.Path( - resolveNixPath(s".#t1.${finalConfig}.ip.offline-checker") + resolveNixPath(s".#t1.${finalConfig}.${finalIp}.offline-checker") ) / "bin" / "offline" val elfFile = - if caseAttr.isDefined then resolveTestElfPath(finalConfig, caseAttr.get).toString + if caseAttr.isDefined then resolveTestElfPath(finalIp, finalConfig, caseAttr.get).toString else lastState.obj .get("elf") @@ -362,6 +389,11 @@ object Main: @main def listCases( + @arg( + name = "ip", + short = 'i', + doc = "specify the IP, such as t1emu, t1rocketemu" + ) ip: String, @arg( name = "config", short = 'c', @@ -378,7 +410,7 @@ object Main: "nix", "--no-warn-dirty", "eval", - s".#t1.${config}.ip.cases", + s".#t1.${config}.${ip}.cases", "--apply", """cases: with builtins; | (map diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala index e8b74ad00..51929c4ec 100644 --- a/t1/src/Lane.scala +++ b/t1/src/Lane.scala @@ -27,6 +27,11 @@ class LaneOM extends Class { @public val vfusIn = IO(Input(Property[Seq[AnyClassType]]())) vfus := vfusIn + @public + val vrf = IO(Output(Property[AnyClassType]())) + @public + val vrfIn = IO(Input(Property[AnyClassType]())) + vrf := vrfIn } class LaneSlotProbe(instructionIndexBits: Int) extends Bundle { @@ -321,6 +326,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ /** VRF instantces. */ val vrf: Instance[VRF] = Instantiate(new VRF(parameter.vrfParam)) + omInstance.vrfIn := Property(vrf.om.asAnyClassType) /** TODO: review later */ diff --git a/t1/src/T1.scala b/t1/src/T1.scala index a7ab45e5b..8113097ae 100644 --- a/t1/src/T1.scala +++ b/t1/src/T1.scala @@ -4,20 +4,36 @@ package org.chipsalliance.t1.rtl import chisel3._ -import chisel3.experimental.hierarchy.{instantiable, public, Definition, Instance, Instantiate} +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import chisel3.probe.{define, Probe, ProbeValue} import chisel3.properties.{AnyClassType, Class, ClassType, Property} -import chisel3.util.{Decoupled, _} import chisel3.util.experimental.BitSet +import chisel3.util.experimental.decode.DecodeBundle +import chisel3.util.{ + log2Ceil, + scanLeftOr, + scanRightOr, + Decoupled, + DecoupledIO, + Enum, + Fill, + FillInterleaved, + Mux1H, + OHToUInt, + Pipe, + RegEnable, + UIntToOH, + Valid, + ValidIO +} +import org.chipsalliance.amba.axi4.bundle.{AXI4BundleParameter, AXI4RWIrrevocable} import org.chipsalliance.rvdecoderdb.Instruction import org.chipsalliance.t1.rtl.decoder.{Decoder, DecoderParam, T1CustomInstruction} -import chisel3.util.experimental.decode._ -import org.chipsalliance.amba.axi4.bundle.{AXI4BundleParameter, AXI4RWIrrevocable} import org.chipsalliance.t1.rtl.lsu.{LSU, LSUParameter, LSUProbe} -import org.chipsalliance.t1.rtl.vrf.{RamType, VRFParam, VRFProbe} +import org.chipsalliance.t1.rtl.vrf.{RamType, VRFParam} -import scala.collection.immutable.{ListMap, SeqMap} +import scala.collection.immutable.SeqMap // TODO: this should be a object model. There should 3 object model here: // 1. T1SubsystemOM(T1(OM), MemoryRegion, Cache configuration) @@ -99,10 +115,8 @@ object T1Parameter { * lane size. TODO: sort a machine-readable chaining matrix for test case generation. */ case class T1Parameter( - vLen: Int, dLen: Int, extensions: Seq[String], - t1customInstructions: Seq[T1CustomInstruction], // Lane vrfBankSize: Int, vrfRamType: RamType, @@ -111,17 +125,22 @@ case class T1Parameter( extends SerializableModuleParameter { // TODO: expose it with the Property API override def toString: String = - s"""T1-VLEN$vLen-DLEN$dLen-${extensions.mkString(",")}(${dLen / 32} lanes) - |Lane: - | VRF: - | Banks: ${vrfBankSize} - | RAMType: ${vrfRamType match { + s"""T1-${extensions.mkString(",")} + |${dLen / 32} Lanes + |VRF Banks: ${vrfBankSize} + |VRFRAMType: ${vrfRamType match { case RamType.p0rw => "Single Port." case RamType.p0rp1w => "First Port Read, Second Port Write." case RamType.p0rwp1rw => "Dual Ports Read Write." }} |""".stripMargin + def t1customInstructions: Seq[T1CustomInstruction] = Nil + + def vLen: Int = extensions.collectFirst { case s"zvl${vlen}b" => + vlen.toInt + }.get + val allInstructions: Seq[Instruction] = { org.chipsalliance.rvdecoderdb .instructions(org.chipsalliance.rvdecoderdb.extractResource(getClass.getClassLoader)) @@ -133,14 +152,20 @@ case class T1Parameter( } } ++ t1customInstructions.map(_.instruction) - }.toSeq.sortBy(_.instructionSet.name).filter { insn => + }.toSeq.filter { insn => insn.name match { case s if Seq("vsetivli", "vsetvli", "vsetvl").contains(s) => false case _ => true } - } - - require(extensions.forall(Seq("Zve32x", "Zve32f", "Zvbb").contains), "unsupported extension.") + }.sortBy(_.instructionSet.name) + + require( + extensions.forall( + (Seq("zve32x", "zve32f", "zvbb") ++ + Seq(128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536).map(vlen => s"zvl${vlen}b")).contains + ), + "unsupported extension." + ) // TODO: require bank not overlap /** xLen of T1, we currently only support 32. */ val xLen: Int = 32 @@ -155,10 +180,10 @@ case class T1Parameter( val vrfWriteQueueSize: Int = 4 /** does t1 has floating datapath? */ - val fpuEnable: Boolean = extensions.contains("Zve32f") + val fpuEnable: Boolean = extensions.contains("zve32f") /** support of zvbb */ - lazy val zvbbEnable: Boolean = extensions.contains("Zvbb") + lazy val zvbbEnable: Boolean = extensions.contains("zvbb") /** how many chaining does T1 support, this is not a parameter yet. */ val chainingSize: Int = 4 @@ -361,7 +386,7 @@ class T1(val parameter: T1Parameter) omInstance.vlenIn := Property(parameter.vLen) omInstance.dlenIn := Property(parameter.dLen) omInstance.extensionsIn := Property(parameter.extensions) - omInstance.marchIn := Property(s"rv32gc_${parameter.extensions.mkString("_").toLowerCase}_zvl${parameter.vLen}b") + omInstance.marchIn := Property(s"rv32gc_${parameter.extensions.mkString("_").toLowerCase}") /** the LSU Module */ diff --git a/t1/src/VectorFunctionUnit.scala b/t1/src/VectorFunctionUnit.scala index e8fdf7a27..9450a11d2 100644 --- a/t1/src/VectorFunctionUnit.scala +++ b/t1/src/VectorFunctionUnit.scala @@ -34,6 +34,11 @@ class VFUOM extends Class { @public val cyclesIn = IO(Input(Property[Int]())) cycles := cyclesIn + @public + val clock = IO(Output(Property[Path])) + @public + val clockIn = IO(Input(Property[Path])) + clock := clockIn } @instantiable @@ -48,7 +53,9 @@ abstract class VFUModule(p: VFUParameter) extends Module { @public val responseIO: DecoupledIO[VFUPipeBundle] = IO(Decoupled(p.outputBundle)) om := omInstance.getPropertyReference - omInstance.cyclesIn := Property(p.latency) + // I don't under the parameter of VFU, dirty hack + omInstance.cyclesIn := Property(if (p.singleCycle) 1 else 0) + omInstance.clockIn := Property(Path(clock)) val vfuRequestReady: Option[Bool] = Option.when(!p.singleCycle)(Wire(Bool())) val requestReg: VFUPipeBundle = RegEnable(requestIO.bits, 0.U.asTypeOf(requestIO.bits), requestIO.fire) @@ -94,6 +101,433 @@ abstract class VFUModule(p: VFUParameter) extends Module { object VFUInstantiateParameter { implicit def rw: upickle.default.ReadWriter[VFUInstantiateParameter] = upickle.default.macroRW + + // generics templates + def parse(vLen: Int, dLen: Int, preset: String, fp: Boolean, zvbb: Boolean) = preset match { + case "minimal" => + (fp, zvbb) match { + case (false, false) => VFUInstantiateParameter.minimalInt(vLen, dLen) + case (true, false) => VFUInstantiateParameter.minimalFP(vLen, dLen) + case (false, true) => VFUInstantiateParameter.zvbb(vLen, dLen) + case (true, true) => VFUInstantiateParameter.zvbbFP(vLen, dLen) + } + case "small" => + (fp, zvbb) match { + case (false, false) => VFUInstantiateParameter.smallInt(vLen, dLen) + case (true, false) => VFUInstantiateParameter.smallFP(vLen, dLen) + case (false, true) => VFUInstantiateParameter.zvbb(vLen, dLen) + case (true, true) => VFUInstantiateParameter.zvbbFP(vLen, dLen) + } + case "medium" => + (fp, zvbb) match { + case (false, false) => VFUInstantiateParameter.smallInt(vLen, dLen) + case (true, false) => VFUInstantiateParameter.mediumFP(vLen, dLen) + case (false, true) => VFUInstantiateParameter.zvbb(vLen, dLen) + case (true, true) => VFUInstantiateParameter.zvbbFP(vLen, dLen) + } + case "large" => + (fp, zvbb) match { + case (false, false) => VFUInstantiateParameter.smallInt(vLen, dLen) + case (true, false) => VFUInstantiateParameter.largeFP(vLen, dLen) + case (false, true) => VFUInstantiateParameter.zvbb(vLen, dLen) + case (true, true) => VFUInstantiateParameter.zvbbFP(vLen, dLen) + } + } + + // instantiate each module and connect to all scoreboards + def minimalFP(vLen: Int, dLen: Int) = VFUInstantiateParameter( + slotCount = 4, + logicModuleParameters = Seq( + (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(0, 1, 2, 3)) + ), + aluModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(0, 1, 2, 3)) + ), + shifterModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(0, 1, 2, 3)) + ), + mulModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneMul], LaneMulParam(32, 2)), Seq(0, 1, 2, 3)) + ), + divModuleParameters = Seq(), + divfpModuleParameters = + Seq((SerializableModuleGenerator(classOf[LaneDivFP], LaneDivFPParam(32, 1)), Seq(0, 1, 2, 3))), + otherModuleParameters = Seq( + ( + SerializableModuleGenerator( + classOf[OtherUnit], + OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) + ), + Seq(0, 1, 2, 3) + ) + ), + floatModuleParameters = + Seq((SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(0, 1, 2, 3))), + zvbbModuleParameters = Seq() + ) + + // standalone ALU for all scoreboards + def smallFP(vLen: Int, dLen: Int) = VFUInstantiateParameter( + slotCount = 4, + logicModuleParameters = Seq( + (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(0, 1, 2, 3)) + ), + aluModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(0)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(1)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(2)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(3)) + ), + shifterModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(0, 1, 2, 3)) + ), + mulModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneMul], LaneMulParam(32, 2)), Seq(0, 1, 2, 3)) + ), + divModuleParameters = Seq(), + divfpModuleParameters = + Seq((SerializableModuleGenerator(classOf[LaneDivFP], LaneDivFPParam(32, 1)), Seq(0, 1, 2, 3))), + otherModuleParameters = Seq( + ( + SerializableModuleGenerator( + classOf[OtherUnit], + OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) + ), + Seq(0, 1, 2, 3) + ) + ), + floatModuleParameters = + Seq((SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(0, 1, 2, 3))), + zvbbModuleParameters = Seq() + ) + + // standalone VFU(except MUL and DIV) for all scoreboards + def mediumFP(vLen: Int, dLen: Int) = VFUInstantiateParameter( + slotCount = 4, + logicModuleParameters = Seq( + (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(0)), + (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(1)), + (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(2)), + (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(3)) + ), + aluModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(0)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(1)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(2)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(3)) + ), + shifterModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(0)), + (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(1)), + (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(2)), + (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(3)) + ), + mulModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneMul], LaneMulParam(32, 2)), Seq(0, 1, 2, 3)) + ), + divModuleParameters = Seq(), + divfpModuleParameters = + Seq((SerializableModuleGenerator(classOf[LaneDivFP], LaneDivFPParam(32, 1)), Seq(0, 1, 2, 3))), + otherModuleParameters = Seq( + ( + SerializableModuleGenerator( + classOf[OtherUnit], + OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) + ), + Seq(0) + ), + ( + SerializableModuleGenerator( + classOf[OtherUnit], + OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) + ), + Seq(1) + ), + ( + SerializableModuleGenerator( + classOf[OtherUnit], + OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) + ), + Seq(2) + ), + ( + SerializableModuleGenerator( + classOf[OtherUnit], + OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) + ), + Seq(3) + ) + ), + floatModuleParameters = + Seq((SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(0, 1, 2, 3))), + zvbbModuleParameters = Seq() + ) + + // standalone VFU(except DIV) for all scoreboards + def largeFP(vLen: Int, dLen: Int) = VFUInstantiateParameter( + slotCount = 4, + logicModuleParameters = Seq( + (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(0)), + (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(1)), + (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(2)), + (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(3)) + ), + aluModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(0)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(1)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(2)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(3)) + ), + shifterModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(0)), + (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(1)), + (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(2)), + (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(3)) + ), + mulModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneMul], LaneMulParam(32, 2)), Seq(0, 1, 2, 3)) + ), + divModuleParameters = Seq(), + divfpModuleParameters = + Seq((SerializableModuleGenerator(classOf[LaneDivFP], LaneDivFPParam(32, 1)), Seq(0, 1, 2, 3))), + otherModuleParameters = Seq( + ( + SerializableModuleGenerator( + classOf[OtherUnit], + OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) + ), + Seq(0) + ), + ( + SerializableModuleGenerator( + classOf[OtherUnit], + OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) + ), + Seq(1) + ), + ( + SerializableModuleGenerator( + classOf[OtherUnit], + OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) + ), + Seq(2) + ), + ( + SerializableModuleGenerator( + classOf[OtherUnit], + OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) + ), + Seq(3) + ) + ), + floatModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(0)), + (SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(1)), + (SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(2)), + (SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(3)) + ), + zvbbModuleParameters = Seq() + ) + + // standalone VFU for all scoreboards + def hugeFP(vLen: Int, dLen: Int) = VFUInstantiateParameter( + slotCount = 4, + logicModuleParameters = Seq( + (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(0)), + (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(1)), + (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(2)), + (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(3)) + ), + aluModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(0)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(1)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(2)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(3)) + ), + shifterModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(0)), + (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(1)), + (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(2)), + (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(3)) + ), + mulModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneMul], LaneMulParam(32, 2)), Seq(0, 1, 2, 3)) + ), + divModuleParameters = Seq(), + divfpModuleParameters = + Seq((SerializableModuleGenerator(classOf[LaneDivFP], LaneDivFPParam(32, 1)), Seq(0, 1, 2, 3))), + otherModuleParameters = Seq( + ( + SerializableModuleGenerator( + classOf[OtherUnit], + OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) + ), + Seq(0) + ), + ( + SerializableModuleGenerator( + classOf[OtherUnit], + OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) + ), + Seq(1) + ), + ( + SerializableModuleGenerator( + classOf[OtherUnit], + OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) + ), + Seq(2) + ), + ( + SerializableModuleGenerator( + classOf[OtherUnit], + OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) + ), + Seq(3) + ) + ), + floatModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(0)), + (SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(1)), + (SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(2)), + (SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(3)) + ), + zvbbModuleParameters = Seq() + ) + + def minimalInt(vLen: Int, dLen: Int) = VFUInstantiateParameter( + slotCount = 4, + logicModuleParameters = Seq( + (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(0, 1, 2, 3)) + ), + aluModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(0, 1, 2, 3)) + ), + shifterModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(0, 1, 2, 3)) + ), + mulModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneMul], LaneMulParam(32, 2)), Seq(0, 1, 2, 3)) + ), + divModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneDiv], LaneDivParam(32, 1)), Seq(0, 1, 2, 3)) + ), + divfpModuleParameters = Seq(), + otherModuleParameters = Seq( + ( + SerializableModuleGenerator( + classOf[OtherUnit], + OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) + ), + Seq(0, 1, 2, 3) + ) + ), + floatModuleParameters = Seq(), + zvbbModuleParameters = Seq() // TODO + ) + + def smallInt(vLen: Int, dLen: Int) = VFUInstantiateParameter( + slotCount = 4, + logicModuleParameters = Seq( + (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(0, 1, 2, 3)) + ), + aluModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(0)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(1)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(2)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(3)) + ), + shifterModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(0, 1, 2, 3)) + ), + mulModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneMul], LaneMulParam(32, 2)), Seq(0, 1, 2, 3)) + ), + divModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneDiv], LaneDivParam(32, 1)), Seq(0, 1, 2, 3)) + ), + divfpModuleParameters = Seq(), + otherModuleParameters = Seq( + ( + SerializableModuleGenerator( + classOf[OtherUnit], + OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) + ), + Seq(0, 1, 2, 3) + ) + ), + floatModuleParameters = Seq(), + zvbbModuleParameters = Seq() // TODO + ) + + // experimental + def zvbb(vLen: Int, dLen: Int) = VFUInstantiateParameter( + slotCount = 4, + logicModuleParameters = Seq( + (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(0, 1, 2, 3)) + ), + aluModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(0)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(1)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(2)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(3)) + ), + shifterModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(0, 1, 2, 3)) + ), + mulModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneMul], LaneMulParam(32, 2)), Seq(0, 1, 2, 3)) + ), + divModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneDiv], LaneDivParam(32, 1)), Seq(0, 1, 2, 3)) + ), + divfpModuleParameters = Seq(), + otherModuleParameters = Seq( + ( + SerializableModuleGenerator( + classOf[OtherUnit], + OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) + ), + Seq(0, 1, 2, 3) + ) + ), + floatModuleParameters = Seq(), + zvbbModuleParameters = Seq((SerializableModuleGenerator(classOf[LaneZvbb], LaneZvbbParam(32, 3)), Seq(0, 1, 2, 3))) + ) + + def zvbbFP(vLen: Int, dLen: Int) = VFUInstantiateParameter( + slotCount = 4, + logicModuleParameters = Seq( + (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(0, 1, 2, 3)) + ), + aluModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(0)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(1)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(2)), + (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(3)) + ), + shifterModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(0, 1, 2, 3)) + ), + mulModuleParameters = Seq( + (SerializableModuleGenerator(classOf[LaneMul], LaneMulParam(32, 2)), Seq(0, 1, 2, 3)) + ), + divModuleParameters = Seq(), + divfpModuleParameters = + Seq((SerializableModuleGenerator(classOf[LaneDivFP], LaneDivFPParam(32, 1)), Seq(0, 1, 2, 3))), + otherModuleParameters = Seq( + ( + SerializableModuleGenerator( + classOf[OtherUnit], + OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) + ), + Seq(0, 1, 2, 3) + ) + ), + floatModuleParameters = + Seq((SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(0, 1, 2, 3))), + zvbbModuleParameters = Seq((SerializableModuleGenerator(classOf[LaneZvbb], LaneZvbbParam(32, 3)), Seq(0, 1, 2, 3))) + ) } case class VFUInstantiateParameter( diff --git a/t1/src/vrf/VRF.scala b/t1/src/vrf/VRF.scala index 3a4c0441b..eaccfee70 100644 --- a/t1/src/vrf/VRF.scala +++ b/t1/src/vrf/VRF.scala @@ -4,12 +4,14 @@ package org.chipsalliance.t1.rtl.vrf import chisel3._ +import chisel3.experimental.hierarchy.Instance import chisel3.experimental.hierarchy.{instantiable, public, Instantiate} import chisel3.experimental.{SerializableModule, SerializableModuleParameter} import chisel3.probe.{define, Probe, ProbeValue} import chisel3.util._ import chisel3.ltl._ import chisel3.ltl.Sequence._ +import chisel3.properties.{AnyClassType, Class, ClassType, Path, Property} import org.chipsalliance.t1.rtl.{ ffo, instIndexL, @@ -117,6 +119,15 @@ case class VRFParam( val vrfReadLatency = 2 } +@instantiable +class VRFOM extends Class { + val srams = IO(Output(Property[Seq[AnyClassType]]())) + + @public + val sramsIn = IO(Input(Property[Seq[AnyClassType]]())) + srams := sramsIn +} + class VRFProbe(parameter: VRFParam) extends Bundle { val valid: Bool = Bool() val requestVd: UInt = UInt(parameter.regNumBits.W) @@ -236,6 +247,12 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar @public val vrfProbe = IO(Output(Probe(new VRFProbe(parameter), layers.Verification))) + val omInstance: Instance[VRFOM] = Instantiate(new VRFOM) + val omType: ClassType = omInstance.toDefinition.getClassType + @public + val om: Property[ClassType] = IO(Output(Property[AnyClassType]())) + om := omInstance.getPropertyReference.asAnyClassType + // reset sram val sramReady: Bool = RegInit(false.B) val sramResetCount: UInt = RegInit(0.U(log2Ceil(parameter.rfDepth).W)) @@ -479,6 +496,8 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar rf } + omInstance.sramsIn := Property(rfVec.map(_.description.get.asAnyClassType)) + val initRecord: ValidIO[VRFWriteReport] = WireDefault(0.U.asTypeOf(Valid(new VRFWriteReport(parameter)))) initRecord.valid := true.B initRecord.bits := instructionWriteReport.bits diff --git a/t1emu/src/TestBench.scala b/t1emu/src/TestBench.scala index 1896f6f8c..32ec3fa25 100644 --- a/t1emu/src/TestBench.scala +++ b/t1emu/src/TestBench.scala @@ -6,7 +6,8 @@ package org.chipsalliance.t1.t1emu import chisel3._ import chisel3.experimental.dataview.DataViewable import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} -import chisel3.experimental.{ExtModule, SerializableModuleGenerator} +import chisel3.experimental.{ExtModule, SerializableModule, SerializableModuleGenerator} +import chisel3.ltl.{CoverProperty, Sequence} import chisel3.properties.{AnyClassType, Class, ClassType, Property} import chisel3.util.circt.dpi.{ RawClockedNonVoidFunctionCall, @@ -14,11 +15,10 @@ import chisel3.util.circt.dpi.{ RawUnclockedNonVoidFunctionCall } import chisel3.util.{BitPat, HasExtModuleInline, PopCount, UIntToOH, Valid} -import chisel3.ltl.{CoverProperty, Sequence} import org.chipsalliance.amba.axi4.bundle._ -import org.chipsalliance.t1.t1emu.dpi._ -import org.chipsalliance.t1.rtl.{T1, T1Parameter} import org.chipsalliance.rvdecoderdb.Instruction +import org.chipsalliance.t1.rtl.{T1, T1Parameter} +import org.chipsalliance.t1.t1emu.dpi._ @instantiable class TestBenchOM extends Class { @@ -29,8 +29,9 @@ class TestBenchOM extends Class { t1 := t1In } -class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) +class TestBench(val parameter: T1Parameter) extends RawModule + with SerializableModule[T1Parameter] with ImplicitClock with ImplicitReset { layer.enable(layers.Verification) @@ -83,7 +84,7 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) def reset = clockGen.reset override def implicitClock = clockGen.clock.asClock override def implicitReset = clockGen.reset - val dut: Instance[T1] = generator.instance() + val dut: Instance[T1] = SerializableModuleGenerator(classOf[T1], parameter).instance() val simulationTime: UInt = RegInit(0.U(64.W)) simulationTime := simulationTime + 1.U @@ -249,7 +250,7 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) when(lsuProbe.reqEnq.orR)(printf(cf"""{"event":"LsuEnq","enq":${lsuProbe.reqEnq},"cycle":${simulationTime}}\n""")) // allocate 2 * chainingSize scoreboards - val vrfWriteScoreboard: Seq[Valid[UInt]] = Seq.tabulate(2 * generator.parameter.chainingSize) { _ => + val vrfWriteScoreboard: Seq[Valid[UInt]] = Seq.tabulate(2 * parameter.chainingSize) { _ => RegInit(0.U.asTypeOf(Valid(UInt(16.W)))) } vrfWriteScoreboard.foreach(scoreboard => dontTouch(scoreboard)) @@ -257,7 +258,7 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) (laneProbes.map(laneProbe => laneProbe.instructionValid ## laneProbe.instructionValid) :+ lsuProbe.lsuInstructionValid :+ t1Probe.instructionValid).reduce(_ | _) val scoreboardEnq = - Mux(t1Probe.instructionIssue, UIntToOH(t1Probe.issueTag), 0.U((2 * generator.parameter.chainingSize).W)) + Mux(t1Probe.instructionIssue, UIntToOH(t1Probe.issueTag), 0.U((2 * parameter.chainingSize).W)) vrfWriteScoreboard.zipWithIndex.foreach { case (scoreboard, tag) => val writeEnq: UInt = VecInit( // vrf write from lane @@ -285,7 +286,7 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) scoreboard.bits := 0.U } } - generator.parameter.decoderParam.allInstructions.map { instruction: Instruction => + parameter.decoderParam.allInstructions.map { instruction: Instruction => val issueMatch = Sequence.BoolSequence(issue.instruction === BitPat("b" + instruction.encoding.toString)) CoverProperty(issueMatch, label = Some(s"t1_cover_issue_${instruction.name}")) } diff --git a/t1rocket/src/T1RocketTile.scala b/t1rocket/src/T1RocketTile.scala index 8901f28d4..8b2fbc520 100644 --- a/t1rocket/src/T1RocketTile.scala +++ b/t1rocket/src/T1RocketTile.scala @@ -3,11 +3,12 @@ package org.chipsalliance.t1.tile import chisel3._ -import chisel3.experimental.hierarchy.{Instance, Instantiate} -import chisel3.experimental.{SerializableModule, SerializableModuleGenerator, SerializableModuleParameter} +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import chisel3.experimental.{SerializableModule, SerializableModuleParameter} +import chisel3.probe.{define, Probe, ProbeValue} +import chisel3.properties.{AnyClassType, Class, ClassType, Property} import chisel3.util.experimental.BitSet import chisel3.util.log2Ceil -import chisel3.probe.{define, Probe, ProbeValue} import org.chipsalliance.amba.axi4.bundle.{AXI4BundleParameter, AXI4ROIrrevocable, AXI4RWIrrevocable} import org.chipsalliance.rocketv.{ BHTParameter, @@ -24,38 +25,12 @@ import org.chipsalliance.rocketv.{ PTWParameter, Rocket, RocketParameter, - RocketProbe, - RocketTileParameter + RocketProbe } import org.chipsalliance.rvdecoderdb.Instruction -import org.chipsalliance.t1.rtl.decoder.T1CustomInstruction import org.chipsalliance.t1.rtl.vrf.RamType import org.chipsalliance.t1.rtl.vrf.RamType.{p0rp1w, p0rw, p0rwp1rw} -import org.chipsalliance.t1.rtl.lsu.LSUProbe -import org.chipsalliance.t1.rtl.vrf.VRFProbe -import org.chipsalliance.t1.rtl.{ - LaneAdder, - LaneAdderParam, - LaneDiv, - LaneDivFP, - LaneDivFPParam, - LaneDivParam, - LaneFloat, - LaneFloatParam, - LaneMul, - LaneMulParam, - LaneProbe, - LaneShifter, - LaneShifterParameter, - LogicParam, - MaskedLogic, - OtherUnit, - OtherUnitParam, - T1, - T1Parameter, - T1Probe, - VFUInstantiateParameter -} +import org.chipsalliance.t1.rtl.{T1, T1Parameter, T1Probe, VFUInstantiateParameter} object T1RocketTileParameter { implicit def bitSetP: upickle.default.ReadWriter[BitSet] = upickle.default @@ -75,22 +50,23 @@ object T1RocketTileParameter { } case class T1RocketTileParameter( - instructionSets: Seq[String], - cacheBlockBytes: Int, - nPMPs: Int, - cacheable: BitSet, - sideEffects: BitSet, - dcacheNSets: Int, - dcacheNWays: Int, - dcacheRowBits: Int, - iCacheNSets: Int, - iCacheNWays: Int, - iCachePrefetch: Boolean, - dLen: Int, - vrfBankSize: Int, - vrfRamType: RamType) + instructionSets: Seq[String], + cacheBlockBytes: Int, + nPMPs: Int, + cacheable: BitSet, + sideEffects: BitSet, + dcacheNSets: Int, + dcacheNWays: Int, + dcacheRowBits: Int, + iCacheNSets: Int, + iCacheNWays: Int, + iCachePrefetch: Boolean, + dLen: Int, + vrfBankSize: Int, + vrfRamType: RamType, + vfuInstantiateParameter: VFUInstantiateParameter) extends SerializableModuleParameter { - require(instructionSets.count(Seq("Zve32x", "Zve32f").contains) == 1, "at least support one Zve32x or Zve32f") + require(instructionSets.count(Seq("zve32x", "zve32f").contains) == 1, "at least support one Zve32x or Zve32f") val useAsyncReset: Boolean = false val clockGate: Boolean = false @@ -375,82 +351,14 @@ case class T1RocketTileParameter( ) } - val vfuInstantiateParameter = - if (instructionSets.contains("Zve32f")) - VFUInstantiateParameter( - slotCount = 4, - logicModuleParameters = Seq( - (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(0, 1, 2, 3)) - ), - aluModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(0)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(1)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(2)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(3)) - ), - shifterModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(0, 1, 2, 3)) - ), - mulModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneMul], LaneMulParam(32, 2)), Seq(0, 1, 2, 3)) - ), - divModuleParameters = Seq(), - divfpModuleParameters = - Seq((SerializableModuleGenerator(classOf[LaneDivFP], LaneDivFPParam(32, 1)), Seq(0, 1, 2, 3))), - otherModuleParameters = Seq( - ( - SerializableModuleGenerator( - classOf[OtherUnit], - OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) - ), - Seq(0, 1, 2, 3) - ) - ), - floatModuleParameters = - Seq((SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(0, 1, 2, 3))), - zvbbModuleParameters = Seq() - ) - else - VFUInstantiateParameter( - slotCount = 4, - logicModuleParameters = Seq( - (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 1)), Seq(0, 1, 2, 3)) - ), - aluModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(0)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(1)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(2)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 1)), Seq(3)) - ), - shifterModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 1)), Seq(0, 1, 2, 3)) - ), - mulModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneMul], LaneMulParam(32, 2)), Seq(0, 1, 2, 3)) - ), - divModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneDiv], LaneDivParam(32, 1)), Seq(0, 1, 2, 3)) - ), - divfpModuleParameters = Seq(), - otherModuleParameters = Seq( - ( - SerializableModuleGenerator( - classOf[OtherUnit], - OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 1) - ), - Seq(0, 1, 2, 3) - ) - ), - floatModuleParameters = Seq(), - zvbbModuleParameters = Seq() - ) - def t1Parameter: T1Parameter = T1Parameter( - vLen = vLen, dLen = dLen, - extensions = instructionSets.filter(Seq("Zve32x", "Zve32f").contains), - // empty for now. - t1customInstructions = Seq(), + extensions = instructionSets.filter { + case i if i.startsWith("zve") => true + case i if i.startsWith("zvl") => true + case i if i == "zvbb" => true + case _ => false + }, vrfBankSize = vrfBankSize, vrfRamType = vrfRamType, vfuInstantiateParameter = vfuInstantiateParameter @@ -469,6 +377,30 @@ case class T1RocketTileParameter( def t1HightOutstandingParameter: AXI4BundleParameter = t1Parameter.axi4BundleParameter.copy(dataWidth = 32) } +@instantiable +class T1RocketTileOM extends Class { + @public + val rocket = IO(Output(Property[AnyClassType]())) + @public + val rocketIn = IO(Input(Property[AnyClassType]())) + @public + val frontend = IO(Output(Property[AnyClassType]())) + @public + val frontendIn = IO(Input(Property[AnyClassType]())) + @public + val hellaCache = IO(Output(Property[AnyClassType]())) + @public + val hellaCacheIn = IO(Input(Property[AnyClassType]())) + @public + val t1 = IO(Output(Property[AnyClassType]())) + @public + val t1In = IO(Input(Property[AnyClassType]())) + rocket := rocketIn + frontend := frontendIn + hellaCache := hellaCacheIn + t1 := t1In +} + class T1RocketProbe(parameter: T1RocketTileParameter) extends Bundle { val rocketProbe: RocketProbe = Output(new RocketProbe(parameter.rocketParameter)) val fpuProbe: Option[FPUProbe] = parameter.fpuParameter.map(param => Output(new FPUProbe(param))) @@ -511,8 +443,9 @@ class T1RocketTileInterface(parameter: T1RocketTileParameter) extends Bundle { val highOutstandingAXI: AXI4RWIrrevocable = org.chipsalliance.amba.axi4.bundle.AXI4RWIrrevocable(parameter.t1HightOutstandingParameter) + val om: Property[ClassType] = Output(Property[AnyClassType]()) // TODO: merge it. - val t1RocketProbe: T1RocketProbe = Output(Probe(new T1RocketProbe(parameter), layers.Verification)) + val t1RocketProbe: T1RocketProbe = Output(Probe(new T1RocketProbe(parameter), layers.Verification)) } class T1RocketTile(val parameter: T1RocketTileParameter) @@ -528,6 +461,12 @@ class T1RocketTile(val parameter: T1RocketTileParameter) val ptw: Instance[PTW] = Instantiate(new PTW(parameter.ptwParameter)) val fpu: Option[Instance[FPU]] = parameter.fpuParameter.map(fpuParameter => Instantiate(new FPU(fpuParameter))) val t1: Instance[T1] = Instantiate(new T1(parameter.t1Parameter)) + val omInstance: Instance[T1RocketTileOM] = Instantiate(new T1RocketTileOM) + io.om := omInstance.getPropertyReference.asAnyClassType + omInstance.rocketIn := Property(rocket.io.om.asAnyClassType) + omInstance.frontendIn := Property(frontend.io.om.asAnyClassType) + omInstance.hellaCacheIn := Property(hellaCache.io.om.asAnyClassType) + omInstance.t1In := Property(t1.io.om.asAnyClassType) rocket.io.clock := io.clock rocket.io.reset := io.reset diff --git a/t1rocketemu/src/TestBench.scala b/t1rocketemu/src/TestBench.scala index 5700de66f..687c6674d 100644 --- a/t1rocketemu/src/TestBench.scala +++ b/t1rocketemu/src/TestBench.scala @@ -4,16 +4,18 @@ package org.chipsalliance.t1.t1rocketemu import chisel3._ -import chisel3.experimental.{BaseModule, ExtModule, SerializableModuleGenerator} import chisel3.experimental.dataview.DataViewable +import chisel3.experimental.hierarchy.Instance +import chisel3.experimental.{ExtModule, SerializableModule, SerializableModuleGenerator} import chisel3.util.circt.dpi.{RawClockedNonVoidFunctionCall, RawUnclockedNonVoidFunctionCall} -import chisel3.util.{HasExtModuleInline, Mux1H, PopCount, Queue, UIntToOH, Valid} +import chisel3.util.{HasExtModuleInline, PopCount, UIntToOH, Valid} import org.chipsalliance.amba.axi4.bundle._ import org.chipsalliance.t1.t1rocketemu.dpi._ import org.chipsalliance.t1.tile.{T1RocketTile, T1RocketTileParameter} -class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTileParameter]) +class TestBench(val parameter: T1RocketTileParameter) extends RawModule + with SerializableModule[T1RocketTileParameter] with ImplicitClock with ImplicitReset { layer.enable(layers.Verification) @@ -65,7 +67,8 @@ class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTil def reset = clockGen.reset override def implicitClock = clockGen.clock.asClock override def implicitReset = clockGen.reset - val dut: T1RocketTile with BaseModule = Module(generator.module()) + val dut: Instance[T1RocketTile] = SerializableModuleGenerator(classOf[T1RocketTile], parameter).instance() + dut.io.clock := clock dut.io.reset := reset @@ -201,7 +204,7 @@ class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTil ) // [[option]] rocket fpu reg write - generator.parameter.fpuParameter.zip(t1RocketProbe.fpuProbe).zip(rocketProbe.fpuScoreboard).map { + parameter.fpuParameter.zip(t1RocketProbe.fpuProbe).zip(rocketProbe.fpuScoreboard).map { case ((fpuParameter, fpu), fpuScoreboard) => { val fpToIEEE = Module( new FPToIEEE( @@ -288,7 +291,7 @@ class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTil ) // t1 vrf scoreboard - val vrfWriteScoreboard: Seq[Valid[UInt]] = Seq.tabulate(2 * generator.parameter.t1Parameter.chainingSize) { _ => + val vrfWriteScoreboard: Seq[Valid[UInt]] = Seq.tabulate(2 * parameter.t1Parameter.chainingSize) { _ => RegInit(0.U.asTypeOf(Valid(UInt(16.W)))) } vrfWriteScoreboard.foreach(scoreboard => dontTouch(scoreboard)) @@ -296,7 +299,7 @@ class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTil (laneProbes.map(laneProbe => laneProbe.instructionValid ## laneProbe.instructionValid) :+ lsuProbe.lsuInstructionValid :+ t1Probe.instructionValid).reduce(_ | _) val scoreboardEnq = - Mux(t1Probe.instructionIssue, UIntToOH(t1Probe.issueTag), 0.U((2 * generator.parameter.t1Parameter.chainingSize).W)) + Mux(t1Probe.instructionIssue, UIntToOH(t1Probe.issueTag), 0.U((2 * parameter.t1Parameter.chainingSize).W)) vrfWriteScoreboard.zipWithIndex.foreach { case (scoreboard, tag) => val writeEnq: UInt = VecInit( // vrf write from lane