From 80f40380d6e970651038dbd2bd774c04c5c95873 Mon Sep 17 00:00:00 2001 From: Avimitin Date: Thu, 12 Sep 2024 19:39:04 +0800 Subject: [PATCH 1/2] [nix] add sail riscv model builder Signed-off-by: Avimitin --- nix/overlay.nix | 7 ++ nix/pkgs/sail-riscv-c-model.nix | 192 ++++++++++++++++++++++++++++++++ 2 files changed, 199 insertions(+) create mode 100644 nix/pkgs/sail-riscv-c-model.nix diff --git a/nix/overlay.nix b/nix/overlay.nix index d6c81428b..e4c8c687a 100644 --- a/nix/overlay.nix +++ b/nix/overlay.nix @@ -20,6 +20,8 @@ rec { libspike = final.callPackage ./pkgs/libspike.nix { }; libspike_interfaces = final.callPackage ../difftest/spike_interfaces { }; + sail-riscv-c-model = final.callPackage ./pkgs/sail-riscv-c-model.nix { }; + # DynamoCompiler doesn't support python 3.12+ yet buddy-mlir = final.callPackage ./pkgs/buddy-mlir.nix { python3 = final.python311; }; @@ -37,6 +39,11 @@ rec { mill = let jre = final.jdk21; in (prev.mill.override { inherit jre; }).overrideAttrs (_: { passthru = { inherit jre; }; + # Using mill without "-i/--interactive" or "--no-server" will run a mill + # build server automatically. The build server doesn't inherit or update + # environment when user invoke mill at command-line, which is hard for + # developers to debug. + # # --interactive implies --no-server postInstall = ''wrapProgram $out/bin/mill --add-flags "--interactive"''; }); diff --git a/nix/pkgs/sail-riscv-c-model.nix b/nix/pkgs/sail-riscv-c-model.nix new file mode 100644 index 000000000..d1ebe7da8 --- /dev/null +++ b/nix/pkgs/sail-riscv-c-model.nix @@ -0,0 +1,192 @@ +# https://github.com/NixOS/nixpkgs/blob/nixpkgs-unstable/pkgs/applications/virtualization/sail-riscv/default.nix + +{ lib +, stdenv +, fetchFromGitHub +, ocamlPackages +, ocaml +, zlib +, z3 +, bear + +, targetArch ? "rv32" +}: +assert lib.assertMsg (lib.elem targetArch [ "rv32" "rv64" ]) "targetArch `${targetArch}' invalid"; + +let + ocamlPackages' = ocamlPackages.overrideScope (finalScope: prevScope: { + sail = prevScope.sail.overrideAttrs rec { + version = "0.18"; + src = fetchFromGitHub { + owner = "rems-project"; + repo = "sail"; + rev = version; + hash = "sha256-QvVK7KeAvJ/RfJXXYo6xEGEk5iOmVsZbvzW28MHRFic="; + }; + + buildInputs = [ finalScope.menhirLib ]; + }; + }); +in +stdenv.mkDerivation (finalAttr: { + pname = "sail-riscv-c-model"; + version = "unstable-b90ec78"; + + src = fetchFromGitHub { + owner = "riscv"; + repo = "sail-riscv"; + rev = "b90ec7881eb0a0ecea6521e3d6cc03bf0b057e41"; + hash = "sha256-vWOKYCkFTYP3t3ZFpmiXOjTpqoX06Ubs2GTncCdj/Cg="; + }; + + nativeBuildInputs = with ocamlPackages'; [ ocamlbuild findlib ocaml z3 sail ]; + buildInputs = with ocamlPackages'; [ zlib linksem ]; + strictDeps = true; + + postPatch = '' + rm -r prover_snapshots + rm -r handwritten_support + ''; + + sailArgs = [ + "--strict-var" + "-dno_cast" + "-c_preserve" + "_set_Misa_C" + "-O" + "-Oconstant_fold" + "-memo_z3" + "-c" + "-c_no_main" + ]; + + sailSrcs = [ + "model/prelude.sail" + ] ++ (if targetArch == "rv32" then [ + "model/riscv_xlen32.sail" + ] else [ + "model/riscv_xlen64.sail" + ]) + ++ [ + "model/riscv_xlen.sail" + "model/riscv_flen_D.sail" + "model/riscv_vlen.sail" + "model/prelude_mem_metadata.sail" + "model/prelude_mem.sail" + "model/riscv_types_common.sail" + "model/riscv_types_ext.sail" + "model/riscv_types.sail" + "model/riscv_vmem_types.sail" + "model/riscv_reg_type.sail" + "model/riscv_freg_type.sail" + "model/riscv_regs.sail" + "model/riscv_pc_access.sail" + "model/riscv_sys_regs.sail" + "model/riscv_pmp_regs.sail" + "model/riscv_pmp_control.sail" + "model/riscv_ext_regs.sail" + "model/riscv_addr_checks_common.sail" + "model/riscv_addr_checks.sail" + "model/riscv_misa_ext.sail" + "model/riscv_vreg_type.sail" + "model/riscv_vext_regs.sail" + "model/riscv_csr_begin.sail" + "model/riscv_vext_control.sail" + "model/riscv_next_regs.sail" + "model/riscv_sys_exceptions.sail" + "model/riscv_sync_exception.sail" + "model/riscv_next_control.sail" + "model/riscv_softfloat_interface.sail" + "model/riscv_fdext_regs.sail" + "model/riscv_fdext_control.sail" + "model/riscv_sys_control.sail" + "model/riscv_platform.sail" + "model/riscv_mem.sail" + "model/riscv_vmem_common.sail" + "model/riscv_vmem_pte.sail" + "model/riscv_vmem_ptw.sail" + "model/riscv_vmem_tlb.sail" + "model/riscv_vmem.sail" + "model/riscv_types_kext.sail" + "model/riscv_insts_begin.sail" + "model/riscv_insts_base.sail" + "model/riscv_insts_aext.sail" + "model/riscv_insts_zca.sail" + "model/riscv_insts_mext.sail" + "model/riscv_insts_zicsr.sail" + "model/riscv_insts_next.sail" + "model/riscv_insts_hints.sail" + "model/riscv_insts_fext.sail" + "model/riscv_insts_zcf.sail" + "model/riscv_insts_dext.sail" + "model/riscv_insts_zcd.sail" + "model/riscv_insts_svinval.sail" + "model/riscv_insts_zba.sail" + "model/riscv_insts_zbb.sail" + "model/riscv_insts_zbc.sail" + "model/riscv_insts_zbs.sail" + "model/riscv_insts_zcb.sail" + "model/riscv_insts_zfh.sail" + "model/riscv_insts_zfa.sail" + "model/riscv_insts_zkn.sail" + "model/riscv_insts_zks.sail" + "model/riscv_insts_zbkb.sail" + "model/riscv_insts_zbkx.sail" + "model/riscv_insts_zicond.sail" + "model/riscv_insts_vext_utils.sail" + "model/riscv_insts_vext_fp_utils.sail" + "model/riscv_insts_vext_vset.sail" + "model/riscv_insts_vext_arith.sail" + "model/riscv_insts_vext_fp.sail" + "model/riscv_insts_vext_mem.sail" + "model/riscv_insts_vext_mask.sail" + "model/riscv_insts_vext_vm.sail" + "model/riscv_insts_vext_fp_vm.sail" + "model/riscv_insts_vext_red.sail" + "model/riscv_insts_vext_fp_red.sail" + "model/riscv_insts_zicbom.sail" + "model/riscv_insts_zicboz.sail" + "model/riscv_jalr_seq.sail" + "model/riscv_insts_end.sail" + "model/riscv_csr_end.sail" + "model/riscv_step_common.sail" + "model/riscv_step_ext.sail" + "model/riscv_decode_ext.sail" + "model/riscv_fetch.sail" + "model/riscv_step.sail" + "model/main.sail" + ]; + + buildPhase = '' + runHook preBuild + + mkdir -p build + sailPhase="sail $sailArgs $sailSrcs -o build/riscv_model_${targetArch}" + echo "$sailPhase" + eval "$sailPhase" + + runHook postBuild + ''; + + installPhase = '' + runHook preInstall + + mkdir -p $out/share/ + cp -v build/riscv_model_${targetArch}.c $out/share/ + + runHook postInstall + ''; + + passthru = { + inherit (ocamlPackages') sail; + inherit targetArch; + + dev = finalAttr.finalPackage.overrideAttrs (old: { + nativeBuildInputs = old.nativeBuildInputs ++ [ bear ]; + }); + }; + + meta = { + description = "Generated C source of the sail RISC-V (${targetArch}) model"; + }; +}) From ab28447e5e2af2246dc46548ff46dbe506247087 Mon Sep 17 00:00:00 2001 From: Avimitin Date: Tue, 8 Oct 2024 21:32:10 +0800 Subject: [PATCH 2/2] [sail-riscv] add sail-riscv Rust binder Disambiguation: * sail: the official sail language, library, API, headers that belongs to rem-project. * sail-riscv: the riscv spec definition describe using sail. Build step: 1. Use rust-bindgen to create Rust FFI to the sail header, so that we can always keep integrity of the sail library. 2. Extern declare all necessary C function define in generated model from sail and sail-riscv. 3. Define or override necessary functions from our Rust side. Current issues: * Implement our Rust emulator using above strategy inevitably create a programming model that functions will be called back and forth from both C and Rust side. This will also make the code hard to read. Hope this situation could be improved in upcomming rational documents. * Although sail support using different prefix for its model declaration when generating C sources, I am still afraid that these global machine state in sail-riscv model will cause problem in our future development. Signed-off-by: Avimitin --- nix/overlay.nix | 1 + sail-riscv/default.nix | 4 + sail-riscv/sail-riscv-sys/Cargo.lock | 286 ++++++++++++++++++ sail-riscv/sail-riscv-sys/Cargo.toml | 9 + sail-riscv/sail-riscv-sys/build.rs | 19 ++ sail-riscv/sail-riscv-sys/default.nix | 47 +++ .../sail-riscv-sys/sail_include/wrapper.h | 1 + sail-riscv/sail-riscv-sys/src/lib.rs | 96 ++++++ 8 files changed, 463 insertions(+) create mode 100644 sail-riscv/default.nix create mode 100644 sail-riscv/sail-riscv-sys/Cargo.lock create mode 100644 sail-riscv/sail-riscv-sys/Cargo.toml create mode 100644 sail-riscv/sail-riscv-sys/build.rs create mode 100644 sail-riscv/sail-riscv-sys/default.nix create mode 100644 sail-riscv/sail-riscv-sys/sail_include/wrapper.h create mode 100644 sail-riscv/sail-riscv-sys/src/lib.rs diff --git a/nix/overlay.nix b/nix/overlay.nix index e4c8c687a..c1c20e865 100644 --- a/nix/overlay.nix +++ b/nix/overlay.nix @@ -21,6 +21,7 @@ rec { libspike_interfaces = final.callPackage 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a/sail-riscv/sail-riscv-sys/Cargo.toml b/sail-riscv/sail-riscv-sys/Cargo.toml new file mode 100644 index 000000000..6221ea018 --- /dev/null +++ b/sail-riscv/sail-riscv-sys/Cargo.toml @@ -0,0 +1,9 @@ +[package] +name = "sail-riscv-sys" +version = "0.1.0" +edition = "2021" + +[dependencies] + +[build-dependencies] +bindgen = "0.70.1" diff --git a/sail-riscv/sail-riscv-sys/build.rs b/sail-riscv/sail-riscv-sys/build.rs new file mode 100644 index 000000000..abf126d08 --- /dev/null +++ b/sail-riscv/sail-riscv-sys/build.rs @@ -0,0 +1,19 @@ +use std::env; +use std::path::PathBuf; + +fn main() { + let sail_install_path = env::var("SAIL_INSTALL_PATH").expect("$SAIL_INSTALL_PATH not set"); + + let bindings = bindgen::Builder::default() + .header("sail_include/wrapper.h") + .clang_arg(format!("-I{sail_install_path}/share/sail/lib")) + .parse_callbacks(Box::new(bindgen::CargoCallbacks::new())) + .generate() + .expect("Unable to generate bindings"); + + // Write the bindings to the $OUT_DIR/bindings.rs file. + let out_path = PathBuf::from(env::var("OUT_DIR").unwrap()); + bindings + .write_to_file(out_path.join("sail_h.rs")) + .expect("Couldn't write bindings!"); +} diff --git a/sail-riscv/sail-riscv-sys/default.nix b/sail-riscv/sail-riscv-sys/default.nix new file mode 100644 index 000000000..4dcaeefc7 --- /dev/null +++ b/sail-riscv/sail-riscv-sys/default.nix @@ -0,0 +1,47 @@ +{ lib +, rustPlatform +, sail-riscv-c-model +, rustfmt +, rust-analyzer +, gmp +}: + +let + finalPkg = rustPlatform.buildRustPackage { + name = "sail-riscv-rs-emulator"; + src = with lib.fileset; toSource { + root = ./.; + fileset = unions [ + ./src + ./build.rs + ./sail_include + ./Cargo.lock + ./Cargo.toml + ]; + }; + + nativeBuildInputs = [ + rustPlatform.bindgenHook + ]; + + buildInputs = [ gmp ]; + + env = { + SAIL_INSTALL_PATH = toString sail-riscv-c-model.sail; + }; + + cargoLock = { + lockFile = ./Cargo.lock; + }; + + passthru = { + devShell = finalPkg.overrideAttrs (prev: { + nativeBuildInputs = prev.nativeBuildInputs ++ [ + rustfmt + rust-analyzer + ]; + }); + }; + }; +in +finalPkg diff --git a/sail-riscv/sail-riscv-sys/sail_include/wrapper.h b/sail-riscv/sail-riscv-sys/sail_include/wrapper.h new file mode 100644 index 000000000..b866f9e2c --- /dev/null +++ b/sail-riscv/sail-riscv-sys/sail_include/wrapper.h @@ -0,0 +1 @@ +#include diff --git a/sail-riscv/sail-riscv-sys/src/lib.rs b/sail-riscv/sail-riscv-sys/src/lib.rs new file mode 100644 index 000000000..8a23b30af --- /dev/null +++ b/sail-riscv/sail-riscv-sys/src/lib.rs @@ -0,0 +1,96 @@ +#![allow(non_upper_case_globals)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +// This disable warning of `u128` type usage. +// The `u128` type is not ABI stable, and is considered not FFI safe. +#![allow(improper_ctypes)] + +include!(concat!(env!("OUT_DIR"), "/sail_h.rs")); + +#[repr(C)] +pub(crate) struct zMisa { + zMisa_chunk_0: mach_bits, +} + +#[repr(C)] +pub(crate) struct zMcause { + zMcause_chunk_0: mach_bits, +} + +// ---------------------------------------------------------------------------- +// Defined in sail model +// ---------------------------------------------------------------------------- +extern "C" { + fn model_init(); + fn model_fini(); + + fn z_set_Misa_C(_: *mut zMisa, _: mach_bits) -> unit; + fn z_set_Misa_D(_: *mut zMisa, _: mach_bits) -> unit; + fn z_set_Misa_F(_: *mut zMisa, _: mach_bits) -> unit; +} + +// ---------------------------------------------------------------------------- +// Defined in sail-riscv model +// ---------------------------------------------------------------------------- +extern "C" { + fn zinit_model(_: unit) -> unit; + fn zstep(_: sail_int) -> bool; + fn ztick_clock(_: unit) -> unit; + fn ztick_platform(_: unit) -> unit; + + pub static mut zxlen_val: mach_bits; + pub static mut zhtif_done: bool; + pub static mut zhtif_exit_code: mach_bits; + pub static mut have_exception: bool; + + /* machine state */ + pub static mut zcur_privilege: u32; + pub static mut zPC: mach_bits; + pub static mut zx1: mach_bits; + pub static mut zx2: mach_bits; + pub static mut zx3: mach_bits; + pub static mut zx4: mach_bits; + pub static mut zx5: mach_bits; + pub static mut zx6: mach_bits; + pub static mut zx7: mach_bits; + pub static mut zx8: mach_bits; + pub static mut zx9: mach_bits; + pub static mut zx10: mach_bits; + pub static mut zx11: mach_bits; + pub static mut zx12: mach_bits; + pub static mut zx13: mach_bits; + pub static mut zx14: mach_bits; + pub static mut zx15: mach_bits; + pub static mut zx16: mach_bits; + pub static mut zx17: mach_bits; + pub static mut zx18: mach_bits; + pub static mut zx19: mach_bits; + pub static mut zx20: mach_bits; + pub static mut zx21: mach_bits; + pub static mut zx22: mach_bits; + pub static mut zx23: mach_bits; + pub static mut zx24: mach_bits; + pub static mut zx25: mach_bits; + pub static mut zx26: mach_bits; + pub static mut zx27: mach_bits; + pub static mut zx28: mach_bits; + pub static mut zx29: mach_bits; + pub static mut zx30: mach_bits; + pub static mut zx31: mach_bits; + + pub static mut zmstatus: mach_bits; + pub static mut zmepc: mach_bits; + pub static mut zmtval: mach_bits; + pub static mut zsepc: mach_bits; + pub static mut zstval: mach_bits; + + pub static mut zfloat_result: mach_bits; + pub static mut zfloat_fflags: mach_bits; + + pub static mut zmcause: zMcause; + pub static mut zscause: zMcause; + + pub static mut zminstret: mach_bits; + + pub static mut zmisa: zMisa; +}