From f5cca8ba6ad1c8fd751ee005f15a4012e4dd4358 Mon Sep 17 00:00:00 2001 From: qinjun-li Date: Sun, 4 Aug 2024 11:57:43 +0800 Subject: [PATCH] [rtl] Add a comment to doubleExecutionInRecord. --- t1/src/laneStage/LaneExecutionBridge.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/t1/src/laneStage/LaneExecutionBridge.scala b/t1/src/laneStage/LaneExecutionBridge.scala index 3a58046f3a..51811ab60f 100644 --- a/t1/src/laneStage/LaneExecutionBridge.scala +++ b/t1/src/laneStage/LaneExecutionBridge.scala @@ -105,6 +105,7 @@ class LaneExecutionBridge(parameter: LaneParameter, isLastSlot: Boolean, slotInd val doubleExecutionInRecord: Bool = executionRecord.decodeResult(Decoder.crossWrite) || executionRecord.decodeResult(Decoder.crossRead) || + // Type widenReduce instructions occupy double the data registers because they need to retain the carry bit. executionRecord.decodeResult(Decoder.widenReduce) // data in executionRecord is narrow type