From f1e1608fc80072206e9fc18390b5921051cf3c3b Mon Sep 17 00:00:00 2001
From: qinjun-li <liqinjun1994@gmail.com>
Date: Mon, 16 Dec 2024 16:09:40 +0800
Subject: [PATCH] [rtl] fix mask update in lane.

---
 t1/src/Lane.scala | 2 +-
 t1/src/T1.scala   | 7 +++----
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
index 5d5e5f08f..abecc3220 100644
--- a/t1/src/Lane.scala
+++ b/t1/src/Lane.scala
@@ -686,7 +686,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
     val maskFailure:    Bool = stage0.updateLaneState.maskExhausted && stage0.enqueue.fire
     // update mask register
     when(maskUpdateFire) {
-      record.mask.bits := DontCare
+      record.mask.bits := maskDataVec(index)
     }
     when(maskUpdateFire ^ maskFailure) {
       record.mask.valid := maskUpdateFire
diff --git a/t1/src/T1.scala b/t1/src/T1.scala
index 0d71bf6a5..4c395f147 100644
--- a/t1/src/T1.scala
+++ b/t1/src/T1.scala
@@ -964,10 +964,9 @@ class T1(val parameter: T1Parameter)
       probe.valid := write.fire && write.bits.mask.orR
       probe.bits  := write.bits.instructionIndex
     }
-    probeWire.instructionValid   := maskAnd(
-      !slots.last.state.wMaskUnitLast && !slots.last.state.idle,
-      indexToOH(slots.last.record.instructionIndex, parameter.chainingSize)
-    ).asUInt
+    probeWire.instructionValid   := slots
+      .map(s => maskAnd(!s.state.idle, indexToOH(s.record.instructionIndex, parameter.chainingSize)).asUInt)
+      .reduce(_ | _)
     probeWire.responseCounter    := responseCounter
     probeWire.laneProbes.zip(laneVec).foreach { case (p, l) => p := probe.read(l.laneProbe) }
     probeWire.lsuProbe           := probe.read(lsu.lsuProbe)