diff --git a/rocketv/src/Decoder.scala b/rocketv/src/Decoder.scala
index d82122cf5..fd2dfa213 100644
--- a/rocketv/src/Decoder.scala
+++ b/rocketv/src/Decoder.scala
@@ -165,14 +165,15 @@ case class DecoderParameter(
   object fp extends BoolDecodeField[RocketDecodePattern] {
     override def name: String = "fp"
 
-    override def genTable(op: RocketDecodePattern): BitPat = op.instruction.instructionSet.name match {
+    override def genTable(op: RocketDecodePattern): BitPat = (op.instruction.instructionSet.name, op) match {
       // format: off
-      case s if Seq(
+      case (s, _) if Seq(
         "rv_d", "rv64_d",
         "rv_f", "rv64_f",
         "rv_q", "rv64_q",
         "rv_zfh", "rv64_zfh", "rv_d_zfh", "rv_q_zfh",
       ).contains(s) => y
+      case (_, p) if p.vectorReadFRegFile => y
       case _ => n
       // format: on
     }
diff --git a/rocketv/src/RocketCore.scala b/rocketv/src/RocketCore.scala
index 67e95ea1f..9a8fa3b56 100644
--- a/rocketv/src/RocketCore.scala
+++ b/rocketv/src/RocketCore.scala
@@ -1409,13 +1409,7 @@ class Rocket(val parameter: RocketParameter)
         csr.io.csrStall || csr.io.singleStep && (exRegValid || memRegValid || wbRegValid) ||
         idCsrEn && csr.io.decode(0).fpCsr && !io.fpu.map(_.fcsr_rdy).getOrElse(false.B) || io.traceStall ||
         !clockEnable ||
-        Option
-          .when(usingFPU)(
-            (idDecodeOutput(parameter.decoderParameter.fp) || idDecodeOutput(
-              parameter.decoderParameter.vectorReadFRs1
-            )) && idStallFpu
-          )
-          .getOrElse(false.B) ||
+        Option.when(usingFPU)(idDecodeOutput(parameter.decoderParameter.fp) && idStallFpu).getOrElse(false.B) ||
         idDecodeOutput(parameter.decoderParameter.mem) && dcacheBlocked || // reduce activity during D$ misses
         Option
           .when(usingMulDiv)(
@@ -1509,11 +1503,7 @@ class Rocket(val parameter: RocketParameter)
     io.fpu.foreach { fpu =>
       fpuDecoder.get.io.instruction := idInstruction
       fpu.dec                       := fpuDecoder.get.io.output
-      fpu.valid                     := !ctrlKilled && (
-        idDecodeOutput(parameter.decoderParameter.fp) ||
-          // vector read frs1
-          (fpu.dec.ren1 && idDecodeOutput(parameter.decoderParameter.vector))
-      )
+      fpu.valid                     := !ctrlKilled && idDecodeOutput(parameter.decoderParameter.fp)
       fpu.killx                     := ctrlKillx
       fpu.killm                     := killmCommon
       fpu.inst                      := idInstruction