From cdb9f6194f252f400e94019751f08a54892cdf71 Mon Sep 17 00:00:00 2001 From: qinjun-li Date: Tue, 3 Sep 2024 13:38:34 +0800 Subject: [PATCH] [rocketv] Supplement vector related csr modification. --- rocketv/src/CSR.scala | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/rocketv/src/CSR.scala b/rocketv/src/CSR.scala index a1248a366..cf323f327 100644 --- a/rocketv/src/CSR.scala +++ b/rocketv/src/CSR.scala @@ -1703,12 +1703,13 @@ class CSR(val parameter: CSRParameter) val newVType = Mux1H( Seq( (vsetvli || vsetivli) -> io.inst(0)(27, 20), - vsetvl -> io.wbRegRS2.get(7, 0) + vsetvl -> io.wbRegRS2.get ) ) + val newTypMSBValid: Bool = (newVType >> 8).asUInt.orR // todo: xLen -> vector.elen val vlmulIllList = Seq(0.U, 1.U, 2.U, 3.U)++ Option.when(xLen>=16)(7.U) ++ Option.when(xLen>=32)(6.U) ++ Option.when(xLen>=64)(5.U) - val vlmulIll: Bool = vlmulIllList.map(_ === newVType(2, 0)).reduce(_ || _) + val vlmulIll: Bool = vlmulIllList.map(_ === newVType(2, 0)).reduce(_ || _) && !newTypMSBValid // vlmax = vlen * lmul / sew val vlmax: UInt = (true.B << (log2Ceil(vLen) - 6) << (newVType(2, 0) + 3.U) >> newVType(5, 3)).asUInt // set vl @@ -1743,6 +1744,9 @@ class CSR(val parameter: CSRParameter) when(decoded_addr(CSRs.vxrm)) { vector.get.states("vxrm") := wdata } + when(decoded_addr(CSRs.vxsat)) { + vector.get.states("vxsat") := wdata + } when(decoded_addr(CSRs.vcsr)) { vector.get.states("vxrm") := wdata(2, 1) vector.get.states("vxsat") := wdata(0)