From c8f1ded6b0d5dbf41cd1730f300b9b343636399a Mon Sep 17 00:00:00 2001 From: Clo91eaf Date: Tue, 6 Aug 2024 11:45:30 +0800 Subject: [PATCH] [ipemu] refactor probe signatures to improve readability --- t1/src/Lane.scala | 29 ++++++++++++----------------- t1/src/T1.scala | 18 +++++++++--------- t1/src/vrf/VRF.scala | 16 ++++++++-------- 3 files changed, 29 insertions(+), 34 deletions(-) diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala index aeb388ae85..49ddff3ee5 100644 --- a/t1/src/Lane.scala +++ b/t1/src/Lane.scala @@ -27,7 +27,7 @@ class LaneOM extends Class { vfus := vfusIn } -class LaneSlotProbe(instructionIndexBit: Int) extends Bundle { +class LaneSlotProbe(instructionIndexBits: Int) extends Bundle { val stage0EnqueueReady: Bool = Bool() val stage0EnqueueValid: Bool = Bool() val changingMaskSet: Bool = Bool() @@ -44,17 +44,17 @@ class LaneSlotProbe(instructionIndexBit: Int) extends Bundle { // write queue enq for lane val writeQueueEnq: Bool = Bool() - val writeTag: UInt = UInt(instructionIndexBit.W) + val writeTag: UInt = UInt(instructionIndexBits.W) val writeMask: UInt = UInt(4.W) } -class LaneWriteProbe(instructionIndexBit: Int) extends Bundle { - val writeTag: UInt = UInt(instructionIndexBit.W) +class LaneWriteProbe(instructionIndexBits: Int) extends Bundle { + val writeTag: UInt = UInt(instructionIndexBits.W) val writeMask: UInt = UInt(4.W) } -class LaneProbe(slotsSize: Int, instructionIndexBit: Int) extends Bundle { - val slots = Vec(slotsSize, new LaneSlotProbe(instructionIndexBit)) +class LaneProbe(parameter: LaneParameter) extends Bundle { + val slots = Vec(parameter.chainingSize, new LaneSlotProbe(parameter.instructionIndexBits)) // @todo @Clo91eaf remove valid here, add stall := valid & !ready val laneRequestValid: Bool = Bool() // @todo remove it. @@ -63,10 +63,10 @@ class LaneProbe(slotsSize: Int, instructionIndexBit: Int) extends Bundle { val lastSlotOccupied: Bool = Bool() // @todo replace it with VRFProbe val vrfInstructionWriteReportReady: Bool = Bool() - val instructionFinished: UInt = UInt(slotsSize.W) - val instructionValid: UInt = UInt(slotsSize.W) + val instructionFinished: UInt = UInt(parameter.chainingSize.W) + val instructionValid: UInt = UInt(parameter.chainingSize.W) - val crossWriteProbe: Vec[ValidIO[LaneWriteProbe]] = Vec(2, Valid(new LaneWriteProbe(instructionIndexBit))) + val crossWriteProbe: Vec[ValidIO[LaneWriteProbe]] = Vec(2, Valid(new LaneWriteProbe(parameter.instructionIndexBits))) } object LaneParameter { @@ -314,16 +314,11 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ val vrfReadyToStore: Bool = IO(Output(Bool())) @public - val probe: LaneProbe = IO(Output(Probe(new LaneProbe(parameter.chainingSize, parameter.instructionIndexBits)))) - val probeWire: LaneProbe = Wire(new LaneProbe(parameter.chainingSize, parameter.instructionIndexBits)) + val probe: LaneProbe = IO(Output(Probe(new LaneProbe(parameter)))) + val probeWire: LaneProbe = Wire(new LaneProbe(parameter)) define(probe, ProbeValue(probeWire)) @public - val vrfProbe = IO(Output(Probe(new VRFProbe( - parameter.vrfParam.regNumBits, - parameter.vrfOffsetBits, - parameter.instructionIndexBits, - parameter.datapathWidth - )))) + val vrfProbe = IO(Output(Probe(new VRFProbe(parameter.vrfParam)))) @public val vrfAllocateIssue: Bool = IO(Output(Bool())) diff --git a/t1/src/T1.scala b/t1/src/T1.scala index 1395dd89b2..af110821c1 100644 --- a/t1/src/T1.scala +++ b/t1/src/T1.scala @@ -292,18 +292,18 @@ case class T1Parameter( def adderParam: LaneAdderParam = LaneAdderParam(datapathWidth, 0) } -class T1Probe(param: T1Parameter) extends Bundle { - val instructionCounter: UInt = UInt(param.instructionIndexBits.W) +class T1Probe(parameter: T1Parameter) extends Bundle { + val instructionCounter: UInt = UInt(parameter.instructionIndexBits.W) val instructionIssue: Bool = Bool() - val issueTag: UInt = UInt(param.instructionIndexBits.W) + val issueTag: UInt = UInt(parameter.instructionIndexBits.W) val retireValid: Bool = Bool() // write queue enq for mask unit - val writeQueueEnq: ValidIO[UInt] = Valid(UInt(param.instructionIndexBits.W)) - val writeQueueEnqMask: UInt = UInt((param.datapathWidth / 8).W) + val writeQueueEnq: ValidIO[UInt] = Valid(UInt(parameter.instructionIndexBits.W)) + val writeQueueEnqMask: UInt = UInt((parameter.datapathWidth / 8).W) // mask unit instruction valid - val instructionValid: UInt = UInt((param.chainingSize * 2).W) + val instructionValid: UInt = UInt((parameter.chainingSize * 2).W) // instruction index for check rd - val responseCounter: UInt = UInt(param.instructionIndexBits.W) + val responseCounter: UInt = UInt(parameter.instructionIndexBits.W) } class T1Interface(parameter: T1Parameter) extends Record { @@ -332,10 +332,10 @@ class T1Interface(parameter: T1Parameter) extends Record { "t1Probe" -> Output(Probe(new T1Probe(parameter))), ) ++ Seq.tabulate(parameter.laneNumber)( - i => s"lane${i}Probe" -> Output(Probe(new LaneProbe(parameter.chainingSize, parameter.instructionIndexBits))) + i => s"lane${i}Probe" -> Output(Probe(new LaneProbe(parameter.laneParam))) ) ++ Seq.tabulate(parameter.laneNumber)( - i => s"lane${i}VrfProbe" -> Output(Probe(new VRFProbe(parameter.laneParam.vrfParam.regNumBits, parameter.laneParam.vrfOffsetBits, parameter.laneParam.instructionIndexBits, parameter.laneParam.datapathWidth))) + i => s"lane${i}VrfProbe" -> Output(Probe(new VRFProbe(parameter.laneParam.vrfParam))) ) ) } diff --git a/t1/src/vrf/VRF.scala b/t1/src/vrf/VRF.scala index 179a321079..61df7864bd 100644 --- a/t1/src/vrf/VRF.scala +++ b/t1/src/vrf/VRF.scala @@ -106,13 +106,13 @@ case class VRFParam( val vrfReadLatency = 2 } -class VRFProbe(regNumBits: Int, offsetBits: Int, instructionIndexSize: Int, dataPathWidth: Int) extends Bundle { +class VRFProbe(parameter: VRFParam) extends Bundle { val valid: Bool = Bool() - val requestVd: UInt = UInt(regNumBits.W) - val requestOffset: UInt = UInt(offsetBits.W) - val requestMask: UInt = UInt((dataPathWidth / 8).W) - val requestData: UInt = UInt(dataPathWidth.W) - val requestInstruction: UInt = UInt(instructionIndexSize.W) + val requestVd: UInt = UInt(parameter.regNumBits.W) + val requestOffset: UInt = UInt(parameter.vrfOffsetBits.W) + val requestMask: UInt = UInt((parameter.datapathWidth / 8).W) + val requestData: UInt = UInt(parameter.datapathWidth.W) + val requestInstruction: UInt = UInt(parameter.instructionIndexBits.W) } /** Vector Register File. @@ -564,8 +564,8 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar * Probe */ @public - val probe = IO(Output(Probe(new VRFProbe(parameter.regNumBits, parameter.vrfOffsetBits, parameter.instructionIndexBits, parameter.datapathWidth)))) - val probeWire = Wire(new VRFProbe(parameter.regNumBits, parameter.vrfOffsetBits, parameter.instructionIndexBits, parameter.datapathWidth)) + val probe = IO(Output(Probe(new VRFProbe(parameter)))) + val probeWire = Wire(new VRFProbe(parameter)) define(probe, ProbeValue(probeWire)) probeWire.valid := writePipe.valid