diff --git a/t1/src/lsu/SimpleAccessUnit.scala b/t1/src/lsu/SimpleAccessUnit.scala
index d4c0bb458..3ba429f98 100644
--- a/t1/src/lsu/SimpleAccessUnit.scala
+++ b/t1/src/lsu/SimpleAccessUnit.scala
@@ -667,8 +667,10 @@ class SimpleAccessUnit(param: MSHRParam) extends Module with LSUPublic {
   /** all check is ready, being able to send request to pipeline. */
   val stateReady: Bool = stateIsRequest && maskCheck && indexCheck && fofCheck
 
+  // state === idle: All the remaining elements are removed by the mask,
+  // but there is still offset left.
   /** signal to request offset in the pipeline, only assert for one cycle. */
-  requestOffset := stateIsRequest && maskCheck && !indexCheck && fofCheck
+  requestOffset := stateIsRequest && maskCheck && !indexCheck && fofCheck || state === idle
 
   val s0DequeueFire: Bool = Wire(Bool())
 
@@ -954,6 +956,7 @@ class SimpleAccessUnit(param: MSHRParam) extends Module with LSUPublic {
   // handle corner case for vl=0
   val invalidInstruction:     Bool = csrInterface.vl === 0.U && !requestIsWholeRegisterLoadStore && lsuRequest.valid
   val invalidInstructionNext: Bool = RegNext(invalidInstruction)
+  val allElementsMasked:      Bool = state === idle && offsetQueueVec.map(_.deq.fire).reduce(_ || _)
 
   // change state to request
   when(lsuRequest.valid && !invalidInstruction) {
@@ -967,7 +970,7 @@ class SimpleAccessUnit(param: MSHRParam) extends Module with LSUPublic {
   /** the current state is idle. */
   val stateIdle = state === idle
   status.idle              := stateIdle
-  status.last              := (!RegNext(stateIdle) && stateIdle) || invalidInstructionNext
+  status.last              := (!RegNext(stateIdle) && stateIdle) || invalidInstructionNext || allElementsMasked
   status.changeMaskGroup   := updateOffsetGroupEnable
   // which lane to access
   status.targetLane        := {