diff --git a/rocketv/src/Bundle.scala b/rocketv/src/Bundle.scala
index 31bc2ba165..b99e832711 100644
--- a/rocketv/src/Bundle.scala
+++ b/rocketv/src/Bundle.scala
@@ -1074,7 +1074,7 @@ class FPUCoreIO(hartIdLen: Int, xLen: Int, fLen: Int) extends Bundle {
   val illegal_rm = Output(Bool())
   val killx = Input(Bool())
   val killm = Input(Bool())
-  val dec = Output(new FPUCtrlSigs())
+  val dec = Input(new FPUCtrlSigs())
   val sboard_set = Output(Bool())
   val sboard_clr = Output(Bool())
   val sboard_clra = Output(UInt(5.W))
diff --git a/rocketv/src/Decoder.scala b/rocketv/src/Decoder.scala
index ac57b723d1..dd4abaca0d 100644
--- a/rocketv/src/Decoder.scala
+++ b/rocketv/src/Decoder.scala
@@ -54,7 +54,9 @@ object DecoderParameter {
 case class DecoderParameter(
   instructionSets:   Set[String],
   pipelinedMul:      Boolean,
-  fenceIFlushDCache: Boolean)
+  fenceIFlushDCache: Boolean,
+  minFLen:           Int = 16,
+  xLen:              Int = 32)
     extends SerializableModuleParameter {
   val instructions: Seq[Instruction] =
     org.chipsalliance.rvdecoderdb
@@ -122,11 +124,35 @@ case class DecoderParameter(
   private val Y = BitPat.Y()
   private val N = BitPat.N()
 
+  private val FPUDecodeFields: Seq[DecodeField[RocketDecodePattern, _ <: Data]] = Seq(
+    fldst,
+    fwen,
+    fren1,
+    fren2,
+    fren3,
+    fswap12,
+    fswap23,
+    ftypeTagIn,
+    ftypeTagOut,
+    ffromint,
+    ftoint,
+    ffastpipe,
+    ffma,
+    fdiv,
+    fsqrt,
+    fwflags
+  )
+
   val table: DecodeTable[RocketDecodePattern] = new DecodeTable[RocketDecodePattern](
     instructionDecodePatterns,
     instructionDecodeFields
   )
 
+  val floatTable: DecodeTable[RocketDecodePattern] = new DecodeTable[RocketDecodePattern](
+    instructionDecodePatterns,
+    FPUDecodeFields
+  )
+
   object isLegal extends BoolDecodeField[RocketDecodePattern] {
     override def name: String = "legal"
 
@@ -693,6 +719,174 @@ case class DecoderParameter(
 
     override def genTable(op: RocketDecodePattern): BitPat = if (op.isVectorCSR) Y else N
   }
+
+  // fpu decode
+  object fldst extends BoolDecodeField[RocketDecodePattern] {
+    override def name: String = "ldst"
+
+    override def genTable(op: RocketDecodePattern): BitPat = op.instruction.name match {
+      case i if Seq("flh", "fsh", "flw", "fsw", "fld", "fsd").contains(i) => y
+      case i if Seq("fmv.h.x", "fcvt.h.w", "fcvt.h.wu", "fcvt.h.l", "fcvt.h.lu", "fmv.x.h", "fclass.h", "fcvt.w.h", "fcvt.wu.h", "fcvt.l.h", "fcvt.lu.h", "fcvt.s.h", "fcvt.h.s", "feq.h", "flt.h", "fle.h", "fsgnj.h", "fsgnjn.h", "fsgnjx.h", "fmin.h", "fmax.h", "fadd.h", "fsub.h", "fmul.h", "fmadd.h", "fmsub.h", "fnmadd.h", "fnmsub.h", "fdiv.h", "fsqrt.h", "fmv.w.x", "fcvt.s.w", "fcvt.s.wu", "fcvt.s.l", "fcvt.s.lu", "fmv.x.w", "fclass.s", "fcvt.w.s", "fcvt.wu.s", "fcvt.l.s", "fcvt.lu.s", "feq.s", "flt.s", "fle.s", "fsgnj.s", "fsgnjn.s", "fsgnjx.s", "fmin.s", "fmax.s", "fadd.s", "fsub.s", "fmul.s", "fmadd.s", "fmsub.s", "fnmadd.s", "fnmsub.s", "fdiv.s", "fsqrt.s", "fmv.d.x", "fcvt.d.w", "fcvt.d.wu", "fcvt.d.l", "fcvt.d.lu", "fmv.x.d", "fclass.d", "fcvt.w.d", "fcvt.wu.d", "fcvt.l.d", "fcvt.lu.d", "fcvt.s.d", "fcvt.d.s", "feq.d", "flt.d", "fle.d", "fsgnj.d", "fsgnjn.d", "fsgnjx.d", "fmin.d", "fmax.d", "fadd.d", "fsub.d", "fmul.d", "fmadd.d", "fmsub.d", "fnmadd.d", "fnmsub.d", "fdiv.d", "fsqrt.d", "fcvt.h.d", "fcvt.d.h").contains(i) => n
+      // todo: dc
+      case _ => n
+    }
+  }
+
+  object fwen extends BoolDecodeField[RocketDecodePattern] {
+    override def name: String = "wen"
+
+    override def genTable(op: RocketDecodePattern): BitPat = op.instruction.name match {
+      case i if Seq("flh", "fmv.h.x", "fcvt.h.w", "fcvt.h.wu", "fcvt.h.l", "fcvt.h.lu", "fcvt.s.h", "fcvt.h.s", "fsgnj.h", "fsgnjn.h", "fsgnjx.h", "fmin.h", "fmax.h", "fadd.h", "fsub.h", "fmul.h", "fmadd.h", "fmsub.h", "fnmadd.h", "fnmsub.h", "fdiv.h", "fsqrt.h", "flw", "fmv.w.x", "fcvt.s.w", "fcvt.s.wu", "fcvt.s.l", "fcvt.s.lu", "fsgnj.s", "fsgnjn.s", "fsgnjx.s", "fmin.s", "fmax.s", "fadd.s", "fsub.s", "fmul.s", "fmadd.s", "fmsub.s", "fnmadd.s", "fnmsub.s", "fdiv.s", "fsqrt.s", "fld", "fmv.d.x", "fcvt.d.w", "fcvt.d.wu", "fcvt.d.l", "fcvt.d.lu", "fcvt.s.d", "fcvt.d.s", "fsgnj.d", "fsgnjn.d", "fsgnjx.d", "fmin.d", "fmax.d", "fadd.d", "fsub.d", "fmul.d", "fmadd.d", "fmsub.d", "fnmadd.d", "fnmsub.d", "fdiv.d", "fsqrt.d", "fcvt.h.d", "fcvt.d.h").contains(i) => y
+      case _ => n
+    }
+  }
+
+  object fren1 extends BoolDecodeField[RocketDecodePattern] {
+    override def name: String = "ren1"
+
+    override def genTable(op: RocketDecodePattern): BitPat = op.instruction.name match {
+      case i if Seq("fmv.x.h", "fclass.h", "fcvt.w.h", "fcvt.wu.h", "fcvt.l.h", "fcvt.lu.h", "fcvt.s.h", "fcvt.h.s", "feq.h", "flt.h", "fle.h", "fsgnj.h", "fsgnjn.h", "fsgnjx.h", "fmin.h", "fmax.h", "fadd.h", "fsub.h", "fmul.h", "fmadd.h", "fmsub.h", "fnmadd.h", "fnmsub.h", "fdiv.h", "fsqrt.h", "fmv.x.w", "fclass.s", "fcvt.w.s", "fcvt.wu.s", "fcvt.l.s", "fcvt.lu.s", "feq.s", "flt.s", "fle.s", "fsgnj.s", "fsgnjn.s", "fsgnjx.s", "fmin.s", "fmax.s", "fadd.s", "fsub.s", "fmul.s", "fmadd.s", "fmsub.s", "fnmadd.s", "fnmsub.s", "fdiv.s", "fsqrt.s", "fmv.x.d", "fclass.d", "fcvt.w.d", "fcvt.wu.d", "fcvt.l.d", "fcvt.lu.d", "fcvt.s.d", "fcvt.d.s", "feq.d", "flt.d", "fle.d", "fsgnj.d", "fsgnjn.d", "fsgnjx.d", "fmin.d", "fmax.d", "fadd.d", "fsub.d", "fmul.d", "fmadd.d", "fmsub.d", "fnmadd.d", "fnmsub.d", "fdiv.d", "fsqrt.d", "fcvt.h.d", "fcvt.d.h").contains(i) => y
+      case _ => n
+    }
+  }
+
+  object fren2 extends BoolDecodeField[RocketDecodePattern] {
+    override def name: String = "ren2"
+
+    override def genTable(op: RocketDecodePattern): BitPat = op.instruction.name match {
+      case i if Seq("fsh", "feq.h", "flt.h", "fle.h", "fsgnj.h", "fsgnjn.h", "fsgnjx.h", "fmin.h", "fmax.h", "fadd.h", "fsub.h", "fmul.h", "fmadd.h", "fmsub.h", "fnmadd.h", "fnmsub.h", "fdiv.h", "fsw", "feq.s", "flt.s", "fle.s", "fsgnj.s", "fsgnjn.s", "fsgnjx.s", "fmin.s", "fmax.s", "fadd.s", "fsub.s", "fmul.s", "fmadd.s", "fmsub.s", "fnmadd.s", "fnmsub.s", "fdiv.s", "fsd", "feq.d", "flt.d", "fle.d", "fsgnj.d", "fsgnjn.d", "fsgnjx.d", "fmin.d", "fmax.d", "fadd.d", "fsub.d", "fmul.d", "fmadd.d", "fmsub.d", "fnmadd.d", "fnmsub.d", "fdiv.d").contains(i) => y
+      case _ => n
+    }
+  }
+
+  object fren3 extends BoolDecodeField[RocketDecodePattern] {
+    override def name: String = "ren3"
+
+    override def genTable(op: RocketDecodePattern): BitPat = op.instruction.name match {
+      case i if Seq("fmadd.h", "fmsub.h", "fnmadd.h", "fnmsub.h", "fmadd.s", "fmsub.s", "fnmadd.s", "fnmsub.s", "fmadd.d", "fmsub.d", "fnmadd.d", "fnmsub.d").contains(i) => y
+      case _ => n
+    }
+  }
+
+  object fswap12 extends BoolDecodeField[RocketDecodePattern] {
+    override def name: String = "swap12"
+
+    override def genTable(op: RocketDecodePattern): BitPat = op.instruction.name match {
+      case i if Seq("fsh", "fsw", "fsd").contains(i) => y
+      case _ => n
+    }
+  }
+
+  object fswap23 extends BoolDecodeField[RocketDecodePattern] {
+    override def name: String = "swap23"
+
+    override def genTable(op: RocketDecodePattern): BitPat = op.instruction.name match {
+      case i if Seq("fadd.h", "fsub.h", "fadd.s", "fsub.s", "fadd.d", "fsub.d").contains(i) => y
+      case _ => n
+    }
+  }
+
+  object UOPFType extends UOP {
+    val helper = new FPUHelper(minFLen, minFLen, xLen)
+    // TODO: wtf here.
+    def H = BitPat(helper.H)
+    def I = BitPat(helper.I)
+    def D = BitPat(helper.D)
+    def S = BitPat(helper.S)
+    def width = D.getWidth
+    def X2 = BitPat.dontCare(width)
+  }
+
+  object ftypeTagIn extends UOPDecodeField[RocketDecodePattern] {
+    override def name: String = "typeTagIn"
+
+    override def genTable(op: RocketDecodePattern): BitPat = op.instruction.name match {
+      case i if Seq("fsh", "fmv.x.h", "fsw", "fmv.x.w", "fsd", "fmv.x.d").contains(i) => UOPFType.I
+      case i if Seq("fmv.h.x", "fcvt.h.w", "fcvt.h.wu", "fcvt.h.l", "fcvt.h.lu", "fclass.h", "fcvt.w.h", "fcvt.wu.h", "fcvt.l.h", "fcvt.lu.h", "fcvt.s.h", "feq.h", "flt.h", "fle.h", "fsgnj.h", "fsgnjn.h", "fsgnjx.h", "fmin.h", "fmax.h", "fadd.h", "fsub.h", "fmul.h", "fmadd.h", "fmsub.h", "fnmadd.h", "fnmsub.h", "fdiv.h", "fsqrt.h", "fcvt.d.h").contains(i) => UOPFType.H
+      case i if Seq("fcvt.h.s", "fmv.w.x", "fcvt.s.w", "fcvt.s.wu", "fcvt.s.l", "fcvt.s.lu", "fclass.s", "fcvt.w.s", "fcvt.wu.s", "fcvt.l.s", "fcvt.lu.s", "feq.s", "flt.s", "fle.s", "fsgnj.s", "fsgnjn.s", "fsgnjx.s", "fmin.s", "fmax.s", "fadd.s", "fsub.s", "fmul.s", "fmadd.s", "fmsub.s", "fnmadd.s", "fnmsub.s", "fdiv.s", "fsqrt.s", "fcvt.d.s").contains(i) => UOPFType.S
+      case i if Seq("fmv.d.x", "fcvt.d.w", "fcvt.d.wu", "fcvt.d.l", "fcvt.d.lu", "fclass.d", "fcvt.w.d", "fcvt.wu.d", "fcvt.l.d", "fcvt.lu.d", "fcvt.s.d", "feq.d", "flt.d", "fle.d", "fsgnj.d", "fsgnjn.d", "fsgnjx.d", "fmin.d", "fmax.d", "fadd.d", "fsub.d", "fmul.d", "fmadd.d", "fmsub.d", "fnmadd.d", "fnmsub.d", "fdiv.d", "fsqrt.d", "fcvt.h.d").contains(i) => UOPFType.D
+      case _ => UOPFType.X2
+    }
+
+    override def uopType: UOPFType.type = UOPFType
+  }
+
+  object ftypeTagOut extends UOPDecodeField[RocketDecodePattern] {
+    override def name: String = "typeTagOut"
+
+    override def genTable(op: RocketDecodePattern): BitPat = op.instruction.name match {
+      case i if Seq("fmv.h.x", "fmv.w.x", "fmv.d.x").contains(i) => UOPFType.I
+      case i if Seq("fsh", "fcvt.h.w", "fcvt.h.wu", "fcvt.h.l", "fcvt.h.lu", "fmv.x.h", "fclass.h", "fcvt.h.s", "feq.h", "flt.h", "fle.h", "fsgnj.h", "fsgnjn.h", "fsgnjx.h", "fmin.h", "fmax.h", "fadd.h", "fsub.h", "fmul.h", "fmadd.h", "fmsub.h", "fnmadd.h", "fnmsub.h", "fdiv.h", "fsqrt.h", "fcvt.h.d").contains(i) => UOPFType.H
+      case i if Seq("fcvt.s.h", "fsw", "fcvt.s.w", "fcvt.s.wu", "fcvt.s.l", "fcvt.s.lu", "fmv.x.w", "fclass.s", "feq.s", "flt.s", "fle.s", "fsgnj.s", "fsgnjn.s", "fsgnjx.s", "fmin.s", "fmax.s", "fadd.s", "fsub.s", "fmul.s", "fmadd.s", "fmsub.s", "fnmadd.s", "fnmsub.s", "fdiv.s", "fsqrt.s", "fcvt.s.d").contains(i) => UOPFType.S
+      case i if Seq("fsd", "fcvt.d.w", "fcvt.d.wu", "fcvt.d.l", "fcvt.d.lu", "fmv.x.d", "fclass.d", "fcvt.d.s", "feq.d", "flt.d", "fle.d", "fsgnj.d", "fsgnjn.d", "fsgnjx.d", "fmin.d", "fmax.d", "fadd.d", "fsub.d", "fmul.d", "fmadd.d", "fmsub.d", "fnmadd.d", "fnmsub.d", "fdiv.d", "fsqrt.d", "fcvt.d.h").contains(i) => UOPFType.D
+      case _ => UOPFType.X2
+    }
+
+    override def uopType: UOPFType.type = UOPFType
+  }
+
+  object ffromint extends BoolDecodeField[RocketDecodePattern] {
+    override def name: String = "fromint"
+
+    override def genTable(op: RocketDecodePattern): BitPat = op.instruction.name match {
+      case i if Seq("fmv.h.x", "fcvt.h.w", "fcvt.h.wu", "fcvt.h.l", "fcvt.h.lu", "fmv.w.x", "fcvt.s.w", "fcvt.s.wu", "fcvt.s.l", "fcvt.s.lu", "fmv.d.x", "fcvt.d.w", "fcvt.d.wu", "fcvt.d.l", "fcvt.d.lu").contains(i) => y
+      case _ => n
+    }
+  }
+
+  object ftoint extends BoolDecodeField[RocketDecodePattern] {
+    override def name: String = "toint"
+
+    override def genTable(op: RocketDecodePattern): BitPat = op.instruction.name match {
+      case i if Seq("fsh", "fmv.x.h", "fclass.h", "fcvt.w.h", "fcvt.wu.h", "fcvt.l.h", "fcvt.lu.h", "feq.h", "flt.h", "fle.h", "fsw", "fmv.x.w", "fclass.s", "fcvt.w.s", "fcvt.wu.s", "fcvt.l.s", "fcvt.lu.s", "feq.s", "flt.s", "fle.s", "fsd", "fmv.x.d", "fclass.d", "fcvt.w.d", "fcvt.wu.d", "fcvt.l.d", "fcvt.lu.d", "feq.d", "flt.d", "fle.d").contains(i) => y
+      case _ => n
+    }
+  }
+
+  object ffastpipe extends BoolDecodeField[RocketDecodePattern] {
+    override def name: String = "fastpipe"
+
+    override def genTable(op: RocketDecodePattern): BitPat = op.instruction.name match {
+      case i if Seq("fcvt.s.h", "fcvt.h.s", "fsgnj.h", "fsgnjn.h", "fsgnjx.h", "fmin.h", "fmax.h", "fsgnj.s", "fsgnjn.s", "fsgnjx.s", "fmin.s", "fmax.s", "fcvt.s.d", "fcvt.d.s", "fsgnj.d", "fsgnjn.d", "fsgnjx.d", "fmin.d", "fmax.d", "fcvt.h.d", "fcvt.d.h").contains(i) => y
+      case _ => n
+    }
+  }
+
+  object ffma extends BoolDecodeField[RocketDecodePattern] {
+    override def name: String = "fma"
+
+    override def genTable(op: RocketDecodePattern): BitPat = op.instruction.name match {
+      case i if Seq("fadd.h", "fsub.h", "fmul.h", "fmadd.h", "fmsub.h", "fnmadd.h", "fnmsub.h", "fadd.s", "fsub.s", "fmul.s", "fmadd.s", "fmsub.s", "fnmadd.s", "fnmsub.s", "fadd.d", "fsub.d", "fmul.d", "fmadd.d", "fmsub.d", "fnmadd.d", "fnmsub.d").contains(i) => y
+      case _ => n
+    }
+  }
+
+  object fdiv extends BoolDecodeField[RocketDecodePattern] {
+    override def name: String = "div"
+
+    override def genTable(op: RocketDecodePattern): BitPat = op.instruction.name match {
+      case i if Seq("fdiv.h", "fdiv.s", "fdiv.d").contains(i) => y
+      case _ => n
+    }
+  }
+
+  object fsqrt extends BoolDecodeField[RocketDecodePattern] {
+    override def name: String = "sqrt"
+
+    override def genTable(op: RocketDecodePattern): BitPat = op.instruction.name match {
+      case i if Seq("fsqrt.h", "fsqrt.s", "fsqrt.d").contains(i) => y
+      case _ => n
+    }
+  }
+
+  object fwflags extends BoolDecodeField[RocketDecodePattern] {
+    override def name: String = "wflags"
+
+    override def genTable(op: RocketDecodePattern): BitPat = op.instruction.name match {
+      case i if Seq("fcvt.h.w", "fcvt.h.wu", "fcvt.h.l", "fcvt.h.lu", "fcvt.w.h", "fcvt.wu.h", "fcvt.l.h", "fcvt.lu.h", "fcvt.s.h", "fcvt.h.s", "feq.h", "flt.h", "fle.h", "fmin.h", "fmax.h", "fadd.h", "fsub.h", "fmul.h", "fmadd.h", "fmsub.h", "fnmadd.h", "fnmsub.h", "fdiv.h", "fsqrt.h", "fcvt.s.w", "fcvt.s.wu", "fcvt.s.l", "fcvt.s.lu", "fcvt.w.s", "fcvt.wu.s", "fcvt.l.s", "fcvt.lu.s", "feq.s", "flt.s", "fle.s", "fmin.s", "fmax.s", "fadd.s", "fsub.s", "fmul.s", "fmadd.s", "fmsub.s", "fnmadd.s", "fnmsub.s", "fdiv.s", "fsqrt.s", "fcvt.d.w", "fcvt.d.wu", "fcvt.d.l", "fcvt.d.lu", "fcvt.w.d", "fcvt.wu.d", "fcvt.l.d", "fcvt.lu.d", "fcvt.s.d", "fcvt.d.s", "feq.d", "flt.d", "fle.d", "fmin.d", "fmax.d", "fadd.d", "fsub.d", "fmul.d", "fmadd.d", "fmsub.d", "fnmadd.d", "fnmsub.d", "fdiv.d", "fsqrt.d", "fcvt.h.d", "fcvt.d.h").contains(i) => y
+      case _ => n
+    }
+  }
 }
 
 class DecoderInterface(parameter: DecoderParameter) extends Bundle {
@@ -700,6 +894,11 @@ class DecoderInterface(parameter: DecoderParameter) extends Bundle {
   val output = Output(parameter.table.bundle)
 }
 
+class FPUDecoderInterface(parameter: DecoderParameter) extends Bundle {
+  val instruction = Input(UInt(32.W))
+  val output = Output(parameter.floatTable.bundle)
+}
+
 /** DecodePattern for an RISC-V instruction */
 case class RocketDecodePattern(instruction: Instruction) extends DecodePattern {
   override def bitPat: BitPat = BitPat("b" + instruction.encoding.toString)
@@ -750,3 +949,10 @@ class Decoder(val parameter: DecoderParameter)
     with SerializableModule[DecoderParameter] {
   io.output := parameter.table.decode(io.instruction)
 }
+
+@instantiable
+class FPUDecoder(val parameter: DecoderParameter)
+  extends FixedIORawModule(new FPUDecoderInterface(parameter))
+    with SerializableModule[DecoderParameter] {
+  io.output := parameter.floatTable.decode(io.instruction)
+}
diff --git a/rocketv/src/FPU.scala b/rocketv/src/FPU.scala
index 4f5fe0eca0..b936e85ae1 100644
--- a/rocketv/src/FPU.scala
+++ b/rocketv/src/FPU.scala
@@ -80,10 +80,7 @@ class FPU(val parameter: FPUParameter)
     if (!useClockGating) io.clock
     else ClockGate(io.clock, clock_en)
 
-  // TODO: remove me.
-  val fp_decoder = Module(new FPUDecoder(parameter))
-  fp_decoder.io.inst := io.core.inst
-  val id_ctrl = fp_decoder.io.sigs
+  val id_ctrl = io.core.dec
 
   val ex_reg_valid = RegNext(io.core.valid, false.B)
   val ex_reg_inst = RegEnable(io.core.inst, io.core.valid)
@@ -365,7 +362,6 @@ class FPU(val parameter: FPUParameter)
     val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
     io.core.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
     io.core.nack_mem := write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight
-    io.core.dec <> fp_decoder.io.sigs
     def useScoreboard(f: ((Pipe[_], Int)) => Bool) =
       pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_ || _)
     io.core.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(
@@ -435,263 +431,6 @@ class FPU(val parameter: FPUParameter)
   val fpuImpl = withClockAndReset(gated_clock, io.reset) { new FPUImpl }
 }
 
-class FPUDecoderInterface(parameter: FPUParameter) extends Bundle {
-  val inst = Input(UInt(32.W))
-  val sigs = Output(new FPUCtrlSigs())
-}
-
-// TODO: we should eliminate this module and move it to CoreDecoder with optional fields.
-class FPUDecoder(val parameter: FPUParameter)
-    extends FixedIORawModule(new FPUDecoderInterface(parameter))
-    with SerializableModule[FPUParameter] {
-  val X2 = BitPat.dontCare(2)
-  val X = BitPat.dontCare(1)
-  val N = BitPat.N()
-  val Y = BitPat.N()
-  val helper = new FPUHelper(parameter.minFLen, parameter.minFLen, parameter.xLen)
-  // TODO: wtf here.
-  def H = BitPat(helper.H)
-  def I = BitPat(helper.I)
-  def D = BitPat(helper.D)
-  def S = BitPat(helper.S)
-
-  def FADD_D = BitPat("b0000001??????????????????1010011")
-  def FADD_H = BitPat("b0000010??????????????????1010011")
-  def FADD_S = BitPat("b0000000??????????????????1010011")
-  def FCLASS_D = BitPat("b111000100000?????001?????1010011")
-  def FCLASS_H = BitPat("b111001000000?????001?????1010011")
-  def FCLASS_S = BitPat("b111000000000?????001?????1010011")
-  def FCVT_D_H = BitPat("b010000100010?????????????1010011")
-  def FCVT_D_L = BitPat("b110100100010?????????????1010011")
-  def FCVT_D_LU = BitPat("b110100100011?????????????1010011")
-  def FCVT_D_S = BitPat("b010000100000?????????????1010011")
-  def FCVT_D_W = BitPat("b110100100000?????????????1010011")
-  def FCVT_D_WU = BitPat("b110100100001?????????????1010011")
-  def FCVT_H_D = BitPat("b010001000001?????????????1010011")
-  def FCVT_H_L = BitPat("b110101000010?????????????1010011")
-  def FCVT_H_LU = BitPat("b110101000011?????????????1010011")
-  def FCVT_H_S = BitPat("b010001000000?????????????1010011")
-  def FCVT_H_W = BitPat("b110101000000?????????????1010011")
-  def FCVT_H_WU = BitPat("b110101000001?????????????1010011")
-  def FCVT_L_D = BitPat("b110000100010?????????????1010011")
-  def FCVT_L_H = BitPat("b110001000010?????????????1010011")
-  def FCVT_L_S = BitPat("b110000000010?????????????1010011")
-  def FCVT_LU_D = BitPat("b110000100011?????????????1010011")
-  def FCVT_LU_H = BitPat("b110001000011?????????????1010011")
-  def FCVT_LU_S = BitPat("b110000000011?????????????1010011")
-  def FCVT_S_D = BitPat("b010000000001?????????????1010011")
-  def FCVT_S_H = BitPat("b010000000010?????????????1010011")
-  def FCVT_S_L = BitPat("b110100000010?????????????1010011")
-  def FCVT_S_LU = BitPat("b110100000011?????????????1010011")
-  def FCVT_S_W = BitPat("b110100000000?????????????1010011")
-  def FCVT_S_WU = BitPat("b110100000001?????????????1010011")
-  def FCVT_W_D = BitPat("b110000100000?????????????1010011")
-  def FCVT_W_H = BitPat("b110001000000?????????????1010011")
-  def FCVT_W_S = BitPat("b110000000000?????????????1010011")
-  def FCVT_WU_D = BitPat("b110000100001?????????????1010011")
-  def FCVT_WU_H = BitPat("b110001000001?????????????1010011")
-  def FCVT_WU_S = BitPat("b110000000001?????????????1010011")
-  def FDIV_D = BitPat("b0001101??????????????????1010011")
-  def FDIV_H = BitPat("b0001110??????????????????1010011")
-  def FDIV_S = BitPat("b0001100??????????????????1010011")
-  def FEQ_D = BitPat("b1010001??????????010?????1010011")
-  def FEQ_H = BitPat("b1010010??????????010?????1010011")
-  def FEQ_S = BitPat("b1010000??????????010?????1010011")
-  def FLD = BitPat("b?????????????????011?????0000111")
-  def FLE_D = BitPat("b1010001??????????000?????1010011")
-  def FLE_H = BitPat("b1010010??????????000?????1010011")
-  def FLE_S = BitPat("b1010000??????????000?????1010011")
-  def FLH = BitPat("b?????????????????001?????0000111")
-  def FLT_D = BitPat("b1010001??????????001?????1010011")
-  def FLT_H = BitPat("b1010010??????????001?????1010011")
-  def FLT_S = BitPat("b1010000??????????001?????1010011")
-  def FLW = BitPat("b?????????????????010?????0000111")
-  def FMADD_D = BitPat("b?????01??????????????????1000011")
-  def FMADD_H = BitPat("b?????10??????????????????1000011")
-  def FMADD_S = BitPat("b?????00??????????????????1000011")
-  def FMAX_D = BitPat("b0010101??????????001?????1010011")
-  def FMAX_H = BitPat("b0010110??????????001?????1010011")
-  def FMAX_S = BitPat("b0010100??????????001?????1010011")
-  def FMIN_D = BitPat("b0010101??????????000?????1010011")
-  def FMIN_H = BitPat("b0010110??????????000?????1010011")
-  def FMIN_S = BitPat("b0010100??????????000?????1010011")
-  def FMSUB_D = BitPat("b?????01??????????????????1000111")
-  def FMSUB_H = BitPat("b?????10??????????????????1000111")
-  def FMSUB_S = BitPat("b?????00??????????????????1000111")
-  def FMUL_D = BitPat("b0001001??????????????????1010011")
-  def FMUL_H = BitPat("b0001010??????????????????1010011")
-  def FMUL_S = BitPat("b0001000??????????????????1010011")
-  def FMV_D_X = BitPat("b111100100000?????000?????1010011")
-  def FMV_H_X = BitPat("b111101000000?????000?????1010011")
-  def FMV_W_X = BitPat("b111100000000?????000?????1010011")
-  def FMV_X_D = BitPat("b111000100000?????000?????1010011")
-  def FMV_X_H = BitPat("b111001000000?????000?????1010011")
-  def FMV_X_W = BitPat("b111000000000?????000?????1010011")
-  def FNMADD_D = BitPat("b?????01??????????????????1001111")
-  def FNMADD_H = BitPat("b?????10??????????????????1001111")
-  def FNMADD_S = BitPat("b?????00??????????????????1001111")
-  def FNMSUB_D = BitPat("b?????01??????????????????1001011")
-  def FNMSUB_H = BitPat("b?????10??????????????????1001011")
-  def FNMSUB_S = BitPat("b?????00??????????????????1001011")
-  def FSD = BitPat("b?????????????????011?????0100111")
-  def FSGNJ_D = BitPat("b0010001??????????000?????1010011")
-  def FSGNJ_H = BitPat("b0010010??????????000?????1010011")
-  def FSGNJ_S = BitPat("b0010000??????????000?????1010011")
-  def FSGNJN_D = BitPat("b0010001??????????001?????1010011")
-  def FSGNJN_H = BitPat("b0010010??????????001?????1010011")
-  def FSGNJN_S = BitPat("b0010000??????????001?????1010011")
-  def FSGNJX_D = BitPat("b0010001??????????010?????1010011")
-  def FSGNJX_H = BitPat("b0010010??????????010?????1010011")
-  def FSGNJX_S = BitPat("b0010000??????????010?????1010011")
-  def FSH = BitPat("b?????????????????001?????0100111")
-  def FSQRT_D = BitPat("b010110100000?????????????1010011")
-  def FSQRT_H = BitPat("b010111000000?????????????1010011")
-  def FSQRT_S = BitPat("b010110000000?????????????1010011")
-  def FSUB_D = BitPat("b0000101??????????????????1010011")
-  def FSUB_H = BitPat("b0000110??????????????????1010011")
-  def FSUB_S = BitPat("b0000100??????????????????1010011")
-  def FSW = BitPat("b?????????????????010?????0100111")
-
-  val default = List(X, X, X, X, X, X, X, X2, X2, X, X, X, X, X, X, X)
-  val h: Array[(BitPat, List[BitPat])] =
-    Array(
-      FLH -> List(Y, Y, N, N, N, X, X, X2, X2, N, N, N, N, N, N, N),
-      FSH -> List(Y, N, N, Y, N, Y, X, I, H, N, Y, N, N, N, N, N),
-      FMV_H_X -> List(N, Y, N, N, N, X, X, H, I, Y, N, N, N, N, N, N),
-      FCVT_H_W -> List(N, Y, N, N, N, X, X, H, H, Y, N, N, N, N, N, Y),
-      FCVT_H_WU -> List(N, Y, N, N, N, X, X, H, H, Y, N, N, N, N, N, Y),
-      FCVT_H_L -> List(N, Y, N, N, N, X, X, H, H, Y, N, N, N, N, N, Y),
-      FCVT_H_LU -> List(N, Y, N, N, N, X, X, H, H, Y, N, N, N, N, N, Y),
-      FMV_X_H -> List(N, N, Y, N, N, N, X, I, H, N, Y, N, N, N, N, N),
-      FCLASS_H -> List(N, N, Y, N, N, N, X, H, H, N, Y, N, N, N, N, N),
-      FCVT_W_H -> List(N, N, Y, N, N, N, X, H, X2, N, Y, N, N, N, N, Y),
-      FCVT_WU_H -> List(N, N, Y, N, N, N, X, H, X2, N, Y, N, N, N, N, Y),
-      FCVT_L_H -> List(N, N, Y, N, N, N, X, H, X2, N, Y, N, N, N, N, Y),
-      FCVT_LU_H -> List(N, N, Y, N, N, N, X, H, X2, N, Y, N, N, N, N, Y),
-      FCVT_S_H -> List(N, Y, Y, N, N, N, X, H, S, N, N, Y, N, N, N, Y),
-      FCVT_H_S -> List(N, Y, Y, N, N, N, X, S, H, N, N, Y, N, N, N, Y),
-      FEQ_H -> List(N, N, Y, Y, N, N, N, H, H, N, Y, N, N, N, N, Y),
-      FLT_H -> List(N, N, Y, Y, N, N, N, H, H, N, Y, N, N, N, N, Y),
-      FLE_H -> List(N, N, Y, Y, N, N, N, H, H, N, Y, N, N, N, N, Y),
-      FSGNJ_H -> List(N, Y, Y, Y, N, N, N, H, H, N, N, Y, N, N, N, N),
-      FSGNJN_H -> List(N, Y, Y, Y, N, N, N, H, H, N, N, Y, N, N, N, N),
-      FSGNJX_H -> List(N, Y, Y, Y, N, N, N, H, H, N, N, Y, N, N, N, N),
-      FMIN_H -> List(N, Y, Y, Y, N, N, N, H, H, N, N, Y, N, N, N, Y),
-      FMAX_H -> List(N, Y, Y, Y, N, N, N, H, H, N, N, Y, N, N, N, Y),
-      FADD_H -> List(N, Y, Y, Y, N, N, Y, H, H, N, N, N, Y, N, N, Y),
-      FSUB_H -> List(N, Y, Y, Y, N, N, Y, H, H, N, N, N, Y, N, N, Y),
-      FMUL_H -> List(N, Y, Y, Y, N, N, N, H, H, N, N, N, Y, N, N, Y),
-      FMADD_H -> List(N, Y, Y, Y, Y, N, N, H, H, N, N, N, Y, N, N, Y),
-      FMSUB_H -> List(N, Y, Y, Y, Y, N, N, H, H, N, N, N, Y, N, N, Y),
-      FNMADD_H -> List(N, Y, Y, Y, Y, N, N, H, H, N, N, N, Y, N, N, Y),
-      FNMSUB_H -> List(N, Y, Y, Y, Y, N, N, H, H, N, N, N, Y, N, N, Y),
-      FDIV_H -> List(N, Y, Y, Y, N, N, N, H, H, N, N, N, N, Y, N, Y),
-      FSQRT_H -> List(N, Y, Y, N, N, N, X, H, H, N, N, N, N, N, Y, Y)
-    )
-  val f: Array[(BitPat, List[BitPat])] =
-    Array(
-      FLW -> List(Y, Y, N, N, N, X, X, X2, X2, N, N, N, N, N, N, N),
-      FSW -> List(Y, N, N, Y, N, Y, X, I, S, N, Y, N, N, N, N, N),
-      FMV_W_X -> List(N, Y, N, N, N, X, X, S, I, Y, N, N, N, N, N, N),
-      FCVT_S_W -> List(N, Y, N, N, N, X, X, S, S, Y, N, N, N, N, N, Y),
-      FCVT_S_WU -> List(N, Y, N, N, N, X, X, S, S, Y, N, N, N, N, N, Y),
-      FCVT_S_L -> List(N, Y, N, N, N, X, X, S, S, Y, N, N, N, N, N, Y),
-      FCVT_S_LU -> List(N, Y, N, N, N, X, X, S, S, Y, N, N, N, N, N, Y),
-      FMV_X_W -> List(N, N, Y, N, N, N, X, I, S, N, Y, N, N, N, N, N),
-      FCLASS_S -> List(N, N, Y, N, N, N, X, S, S, N, Y, N, N, N, N, N),
-      FCVT_W_S -> List(N, N, Y, N, N, N, X, S, X2, N, Y, N, N, N, N, Y),
-      FCVT_WU_S -> List(N, N, Y, N, N, N, X, S, X2, N, Y, N, N, N, N, Y),
-      FCVT_L_S -> List(N, N, Y, N, N, N, X, S, X2, N, Y, N, N, N, N, Y),
-      FCVT_LU_S -> List(N, N, Y, N, N, N, X, S, X2, N, Y, N, N, N, N, Y),
-      FEQ_S -> List(N, N, Y, Y, N, N, N, S, S, N, Y, N, N, N, N, Y),
-      FLT_S -> List(N, N, Y, Y, N, N, N, S, S, N, Y, N, N, N, N, Y),
-      FLE_S -> List(N, N, Y, Y, N, N, N, S, S, N, Y, N, N, N, N, Y),
-      FSGNJ_S -> List(N, Y, Y, Y, N, N, N, S, S, N, N, Y, N, N, N, N),
-      FSGNJN_S -> List(N, Y, Y, Y, N, N, N, S, S, N, N, Y, N, N, N, N),
-      FSGNJX_S -> List(N, Y, Y, Y, N, N, N, S, S, N, N, Y, N, N, N, N),
-      FMIN_S -> List(N, Y, Y, Y, N, N, N, S, S, N, N, Y, N, N, N, Y),
-      FMAX_S -> List(N, Y, Y, Y, N, N, N, S, S, N, N, Y, N, N, N, Y),
-      FADD_S -> List(N, Y, Y, Y, N, N, Y, S, S, N, N, N, Y, N, N, Y),
-      FSUB_S -> List(N, Y, Y, Y, N, N, Y, S, S, N, N, N, Y, N, N, Y),
-      FMUL_S -> List(N, Y, Y, Y, N, N, N, S, S, N, N, N, Y, N, N, Y),
-      FMADD_S -> List(N, Y, Y, Y, Y, N, N, S, S, N, N, N, Y, N, N, Y),
-      FMSUB_S -> List(N, Y, Y, Y, Y, N, N, S, S, N, N, N, Y, N, N, Y),
-      FNMADD_S -> List(N, Y, Y, Y, Y, N, N, S, S, N, N, N, Y, N, N, Y),
-      FNMSUB_S -> List(N, Y, Y, Y, Y, N, N, S, S, N, N, N, Y, N, N, Y),
-      FDIV_S -> List(N, Y, Y, Y, N, N, N, S, S, N, N, N, N, Y, N, Y),
-      FSQRT_S -> List(N, Y, Y, N, N, N, X, S, S, N, N, N, N, N, Y, Y)
-    )
-  val d: Array[(BitPat, List[BitPat])] =
-    Array(
-      FLD -> List(Y, Y, N, N, N, X, X, X2, X2, N, N, N, N, N, N, N),
-      FSD -> List(Y, N, N, Y, N, Y, X, I, D, N, Y, N, N, N, N, N),
-      FMV_D_X -> List(N, Y, N, N, N, X, X, D, I, Y, N, N, N, N, N, N),
-      FCVT_D_W -> List(N, Y, N, N, N, X, X, D, D, Y, N, N, N, N, N, Y),
-      FCVT_D_WU -> List(N, Y, N, N, N, X, X, D, D, Y, N, N, N, N, N, Y),
-      FCVT_D_L -> List(N, Y, N, N, N, X, X, D, D, Y, N, N, N, N, N, Y),
-      FCVT_D_LU -> List(N, Y, N, N, N, X, X, D, D, Y, N, N, N, N, N, Y),
-      FMV_X_D -> List(N, N, Y, N, N, N, X, I, D, N, Y, N, N, N, N, N),
-      FCLASS_D -> List(N, N, Y, N, N, N, X, D, D, N, Y, N, N, N, N, N),
-      FCVT_W_D -> List(N, N, Y, N, N, N, X, D, X2, N, Y, N, N, N, N, Y),
-      FCVT_WU_D -> List(N, N, Y, N, N, N, X, D, X2, N, Y, N, N, N, N, Y),
-      FCVT_L_D -> List(N, N, Y, N, N, N, X, D, X2, N, Y, N, N, N, N, Y),
-      FCVT_LU_D -> List(N, N, Y, N, N, N, X, D, X2, N, Y, N, N, N, N, Y),
-      FCVT_S_D -> List(N, Y, Y, N, N, N, X, D, S, N, N, Y, N, N, N, Y),
-      FCVT_D_S -> List(N, Y, Y, N, N, N, X, S, D, N, N, Y, N, N, N, Y),
-      FEQ_D -> List(N, N, Y, Y, N, N, N, D, D, N, Y, N, N, N, N, Y),
-      FLT_D -> List(N, N, Y, Y, N, N, N, D, D, N, Y, N, N, N, N, Y),
-      FLE_D -> List(N, N, Y, Y, N, N, N, D, D, N, Y, N, N, N, N, Y),
-      FSGNJ_D -> List(N, Y, Y, Y, N, N, N, D, D, N, N, Y, N, N, N, N),
-      FSGNJN_D -> List(N, Y, Y, Y, N, N, N, D, D, N, N, Y, N, N, N, N),
-      FSGNJX_D -> List(N, Y, Y, Y, N, N, N, D, D, N, N, Y, N, N, N, N),
-      FMIN_D -> List(N, Y, Y, Y, N, N, N, D, D, N, N, Y, N, N, N, Y),
-      FMAX_D -> List(N, Y, Y, Y, N, N, N, D, D, N, N, Y, N, N, N, Y),
-      FADD_D -> List(N, Y, Y, Y, N, N, Y, D, D, N, N, N, Y, N, N, Y),
-      FSUB_D -> List(N, Y, Y, Y, N, N, Y, D, D, N, N, N, Y, N, N, Y),
-      FMUL_D -> List(N, Y, Y, Y, N, N, N, D, D, N, N, N, Y, N, N, Y),
-      FMADD_D -> List(N, Y, Y, Y, Y, N, N, D, D, N, N, N, Y, N, N, Y),
-      FMSUB_D -> List(N, Y, Y, Y, Y, N, N, D, D, N, N, N, Y, N, N, Y),
-      FNMADD_D -> List(N, Y, Y, Y, Y, N, N, D, D, N, N, N, Y, N, N, Y),
-      FNMSUB_D -> List(N, Y, Y, Y, Y, N, N, D, D, N, N, N, Y, N, N, Y),
-      FDIV_D -> List(N, Y, Y, Y, N, N, N, D, D, N, N, N, N, Y, N, Y),
-      FSQRT_D -> List(N, Y, Y, N, N, N, X, D, D, N, N, N, N, N, Y, Y)
-    )
-  val fcvt_hd: Array[(BitPat, List[BitPat])] =
-    Array(
-      FCVT_H_D -> List(N, Y, Y, N, N, N, X, D, H, N, N, Y, N, N, N, Y),
-      FCVT_D_H -> List(N, Y, Y, N, N, N, X, H, D, N, N, Y, N, N, N, Y)
-    )
-
-  val insns = (parameter.minFLen, parameter.fLen) match {
-    case (32, 32) => f
-    case (16, 32) => h ++ f
-    case (32, 64) => f ++ d
-    case (16, 64) => h ++ f ++ d ++ fcvt_hd
-    case other =>
-      throw new Exception(s"minFLen = ${parameter.minFLen} & fLen = ${parameter.fLen} is an unsupported configuration")
-  }
-  val decoder = DecodeLogic(io.inst, default, insns)
-  val s = io.sigs
-  val sigs = Seq(
-    s.ldst,
-    s.wen,
-    s.ren1,
-    s.ren2,
-    s.ren3,
-    s.swap12,
-    s.swap23,
-    s.typeTagIn,
-    s.typeTagOut,
-    s.fromint,
-    s.toint,
-    s.fastpipe,
-    s.fma,
-    s.div,
-    s.sqrt,
-    s.wflags
-  )
-  sigs.zip(decoder).foreach { case (s, d) => s := d }
-}
 
 object FType {
   implicit def rwP: upickle.default.ReadWriter[FType] = upickle.default.macroRW[FType]
diff --git a/rocketv/src/RocketCore.scala b/rocketv/src/RocketCore.scala
index 609d3aefcf..1a22d2ba1d 100644
--- a/rocketv/src/RocketCore.scala
+++ b/rocketv/src/RocketCore.scala
@@ -252,7 +252,10 @@ case class RocketParameter(
   val decoderParameter = DecoderParameter(
     instructionSets,
     pipelinedMul,
-    flushOnFenceI
+    flushOnFenceI,
+    // todo: default = 16?
+    minFLen.getOrElse(16),
+    xLen
   )
   val iBufParameter: IBufParameter = IBufParameter(
     useAsyncReset,
@@ -366,6 +369,7 @@ class Rocket(val parameter: RocketParameter)
   override protected def implicitReset: Reset = io.reset
   val csr: Instance[CSR] = Instantiate(new CSR(parameter.csrParameter))
   val decoder: Instance[Decoder] = Instantiate(new Decoder(parameter.decoderParameter))
+  val fpuDecoder: Option[Instance[FPUDecoder]] = Option.when(usingFPU)(Instantiate(new FPUDecoder(parameter.decoderParameter)))
   val instructionBuffer: Instance[IBuf] = Instantiate(new IBuf(parameter.iBufParameter))
   val breakpointUnit: Instance[BreakpointUnit] = Instantiate(new BreakpointUnit(parameter.breakpointUnitParameter))
   val alu: Instance[ALU] = Instantiate(new ALU(parameter.aluParameter))
@@ -1364,6 +1368,8 @@ class Rocket(val parameter: RocketParameter)
     io.imem.ras_update := DontCare
 
     io.fpu.foreach { fpu =>
+      fpuDecoder.get.io.instruction := idInstruction
+      fpu.dec := fpuDecoder.get.io.output
       fpu.valid := !ctrlKilled && idDecodeOutput(parameter.decoderParameter.fp)
       fpu.killx := ctrlKillx
       fpu.killm := killmCommon