From b7d4b7a3f2108ed6b0db5dac547c14dbd823e621 Mon Sep 17 00:00:00 2001 From: Lucas-Wye Date: Sat, 3 Aug 2024 04:32:42 +0000 Subject: [PATCH] remove source2 --- t1/src/LaneZvbb.scala | 28 ++++++++++++++----------- t1/src/decoder/attribute/isSwrite.scala | 4 ++++ t1/src/decoder/attribute/isVtype.scala | 1 - 3 files changed, 20 insertions(+), 13 deletions(-) diff --git a/t1/src/LaneZvbb.scala b/t1/src/LaneZvbb.scala index cd332406c0..d7fd29b1e4 100644 --- a/t1/src/LaneZvbb.scala +++ b/t1/src/LaneZvbb.scala @@ -29,7 +29,6 @@ class LaneZvbbRequest(datapathWidth: Int) extends VFUPipeBundle { class LaneZvbbResponse(datapathWidth: Int) extends VFUPipeBundle { val data = UInt(datapathWidth.W) - val source2 = UInt(datapathWidth.W) } @instantiable @@ -114,20 +113,27 @@ class LaneZvbb(val parameter: LaneZvbbParam) zvbbROR32, )) - val zvbbSLL64_32 = (0.U((parameter.datapathWidth).W) ## zvbbSrc).asUInt << zvbbRs(5, 0) - val zvbbSLL64_16 = ((0.U(16.W) ## zvbbSrc16a).asUInt << zvbbRs16a(4, 0)).asUInt(31, 0) ## - ((0.U(16.W) ## zvbbSrc16b).asUInt << zvbbRs16b(4, 0)).asUInt(31, 0) - val zvbbSLL64_8 = ((0.U(8.W) ## zvbbSrc8a).asUInt << zvbbRs8a(3, 0)).asUInt(15, 0) ## - ((0.U(8.W) ## zvbbSrc8b).asUInt << zvbbRs8b(3, 0)).asUInt(15, 0) ## - ((0.U(8.W) ## zvbbSrc8c).asUInt << zvbbRs8c(3, 0)).asUInt(15, 0) ## - ((0.U(8.W) ## zvbbSrc8d).asUInt << zvbbRs8d(3, 0)).asUInt(15, 0) + // val zvbbSLL64_32 = ((0.U((parameter.datapathWidth).W) ## zvbbSrc).asUInt << zvbbRs(5, 0)).asUInt(63, 0) + // val zvbbSLL64_16 = ((0.U(16.W) ## zvbbSrc16a).asUInt << zvbbRs16a(4, 0)).asUInt(31, 0) ## + // ((0.U(16.W) ## zvbbSrc16b).asUInt << zvbbRs16b(4, 0)).asUInt(31, 0) + // val zvbbSLL64_8 = ((0.U(8.W) ## zvbbSrc8a).asUInt << zvbbRs8a(3, 0)).asUInt(15, 0) ## + // ((0.U(8.W) ## zvbbSrc8b).asUInt << zvbbRs8b(3, 0)).asUInt(15, 0) ## + // ((0.U(8.W) ## zvbbSrc8c).asUInt << zvbbRs8c(3, 0)).asUInt(15, 0) ## + // ((0.U(8.W) ## zvbbSrc8d).asUInt << zvbbRs8d(3, 0)).asUInt(15, 0) + val zvbbSLL64_32 = ((0.U((parameter.datapathWidth).W) ## zvbbSrc).asUInt << zvbbRs(5, 0)).asUInt(31, 0) + val zvbbSLL64_16 = ((0.U(16.W) ## zvbbSrc16a).asUInt << zvbbRs16a(4, 0)).asUInt(15, 0) ## + ((0.U(16.W) ## zvbbSrc16b).asUInt << zvbbRs16b(4, 0)).asUInt(15, 0) + val zvbbSLL64_8 = ((0.U(8.W) ## zvbbSrc8a).asUInt << zvbbRs8a(3, 0)).asUInt(7, 0) ## + ((0.U(8.W) ## zvbbSrc8b).asUInt << zvbbRs8b(3, 0)).asUInt(7, 0) ## + ((0.U(8.W) ## zvbbSrc8c).asUInt << zvbbRs8c(3, 0)).asUInt(7, 0) ## + ((0.U(8.W) ## zvbbSrc8d).asUInt << zvbbRs8d(3, 0)).asUInt(7, 0) val zvbbSLL64 = Mux1H(vSew, Seq( zvbbSLL64_8, zvbbSLL64_16, zvbbSLL64_32, )) val zvbbSLL = zvbbSLL64(parameter.datapathWidth-1, 0) - val zvbbSLLMSB = zvbbSLL64(2*parameter.datapathWidth-1, parameter.datapathWidth) + // val zvbbSLLMSB = zvbbSLL64(2*parameter.datapathWidth-1, parameter.datapathWidth) val zvbbANDN = zvbbSrc & (~zvbbRs) @@ -141,8 +147,6 @@ class LaneZvbb(val parameter: LaneZvbbParam) zvbbROR, zvbbSLL, zvbbANDN, - ) - ) - response.source2 := Mux(request.opcode === 7.U, zvbbSLLMSB, 0.U) + )) } diff --git a/t1/src/decoder/attribute/isSwrite.scala b/t1/src/decoder/attribute/isSwrite.scala index 01325fe1f8..f16f28e5d5 100644 --- a/t1/src/decoder/attribute/isSwrite.scala +++ b/t1/src/decoder/attribute/isSwrite.scala @@ -210,6 +210,10 @@ object isSwrite { "vzext.vf2", "vzext.vf4", "vzext.vf8", + // rv_zvbb + "vwsll.vv", + "vwsll.vx", + "vwsll.vi", ) allMatched.contains(t1DecodePattern.instruction.name) } diff --git a/t1/src/decoder/attribute/isVtype.scala b/t1/src/decoder/attribute/isVtype.scala index 708b3f4187..7649d715a2 100644 --- a/t1/src/decoder/attribute/isVtype.scala +++ b/t1/src/decoder/attribute/isVtype.scala @@ -186,7 +186,6 @@ object isVtype { "vrol.vv", "vror.vv", "vwsll.vv", - "vwsll.vv", ) allMatched.contains(t1DecodePattern.instruction.name) }