From 9f4bad704514481e17e0daa76b010fd9c278dc37 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Mon, 14 Oct 2024 10:53:28 +0800 Subject: [PATCH] [configs] new configs --- ...org.chipsalliance.t1.elaborator.t1.T1.toml | 78 +++++++++++++++++-- ...lliance.t1.elaborator.t1emu.Testbench.toml | 10 +-- ...1.elaborator.t1rocketemu.T1RocketTile.toml | 6 +- ....t1.elaborator.t1rocketv.T1RocketTile.toml | 69 +++++++++++++++- 4 files changed, 146 insertions(+), 17 deletions(-) diff --git a/designs/org.chipsalliance.t1.elaborator.t1.T1.toml b/designs/org.chipsalliance.t1.elaborator.t1.T1.toml index fb43bf724..744b599c3 100644 --- a/designs/org.chipsalliance.t1.elaborator.t1.T1.toml +++ b/designs/org.chipsalliance.t1.elaborator.t1.T1.toml @@ -1,8 +1,74 @@ +# TestChips +[rookidee] +cmdopt = "--dLen 128 --extensions zvl512b --extensions zve32x --vrfBankSize 2 --vrfRamType p0rp1w --vfuInstantiateParameter small" [blastoise] cmdopt = "--dLen 256 --extensions zvl512b --extensions zve32f --vrfBankSize 1 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" -[machamp] -cmdopt = "--dLen 512 --extensions zvl1024b --extensions zve32x --vrfBankSize 2 --vrfRamType p0rp1w --vfuInstantiateParameter small" -[psyduck] -cmdopt = "--dLen 256 --extensions zvl512b --extensions zve32f --extensions zvbb --vrfBankSize 1 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" -[sandslash] -cmdopt = "--dLen 1024 --extensions zvl4096b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter small" + +# Physcial Design Benchmark +## VLEN from 128 to 64K +[physical_design_case_0] +cmdopt = "--dLen 128 --extensions zvl128b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_1] +cmdopt = "--dLen 128 --extensions zvl256b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_2] +cmdopt = "--dLen 128 --extensions zvl512b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_3] +cmdopt = "--dLen 128 --extensions zvl1024b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_4] +cmdopt = "--dLen 128 --extensions zvl2048b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_5] +cmdopt = "--dLen 128 --extensions zvl4096b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_6] +cmdopt = "--dLen 128 --extensions zvl8192b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_7] +cmdopt = "--dLen 128 --extensions zvl16384b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_8] +cmdopt = "--dLen 128 --extensions zvl32768b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_9] +cmdopt = "--dLen 128 --extensions zvl65536b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +## 4 8 16 32 Lanes floorplan and extra size by Permutation Unit +[physical_design_case_10] +cmdopt = "--dLen 128 --extensions zvl2048b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_11] +cmdopt = "--dLen 256 --extensions zvl2048b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_12] +cmdopt = "--dLen 512 --extensions zvl2048b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_13] +cmdopt = "--dLen 1024 --extensions zvl2048b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +## Lane with different VRF bank size +[physical_design_case_14] +cmdopt = "--dLen 128 --extensions zvl4096b --extensions zve32x --vrfBankSize 1 --vrfRamType p0rw --vfuInstantiateParameter small" +[physical_design_case_15] +cmdopt = "--dLen 128 --extensions zvl4096b --extensions zve32x --vrfBankSize 2 --vrfRamType p0rw --vfuInstantiateParameter small" +[physical_design_case_16] +cmdopt = "--dLen 128 --extensions zvl4096b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter small" +[physical_design_case_17] +cmdopt = "--dLen 128 --extensions zvl4096b --extensions zve32x --vrfBankSize 8 --vrfRamType p0rw --vfuInstantiateParameter small" +[physical_design_case_18] +cmdopt = "--dLen 128 --extensions zvl4096b --extensions zve32x --vrfBankSize 16 --vrfRamType p0rw --vfuInstantiateParameter small" +## Lane with different VRF RAM Type +[physical_design_case_19] +cmdopt = "--dLen 128 --extensions zvl4096b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter small" +[physical_design_case_20] +cmdopt = "--dLen 128 --extensions zvl4096b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rp1w --vfuInstantiateParameter small" +[physical_design_case_21] +cmdopt = "--dLen 128 --extensions zvl4096b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" +## Lane with different VFU +[physical_design_case_22] +cmdopt = "--dLen 128 --extensions zvl512b --extensions zve32x --vrfBankSize 1 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_23] +cmdopt = "--dLen 128 --extensions zvl512b --extensions zve32x --vrfBankSize 1 --vrfRamType p0rw --vfuInstantiateParameter small" +[physical_design_case_24] +cmdopt = "--dLen 128 --extensions zvl512b --extensions zve32f --vrfBankSize 1 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_25] +cmdopt = "--dLen 128 --extensions zvl512b --extensions zve32f --vrfBankSize 1 --vrfRamType p0rw --vfuInstantiateParameter small" +[physical_design_case_26] +cmdopt = "--dLen 128 --extensions zvl512b --extensions zve32f --vrfBankSize 1 --vrfRamType p0rw --vfuInstantiateParameter medium" +[physical_design_case_27] +cmdopt = "--dLen 128 --extensions zvl512b --extensions zve32f --vrfBankSize 1 --vrfRamType p0rw --vfuInstantiateParameter large" +[physical_design_case_28] +cmdopt = "--dLen 128 --extensions zvl512b --extensions zve32f --vrfBankSize 1 --vrfRamType p0rw --vfuInstantiateParameter huge" + +# Experimental(only for elaboration) +[experimental_0] +cmdopt = "--dLen 256 --extensions zvl256b --extensions zve32x --extensions zvbb --vrfBankSize 1 --vrfRamType p0rwp1rw --vfuInstantiateParameter zvbb" diff --git a/designs/org.chipsalliance.t1.elaborator.t1emu.Testbench.toml b/designs/org.chipsalliance.t1.elaborator.t1emu.Testbench.toml index fb43bf724..c4ecc2ff8 100644 --- a/designs/org.chipsalliance.t1.elaborator.t1emu.Testbench.toml +++ b/designs/org.chipsalliance.t1.elaborator.t1emu.Testbench.toml @@ -1,8 +1,4 @@ +[rookidee] +cmdopt = "--dLen 128 --extensions zvl512b --extensions zve32x --vrfBankSize 2 --vrfRamType p0rp1w --vfuInstantiateParameter small" [blastoise] -cmdopt = "--dLen 256 --extensions zvl512b --extensions zve32f --vrfBankSize 1 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" -[machamp] -cmdopt = "--dLen 512 --extensions zvl1024b --extensions zve32x --vrfBankSize 2 --vrfRamType p0rp1w --vfuInstantiateParameter small" -[psyduck] -cmdopt = "--dLen 256 --extensions zvl512b --extensions zve32f --extensions zvbb --vrfBankSize 1 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" -[sandslash] -cmdopt = "--dLen 1024 --extensions zvl4096b --extensions zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter small" +cmdopt = "--dLen 256 --extensions zvl512b --extensions zve32f --vrfBankSize 2 --vrfRamType p0rp1w --vfuInstantiateParameter small" diff --git a/designs/org.chipsalliance.t1.elaborator.t1rocketemu.T1RocketTile.toml b/designs/org.chipsalliance.t1.elaborator.t1rocketemu.T1RocketTile.toml index 9aaa75f46..8ff9acb85 100644 --- a/designs/org.chipsalliance.t1.elaborator.t1rocketemu.T1RocketTile.toml +++ b/designs/org.chipsalliance.t1.elaborator.t1rocketemu.T1RocketTile.toml @@ -1,2 +1,4 @@ -[t1rocket] -cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_f --instructionSets rv_v --instructionSets zve32f --instructionSets zvl1024b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 2 --vrfRamType p0rp1w --vfuInstantiateParameter small" +[rookidee] +cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --instructionSets zve32x --instructionSets zvl512b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 1 --vrfRamType p0rp1w --vfuInstantiateParameter small" +[blastoise] +cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_f --instructionSets rv_v --instructionSets zve32f --instructionSets zvl512b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 2 --vrfRamType p0rp1w --vfuInstantiateParameter small" diff --git a/designs/org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile.toml b/designs/org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile.toml index 9aaa75f46..64c23849a 100644 --- a/designs/org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile.toml +++ b/designs/org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile.toml @@ -1,2 +1,67 @@ -[t1rocket] -cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_f --instructionSets rv_v --instructionSets zve32f --instructionSets zvl1024b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 2 --vrfRamType p0rp1w --vfuInstantiateParameter small" +[rookidee] +cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --instructionSets zve32x --instructionSets zvl512b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 1 --vrfRamType p0rp1w --vfuInstantiateParameter small" +[blastoise] +cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_f --instructionSets rv_v --instructionSets zve32f --instructionSets zvl512b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 2 --vrfRamType p0rp1w --vfuInstantiateParameter small" + +[physical_design_case_0] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl128b --instructionSets zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_1] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl256b --instructionSets zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_2] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl512b --instructionSets zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_3] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl1024b --instructionSets zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_4] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl2048b --instructionSets zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_5] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl4096b --instructionSets zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_6] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl8192b --instructionSets zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_7] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl16384b --instructionSets zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_8] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl32768b --instructionSets zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_9] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl65536b --instructionSets zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +## 4 8 16 32 Lanes floorplan and extra size by Permutation Unit +[physical_design_case_10] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl2048b --instructionSets zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_11] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --instructionSets zvl2048b --instructionSets zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_12] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 512 --instructionSets zvl2048b --instructionSets zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_13] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 1024 --instructionSets zvl2048b --instructionSets zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter minimal" +## Lane with different VRF bank size +[physical_design_case_14] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl4096b --instructionSets zve32x --vrfBankSize 1 --vrfRamType p0rw --vfuInstantiateParameter small" +[physical_design_case_15] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl4096b --instructionSets zve32x --vrfBankSize 2 --vrfRamType p0rw --vfuInstantiateParameter small" +[physical_design_case_16] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl4096b --instructionSets zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter small" +[physical_design_case_17] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl4096b --instructionSets zve32x --vrfBankSize 8 --vrfRamType p0rw --vfuInstantiateParameter small" +[physical_design_case_18] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl4096b --instructionSets zve32x --vrfBankSize 16 --vrfRamType p0rw --vfuInstantiateParameter small" +## Lane with different VRF RAM Type +[physical_design_case_19] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl4096b --instructionSets zve32x --vrfBankSize 4 --vrfRamType p0rw --vfuInstantiateParameter small" +[physical_design_case_20] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl4096b --instructionSets zve32x --vrfBankSize 4 --vrfRamType p0rp1w --vfuInstantiateParameter small" +[physical_design_case_21] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl4096b --instructionSets zve32x --vrfBankSize 4 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" +## Lane with different VFU +[physical_design_case_22] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl512b --instructionSets zve32x --vrfBankSize 1 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_23] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl512b --instructionSets zve32x --vrfBankSize 1 --vrfRamType p0rw --vfuInstantiateParameter small" +[physical_design_case_24] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl512b --instructionSets zve32f --vrfBankSize 1 --vrfRamType p0rw --vfuInstantiateParameter minimal" +[physical_design_case_25] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl512b --instructionSets zve32f --vrfBankSize 1 --vrfRamType p0rw --vfuInstantiateParameter small" +[physical_design_case_26] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl512b --instructionSets zve32f --vrfBankSize 1 --vrfRamType p0rw --vfuInstantiateParameter medium" +[physical_design_case_27] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl512b --instructionSets zve32f --vrfBankSize 1 --vrfRamType p0rw --vfuInstantiateParameter large" +[physical_design_case_28] +cmdopt = "--instructionSets rv32_i --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --instructionSets zvl512b --instructionSets zve32f --vrfBankSize 1 --vrfRamType p0rw --vfuInstantiateParameter huge"