From 930814d434bb8a8819c0a20f293a91839a634352 Mon Sep 17 00:00:00 2001
From: Jiuyang Liu <liu@jiuyang.me>
Date: Tue, 13 Aug 2024 16:35:11 +0800
Subject: [PATCH] [om] add VRF SRAMOM

---
 t1/src/Lane.scala    |  6 ++++++
 t1/src/vrf/VRF.scala | 19 ++++++++++++++++++-
 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
index 59a7eb8a6..be876ebc5 100644
--- a/t1/src/Lane.scala
+++ b/t1/src/Lane.scala
@@ -25,6 +25,11 @@ class LaneOM extends Class {
   @public
   val vfusIn = IO(Input(Property[Seq[AnyClassType]]()))
   vfus := vfusIn
+  @public
+  val vrf = IO(Output(Property[AnyClassType]()))
+  @public
+  val vrfIn = IO(Input(Property[AnyClassType]()))
+  vrf := vrfIn
 }
 
 class LaneSlotProbe(instructionIndexBits: Int) extends Bundle {
@@ -323,6 +328,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
 
   /** VRF instantces. */
   val vrf: Instance[VRF] = Instantiate(new VRF(parameter.vrfParam))
+  omInstance.vrfIn := Property(vrf.om.asAnyClassType)
 
   /** TODO: review later
     */
diff --git a/t1/src/vrf/VRF.scala b/t1/src/vrf/VRF.scala
index 724ef6372..9a8e902c2 100644
--- a/t1/src/vrf/VRF.scala
+++ b/t1/src/vrf/VRF.scala
@@ -4,9 +4,10 @@
 package org.chipsalliance.t1.rtl.vrf
 
 import chisel3._
-import chisel3.experimental.hierarchy.{Instantiate, instantiable, public}
+import chisel3.experimental.hierarchy.{Instance, Instantiate, instantiable, public}
 import chisel3.experimental.{SerializableModule, SerializableModuleParameter}
 import chisel3.probe.{Probe, ProbeValue, define}
+import chisel3.properties.{AnyClassType, Class, ClassType, Property}
 import chisel3.util._
 import org.chipsalliance.t1.rtl.{LSUWriteCheck, VRFReadPipe, VRFReadRequest, VRFWriteReport, VRFWriteRequest, ffo, instIndexL, instIndexLE, ohCheck}
 
@@ -28,6 +29,16 @@ object VRFParam {
   implicit val rwP: upickle.default.ReadWriter[VRFParam] = upickle.default.macroRW
 }
 
+
+@instantiable
+class VRFOM extends Class {
+  @public
+  val vrfSRAMOM = IO(Output(Property[Seq[AnyClassType]]()))
+  @public
+  val vrfSRAMOMIn = IO(Input(Property[Seq[AnyClassType]]()))
+  vrfSRAMOM := vrfSRAMOMIn
+}
+
 /** Parameter for [[Lane]].
   * @param vLen VLEN
   * @param laneNumber how many lanes in the vector processor
@@ -127,6 +138,11 @@ class VRFProbe(parameter: VRFParam) extends Bundle {
   */
 @instantiable
 class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFParam] {
+  val omInstance: Instance[VRFOM] = Instantiate(new VRFOM)
+  val omType: ClassType = omInstance.toDefinition.getClassType
+  @public
+  val om: Property[ClassType] = IO(Output(Property[omType.Type]()))
+  om := omInstance.getPropertyReference
 
   /** VRF read requests
     * ready will couple from valid from [[readRequests]],
@@ -434,6 +450,7 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
 
     rf
   }
+  omInstance.vrfSRAMOMIn := Property(rfVec.map(_.om.asAnyClassType))
 
   val initRecord: ValidIO[VRFWriteReport] = WireDefault(0.U.asTypeOf(Valid(new VRFWriteReport(parameter))))
   initRecord.valid := true.B