From 868b317d02927d87a5adee2bbf5a75ed6928e791 Mon Sep 17 00:00:00 2001 From: qinjun-li Date: Thu, 17 Oct 2024 18:29:47 +0800 Subject: [PATCH] [tests] fix lsu write probe. --- t1/src/lsu/LSU.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/t1/src/lsu/LSU.scala b/t1/src/lsu/LSU.scala index 5dc10c7e2..d5cd1f2a6 100644 --- a/t1/src/lsu/LSU.scala +++ b/t1/src/lsu/LSU.scala @@ -283,7 +283,7 @@ class LSU(param: LSUParameter) extends Module { probeWire.slots(index).dataMask := write.io.enq.bits.data.mask probeWire.slots(index).dataData := write.io.enq.bits.data.data probeWire.slots(index).dataInstruction := write.io.enq.bits.data.instructionIndex - probeWire.slots(index).writeValid := write.io.enq.valid + probeWire.slots(index).writeValid := write.io.enq.fire probeWire.slots(index).targetLane := OHToUInt(write.io.enq.bits.targetLane) } probeWire.reqEnq := reqEnq.asUInt