diff --git a/t1rocketemu/src/TestBench.scala b/t1rocketemu/src/TestBench.scala
index f76e245ba..9de28786a 100644
--- a/t1rocketemu/src/TestBench.scala
+++ b/t1rocketemu/src/TestBench.scala
@@ -11,6 +11,7 @@ import chisel3.util.{HasExtModuleInline, Mux1H, PopCount, Queue, UIntToOH, Valid
 import org.chipsalliance.amba.axi4.bundle._
 import org.chipsalliance.t1.t1rocketemu.dpi._
 import org.chipsalliance.t1.tile.{T1RocketTile, T1RocketTileParameter}
+import org.chipsalliance.t1.rtl.T1Probe
 
 class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTileParameter])
     extends RawModule
@@ -326,4 +327,11 @@ class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTil
   when(quitFlag && t1Probe.idle && rocketProbe.idle) {
     stop(cf"""{"event":"SimulationEnd", "cycle":${simulationTime}}\n""")
   }
+
+  val profData = Module(new Module {
+    override def desiredName: String = "ProfData"
+    val probe = IO(Input(new T1Probe(generator.parameter.t1Parameter)))
+    dontTouch(probe)
+  })
+  profData.probe := t1Probe
 }