From 7daad5b4b13b17d48d92f0d4a7976e080ad9c06a Mon Sep 17 00:00:00 2001 From: Lucas-Wye Date: Fri, 2 Aug 2024 06:58:03 +0000 Subject: [PATCH] fix vs1 and vs2 error --- t1/src/LaneZvbb.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/t1/src/LaneZvbb.scala b/t1/src/LaneZvbb.scala index 611986746..8d38d88dc 100644 --- a/t1/src/LaneZvbb.scala +++ b/t1/src/LaneZvbb.scala @@ -37,8 +37,8 @@ class LaneZvbb(val parameter: LaneZvbbParam) val response: LaneZvbbResponse = Wire(new LaneZvbbResponse(parameter.datapathWidth)) val request : LaneZvbbRequest = connectIO(response).asTypeOf(parameter.inputBundle) - val zvbbSrc: UInt = request.src(0) // vs2 - val zvbbRs: UInt = request.src(1) // vs1 or rs1 + val zvbbSrc: UInt = request.src(1) // vs1 or rs1 + val zvbbRs: UInt = request.src(0) // vs2 val zvbbBRev = VecInit(zvbbSrc(parameter.datapathWidth-1, 0).asBools.reverse).asUInt // element's bit reverse val zvbbBRev8 = VecInit(zvbbSrc(parameter.datapathWidth-1, 0).asBools.grouped(8).map(s => VecInit(s.reverse)).toSeq).asUInt // byte's bit reverse