From 695b32dc09e1e43bbf9b57d6408163f6be03d1f4 Mon Sep 17 00:00:00 2001
From: qinjun-li <liqinjun1994@gmail.com>
Date: Sun, 25 Aug 2024 01:06:38 +0800
Subject: [PATCH] [rocketv] fix vxrm write.

---
 rocketv/src/CSR.scala | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/rocketv/src/CSR.scala b/rocketv/src/CSR.scala
index af5bbfae1..e122aace8 100644
--- a/rocketv/src/CSR.scala
+++ b/rocketv/src/CSR.scala
@@ -1320,7 +1320,10 @@ class CSR(val parameter: CSRParameter)
   }
 
   val setVlReadData: UInt = Wire(UInt(xLen.W))
-  io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v).asUInt | setVlReadData
+  val cseReadData: UInt = Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v).asUInt
+  io.rw.rdata := io.vectorCsr.map(s =>
+    Mux(s, setVlReadData, cseReadData)
+  ).getOrElse(cseReadData)
 
   // cover access to register
   val coverable_counters = read_mapping.filterNot {
@@ -1733,6 +1736,12 @@ class CSR(val parameter: CSRParameter)
         vector.get.states("vill") := true.B
       }
     }
+    // v csr write
+    when(csr_wen) {
+      when(decoded_addr(CSRs.vxrm)) {
+        vector.get.states("vxrm") := wdata
+      }
+    }
   } else {
     setVlReadData := 0.U
   }