From 571b2abc77d5ea5fdcb50373adb1323bf5de4ce5 Mon Sep 17 00:00:00 2001
From: qinjun-li <liqinjun1994@gmail.com>
Date: Mon, 11 Nov 2024 12:52:14 +0800
Subject: [PATCH] [rtl] fix index unit.

---
 t1/src/lsu/SimpleAccessUnit.scala | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/t1/src/lsu/SimpleAccessUnit.scala b/t1/src/lsu/SimpleAccessUnit.scala
index 3ba429f98..53497e833 100644
--- a/t1/src/lsu/SimpleAccessUnit.scala
+++ b/t1/src/lsu/SimpleAccessUnit.scala
@@ -197,12 +197,19 @@ class SimpleAccessUnit(param: MSHRParam) extends Module with LSUPublic {
   val offsetRelease: Vec[Bool] = IO(Output(Vec(param.laneNumber, Bool())))
 
   val requestOffset:  Bool               = Wire(Bool())
+  val stateIdle: Bool = Wire(Bool())
+  val waitQueueDeq: Vec[Bool] = Wire(Vec(param.laneNumber, Bool()))
   val offsetQueueVec: Seq[QueueIO[UInt]] = offsetReadResult.zipWithIndex.map { case (req, index) =>
     val queue: QueueIO[UInt] = Queue.io(chiselTypeOf(req.bits), param.maskRequestQueueSize)
+    val deqLock: Bool = RegInit(false.B)
+    waitQueueDeq(index) := deqLock
+    when(lsuRequest.valid || requestOffset || queue.deq.fire) {
+      deqLock := queue.deq.fire
+    }
     offsetRelease(index) := queue.deq.fire
     queue.enq.valid      := req.valid
     queue.enq.bits       := req.bits
-    queue.deq.ready      := requestOffset
+    queue.deq.ready      := !deqLock || stateIdle
     queue
   }
 
@@ -601,7 +608,7 @@ class SimpleAccessUnit(param: MSHRParam) extends Module with LSUPublic {
           indexedInstructionOffsetExhausted
       ) ||
         // change offset group
-        requestOffset ||
+        (requestOffset && waitQueueDeq.asUInt.andR) ||
         // change mask group
         // TODO: remove [[maskNeedUpdate]]?
         maskGroupEndAndRequestNewMask
@@ -670,7 +677,7 @@ class SimpleAccessUnit(param: MSHRParam) extends Module with LSUPublic {
   // state === idle: All the remaining elements are removed by the mask,
   // but there is still offset left.
   /** signal to request offset in the pipeline, only assert for one cycle. */
-  requestOffset := stateIsRequest && maskCheck && !indexCheck && fofCheck || state === idle
+  requestOffset := stateIsRequest && maskCheck && !indexCheck && fofCheck
 
   val s0DequeueFire: Bool = Wire(Bool())
 
@@ -968,7 +975,7 @@ class SimpleAccessUnit(param: MSHRParam) extends Module with LSUPublic {
   status.instructionIndex := lsuRequestReg.instructionIndex
 
   /** the current state is idle. */
-  val stateIdle = state === idle
+  stateIdle := state === idle
   status.idle              := stateIdle
   status.last              := (!RegNext(stateIdle) && stateIdle) || invalidInstructionNext || allElementsMasked
   status.changeMaskGroup   := updateOffsetGroupEnable