From 24d368b50f9cf2145ab7e0de4957a0ab6516dd7f Mon Sep 17 00:00:00 2001 From: qinjun-li Date: Thu, 26 Sep 2024 19:59:28 +0800 Subject: [PATCH] [tests] Distinguish between vector write and vector commit. --- rocketv/src/RocketCore.scala | 28 +++++++++++++++------------- t1rocketemu/src/TestBench.scala | 6 +++--- 2 files changed, 18 insertions(+), 16 deletions(-) diff --git a/rocketv/src/RocketCore.scala b/rocketv/src/RocketCore.scala index 67e95ea1f..52ac45afe 100644 --- a/rocketv/src/RocketCore.scala +++ b/rocketv/src/RocketCore.scala @@ -39,16 +39,17 @@ class FPUScoreboardProbe extends Bundle { } class RocketProbe(param: RocketParameter) extends Bundle { - val rfWen: Bool = Bool() - val rfWaddr: UInt = UInt(param.lgNXRegs.W) - val rfWdata: UInt = UInt(param.xLen.W) + val rfWen: Bool = Bool() + val rfWaddr: UInt = UInt(param.lgNXRegs.W) + val rfWdata: UInt = UInt(param.xLen.W) // rocket is idle - val waitWen: Bool = new Bool() - val waitWaddr: UInt = UInt(param.lgNXRegs.W) - val isVector: Bool = Bool() - val idle: Bool = Bool() + val waitWen: Bool = new Bool() + val waitWaddr: UInt = UInt(param.lgNXRegs.W) + val isVectorCommit: Bool = Bool() + val isVectorWrite: Bool = Bool() + val idle: Bool = Bool() // fpu score board - val fpuScoreboard: Option[FPUScoreboardProbe] = Option.when(param.usingFPU)(new FPUScoreboardProbe) + val fpuScoreboard: Option[FPUScoreboardProbe] = Option.when(param.usingFPU)(new FPUScoreboardProbe) } object RocketParameter { @@ -1616,14 +1617,15 @@ class Rocket(val parameter: RocketParameter) probeWire.rfWaddr := rfWaddr probeWire.rfWdata := rfWdata - probeWire.waitWen := wbSetSboard && wbWen - probeWire.waitWaddr := wbWaddr + probeWire.waitWen := wbSetSboard && wbWen + probeWire.waitWaddr := wbWaddr // vector commit || vector write rd - probeWire.isVector := io.t1.map { t1 => + probeWire.isVectorCommit := io.t1.map { t1 => wbRegValid && wbRegDecodeOutput(parameter.decoderParameter.vector) && !wbRegDecodeOutput(parameter.decoderParameter.vectorCSR) - }.getOrElse(false.B) || t1RetireQueue.map(q => q.io.deq.fire).getOrElse(false.B) - probeWire.idle := vectorEmpty + }.getOrElse(false.B) + probeWire.isVectorWrite := t1RetireQueue.map(q => q.io.deq.fire).getOrElse(false.B) + probeWire.idle := vectorEmpty probeWire.fpuScoreboard.foreach { case fpProbe => fpProbe.memSetScoreBoard := wbValid && wbDcacheMiss && wbRegDecodeOutput(parameter.decoderParameter.wfd) diff --git a/t1rocketemu/src/TestBench.scala b/t1rocketemu/src/TestBench.scala index f76e245ba..80de5d128 100644 --- a/t1rocketemu/src/TestBench.scala +++ b/t1rocketemu/src/TestBench.scala @@ -189,13 +189,13 @@ class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTil // output the probes // rocket reg write - when(rocketProbe.rfWen && !rocketProbe.isVector && rocketProbe.rfWaddr =/= 0.U && !(rocketProbe.waitWen && rocketProbe.waitWaddr =/= 0.U))( + when(rocketProbe.rfWen && !rocketProbe.isVectorWrite && rocketProbe.rfWaddr =/= 0.U && !(rocketProbe.waitWen && rocketProbe.waitWaddr =/= 0.U))( printf( cf"""{"event":"RegWrite","idx":${rocketProbe.rfWaddr},"data":"${rocketProbe.rfWdata}%x","cycle":${simulationTime}}\n""" ) ) - when(rocketProbe.waitWen && !rocketProbe.isVector && rocketProbe.waitWaddr =/= 0.U)( + when(rocketProbe.waitWen && !rocketProbe.isVectorCommit && rocketProbe.waitWaddr =/= 0.U)( printf( cf"""{"event":"RegWriteWait","idx":${rocketProbe.waitWaddr},"cycle":${simulationTime}}\n""" ) @@ -210,7 +210,7 @@ class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTil fpuParameter.fLen, fpuParameter.minFLen ))) - val isVectorForLLWrite = RegNext(rocketProbe.isVector, false.B) + val isVectorForLLWrite = RegNext(rocketProbe.isVectorWrite, false.B) fpToIEEE.io.clock := clock fpToIEEE.io.reset := reset