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[ci] update test case cycle data
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github-actions authored and sequencer committed Jul 30, 2024
1 parent 149f911 commit 1eb32c4
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Showing 3 changed files with 38 additions and 38 deletions.
24 changes: 12 additions & 12 deletions .github/cases/blastoise/default.json
Original file line number Diff line number Diff line change
Expand Up @@ -273,9 +273,9 @@
"codegen.vse16_v": 4013,
"codegen.vse32_v": 3403,
"codegen.vse8_v": 4623,
"codegen.vsetivli": 469,
"codegen.vsetvl": 469,
"codegen.vsetvli": 469,
"codegen.vsetivli": 468,
"codegen.vsetvl": 468,
"codegen.vsetvli": 468,
"codegen.vsext_vf2": 23212,
"codegen.vsext_vf4": 4241,
"codegen.vslide1down_vx": 866515,
Expand Down Expand Up @@ -499,15 +499,15 @@
"codegen.vfredusum_vs": 122332,
"codegen.vfredmax_vs": 122332,
"codegen.vfredmin_vs": 122332,
"rvv_bench.ascii_to_utf16": 1583519,
"rvv_bench.ascii_to_utf32": 704038,
"rvv_bench.ascii_to_utf16": 1583627,
"rvv_bench.ascii_to_utf32": 704056,
"rvv_bench.byteswap": 3353190,
"rvv_bench.chacha20": 2,
"rvv_bench.chacha20": 3,
"rvv_bench.mandelbrot": 4056017,
"rvv_bench.memcpy": 2072895,
"rvv_bench.memset": 438920,
"rvv_bench.mergelines": 3347920,
"rvv_bench.poly1305": 2,
"rvv_bench.strlen": 877645,
"rvv_bench.utf8_count": 6339104
"rvv_bench.memcpy": 2103216,
"rvv_bench.memset": 438703,
"rvv_bench.mergelines": 3351737,
"rvv_bench.poly1305": 3,
"rvv_bench.strlen": 877754,
"rvv_bench.utf8_count": 6340467
}
26 changes: 13 additions & 13 deletions .github/cases/machamp/default.json
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
{
"mlir.rvv_vp_intrinsic_add": 422,
"mlir.rvv_vp_intrinsic_add_scalable": 575,
"mlir.rvv_vp_intrinsic_add_scalable": 576,
"mlir.hello": 113,
"mlir.stripmining": 13447,
"asm.mmm": 91467,
Expand Down Expand Up @@ -271,9 +271,9 @@
"codegen.vse16_v": 3981,
"codegen.vse32_v": 3371,
"codegen.vse8_v": 4591,
"codegen.vsetivli": 437,
"codegen.vsetvl": 437,
"codegen.vsetvli": 437,
"codegen.vsetivli": 436,
"codegen.vsetvl": 436,
"codegen.vsetvli": 436,
"codegen.vsext_vf2": 39423,
"codegen.vsext_vf4": 6444,
"codegen.vslide1down_vx": 1631043,
Expand Down Expand Up @@ -435,14 +435,14 @@
"codegen.vxor_vx": 63114,
"codegen.vzext_vf2": 39423,
"codegen.vzext_vf4": 6444,
"rvv_bench.ascii_to_utf16": 1460027,
"rvv_bench.ascii_to_utf32": 631198,
"rvv_bench.ascii_to_utf16": 1460089,
"rvv_bench.ascii_to_utf32": 631174,
"rvv_bench.byteswap": 3259012,
"rvv_bench.chacha20": 2,
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"rvv_bench.memset": 244393,
"rvv_bench.mergelines": 3170081,
"rvv_bench.poly1305": 2,
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"rvv_bench.utf8_count": 5727933
"rvv_bench.chacha20": 3,
"rvv_bench.memcpy": 1846662,
"rvv_bench.memset": 244374,
"rvv_bench.mergelines": 3145593,
"rvv_bench.poly1305": 3,
"rvv_bench.strlen": 710137,
"rvv_bench.utf8_count": 5729458
}
26 changes: 13 additions & 13 deletions .github/cases/sandslash/default.json
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
{
"mlir.rvv_vp_intrinsic_add": 428,
"mlir.rvv_vp_intrinsic_add_scalable": 648,
"mlir.rvv_vp_intrinsic_add_scalable": 649,
"mlir.hello": 115,
"mlir.stripmining": 3598,
"asm.mmm": 91467,
Expand Down Expand Up @@ -271,9 +271,9 @@
"codegen.vse16_v": 5523,
"codegen.vse32_v": 4817,
"codegen.vse8_v": 6229,
"codegen.vsetivli": 821,
"codegen.vsetvl": 821,
"codegen.vsetvli": 821,
"codegen.vsetivli": 820,
"codegen.vsetvl": 820,
"codegen.vsetvli": 820,
"codegen.vsext_vf2": 134897,
"codegen.vsext_vf4": 19825,
"codegen.vslide1down_vx": 6151901,
Expand Down Expand Up @@ -435,14 +435,14 @@
"codegen.vxor_vx": 84861,
"codegen.vzext_vf2": 134897,
"codegen.vzext_vf4": 19825,
"rvv_bench.ascii_to_utf16": 1371567,
"rvv_bench.ascii_to_utf32": 583336,
"rvv_bench.ascii_to_utf16": 1371586,
"rvv_bench.ascii_to_utf32": 583329,
"rvv_bench.byteswap": 3556325,
"rvv_bench.chacha20": 2,
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"rvv_bench.poly1305": 3,
"rvv_bench.strlen": 715092,
"rvv_bench.utf8_count": 4797064
}

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