From 1de77d01f844c5a1dcb0e945f0ced7653bbbf8c2 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Sun, 28 Jul 2024 16:52:21 +0800 Subject: [PATCH] [ipemu] gate dpi call with !reset to work around verilator scheduling bug --- ipemu/src/TestBench.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ipemu/src/TestBench.scala b/ipemu/src/TestBench.scala index 9c2c2dbe2..15053fcc1 100644 --- a/ipemu/src/TestBench.scala +++ b/ipemu/src/TestBench.scala @@ -112,7 +112,7 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) extends val issue = WireDefault(0.U.asTypeOf(new Issue)) val fence = RegInit(false.B) val outstanding = RegInit(0.U(4.W)) - val doIssue: Bool = dut.request.ready && !fence + val doIssue: Bool = dut.request.ready && !fence && !reset // used to gate Xprop when DPI hasn't issued yet. val didIssue = RegNext(doIssue, false.B) outstanding := outstanding + (doIssue && (issue.meta === 1.U)) - dut.response.valid