diff --git a/t1/src/Bundles.scala b/t1/src/Bundles.scala
index 59b317b5b..492fc195d 100644
--- a/t1/src/Bundles.scala
+++ b/t1/src/Bundles.scala
@@ -138,6 +138,8 @@ class LaneRequest(param: LaneParameter) extends Bundle {
   /** data of rs1 */
   val readFromScalar: UInt = UInt(param.datapathWidth.W)
 
+  val csrInterface: CSRInterface = new CSRInterface(param.vlMaxBits)
+
   // vmacc 的vd需要跨lane读 TODO: move to [[V]]
   def ma: Bool =
     decodeResult(Decoder.multiplier) && decodeResult(Decoder.uop)(1, 0).xorR && !decodeResult(Decoder.vwmacc)
@@ -220,10 +222,6 @@ class InstructionControlRecord(param: LaneParameter) extends Bundle {
   /** Store request from [[T1]]. */
   val laneRequest: LaneRequest = new LaneRequest(param)
 
-  /** csr follows the instruction. TODO: move to [[laneRequest]]
-    */
-  val csr: CSRInterface = new CSRInterface(param.vlMaxBits)
-
   /** which group is the last group for instruction. */
   val lastGroupForInstruction: UInt = UInt(param.groupNumberBits.W)
 
diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
index 7af7f3800..8a481c3ee 100644
--- a/t1/src/Lane.scala
+++ b/t1/src/Lane.scala
@@ -234,11 +234,6 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
   @public
   val laneRequest: DecoupledIO[LaneRequest] = IO(Flipped(Decoupled(new LaneRequest(parameter))))
 
-  /** CSR Interface. TODO: merge to [[laneRequest]]
-    */
-  @public
-  val csrInterface: CSRInterface = IO(Input(new CSRInterface(parameter.vlMaxBits)))
-
   @public
   val maskUnitRequest: ValidIO[MaskUnitExeReq] = IO(Valid(new MaskUnitExeReq(parameter)))
 
@@ -325,6 +320,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
 
   // TODO: remove
   dontTouch(writeBusPort)
+  val csrInterface: CSRInterface = laneRequest.bits.csrInterface
 
   /** VRF instantces. */
   val vrf: Instance[VRF] = Instantiate(new VRF(parameter.vrfParam))
@@ -556,7 +552,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
       record.laneRequest.decodeResult(Decoder.maskLogic)
 
     /** onehot value of SEW. */
-    val vSew1H: UInt = UIntToOH(record.csr.vSew)(2, 0)
+    val vSew1H: UInt = UIntToOH(record.laneRequest.csrInterface.vSew)(2, 0)
 
     /** if asserted, the element won't be executed. adc: vm = 0; madc: vm = 0 -> s0 + s1 + c, vm = 1 -> s0 + s1
       */
@@ -612,7 +608,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
     laneState.lastGroupForInstruction  := record.lastGroupForInstruction
     laneState.isLastLaneForInstruction := record.isLastLaneForInstruction
     laneState.instructionFinished      := record.instructionFinished
-    laneState.csr                      := record.csr
+    laneState.csr                      := record.laneRequest.csrInterface
     laneState.maskType                 := record.laneRequest.mask
     laneState.maskNotMaskedElement     := !record.laneRequest.mask ||
       record.laneRequest.decodeResult(Decoder.maskSource) ||
@@ -944,7 +940,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
     )
     maskSelectSew     := Mux1H(
       maskSelectArbitrator,
-      csrInterface.vSew +: slotControl.map(_.csr.vSew)
+      csrInterface.vSew +: slotControl.map(_.laneRequest.csrInterface.vSew)
     )
   }
 
@@ -955,8 +951,6 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
   val maskLogicCompleted: Bool =
     laneRequest.bits.decodeResult(Decoder.maskLogic) &&
       (laneIndex ## 0.U(parameter.datapathWidthBits.W) >= csrInterface.vl)
-  // latch CSR from V
-  entranceControl.csr := csrInterface
 
   entranceControl.laneRequest         := laneRequest.bits
   // TODO: in scalar core, raise illegal instruction exception when vstart is nonzero.
diff --git a/t1/src/T1.scala b/t1/src/T1.scala
index dc08f788f..f011dbfb2 100644
--- a/t1/src/T1.scala
+++ b/t1/src/T1.scala
@@ -734,11 +734,12 @@ class T1(val parameter: T1Parameter)
     lane.laneRequest.bits.mask       := maskType
     laneReady(index)                 := lane.laneRequest.ready
 
-    lane.csrInterface      := requestRegCSR
+    // connect csrInterface
+    lane.laneRequest.bits.csrInterface := requestRegCSR
     // index type EEW Decoded in the instruction
-    lane.csrInterface.vSew := vSewSelect
-    lane.csrInterface.vl   := evlForLane
-    lane.laneIndex         := index.U
+    lane.laneRequest.bits.csrInterface.vSew := vSewSelect
+    lane.laneRequest.bits.csrInterface.vl   := evlForLane
+    lane.laneIndex                          := index.U
 
     // lsu 优先会有死锁:
     // vmadc, v1, v2, 1 (vl=17) -> 需要先读后写