From 10ad9f4c26367770418f67886c24fee3e64028e2 Mon Sep 17 00:00:00 2001
From: qinjun-li <liqinjun1994@gmail.com>
Date: Thu, 19 Dec 2024 17:44:21 +0800
Subject: [PATCH] [rtl] Add read token in store unit.

---
 t1/src/lsu/SimpleAccessUnit.scala |  4 ++++
 t1/src/lsu/StoreUnit.scala        | 26 ++++++++++++++------------
 2 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/t1/src/lsu/SimpleAccessUnit.scala b/t1/src/lsu/SimpleAccessUnit.scala
index d7409500b..bc517d5eb 100644
--- a/t1/src/lsu/SimpleAccessUnit.scala
+++ b/t1/src/lsu/SimpleAccessUnit.scala
@@ -120,6 +120,10 @@ case class MSHRParam(
   // outstanding of MaskExchangeUnit.maskReq
   // todo: param from T1Param
   val maskRequestQueueSize: Int = 8
+
+  // outstanding of StoreUnit.vrfReadDataPorts
+  // todo: param from T1Param
+  val storeUnitReadOutStanding: Int = 8
 }
 
 /** Miss Status Handler Register this is used to record the outstanding memory access request for each instruction. it
diff --git a/t1/src/lsu/StoreUnit.scala b/t1/src/lsu/StoreUnit.scala
index a4e125296..00f261a4b 100644
--- a/t1/src/lsu/StoreUnit.scala
+++ b/t1/src/lsu/StoreUnit.scala
@@ -62,8 +62,9 @@ class StoreUnit(param: MSHRParam) extends StrideBase(param) with LSUPublic {
   // todo: need hazardCheck?
   val hazardCheck:     Bool               = RegEnable(vrfReadyToStore && !lsuRequest.valid, false.B, lsuRequest.valid || vrfReadyToStore)
   // read stage dequeue ready need all source valid, Or add a queue to coordinate
-  val vrfReadQueueVec: Seq[QueueIO[UInt]] =
-    Seq.tabulate(param.laneNumber)(_ => Queue.io(UInt(param.datapathWidth.W), 2, flow = true, pipe = true))
+  val vrfReadQueueVec: Seq[QueueIO[UInt]] = Seq.tabulate(param.laneNumber)(_ =>
+    Queue.io(UInt(param.datapathWidth.W), param.storeUnitReadOutStanding, flow = true, pipe = true)
+  )
 
   // 从vrf里面读数据
   val readStageValid: Bool = Seq
@@ -72,10 +73,6 @@ class StoreUnit(param: MSHRParam) extends StrideBase(param) with LSUPublic {
       val segPtr:    UInt                        = RegInit(0.U(3.W))
       val readCount: UInt                        = RegInit(0.U(dataGroupBits.W))
       val stageValid = RegInit(false.B)
-      // queue for read latency
-      // todo: param.vrfReadLatency => param.vrfReadLatency + shifterLatency
-      val queue: QueueIO[UInt] =
-        Queue.io(UInt(param.datapathWidth.W), param.vrfReadLatency, flow = true)
 
       val lastReadPtr: Bool = segPtr === 0.U
 
@@ -105,8 +102,14 @@ class StoreUnit(param: MSHRParam) extends StrideBase(param) with LSUPublic {
         readCount := nextReadCount
       }
 
+      val readCounter = RegInit(0.U(log2Ceil(param.storeUnitReadOutStanding + 1).W))
+      val counterChange: UInt = Mux(readPort.fire, 1.U, -1.S(readCounter.getWidth.W).asUInt)
+      when(readPort.fire ^ vrfReadQueueVec(laneIndex).deq.fire) {
+        readCounter := readCounter + counterChange
+      }
+
       // vrf read request
-      readPort.valid                 := stageValid && vrfReadQueueVec(laneIndex).enq.ready
+      readPort.valid                 := stageValid && !readCounter.asBools.last
       readPort.bits.vs               :=
         lsuRequestReg.instructionInformation.vs3 +
           segPtr * segmentInstructionIndexInterval +
@@ -116,11 +119,10 @@ class StoreUnit(param: MSHRParam) extends StrideBase(param) with LSUPublic {
       readPort.bits.instructionIndex := lsuRequestReg.instructionIndex
 
       // latency queue enq
-      queue.enq.valid := vrfReadResults(laneIndex).valid
-      queue.enq.bits  := vrfReadResults(laneIndex).bits
-      AssertProperty(BoolSequence(!queue.enq.valid || queue.enq.ready))
-      vrfReadQueueVec(laneIndex).enq <> queue.deq
-      stageValid || RegNext(readPort.fire)
+      AssertProperty(BoolSequence(!vrfReadQueueVec(laneIndex).enq.valid || vrfReadQueueVec(laneIndex).enq.ready))
+      vrfReadQueueVec(laneIndex).enq.valid := vrfReadResults(laneIndex).valid
+      vrfReadQueueVec(laneIndex).enq.bits  := vrfReadResults(laneIndex).bits
+      stageValid || readCounter.orR
     }
     .reduce(_ || _)