You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
I am building my SystemVerilog code with synlig and when yosys goes to create the UHDM model and I get an error. I am getting the following output before the ERROR:
[NTE:EL0503] /mnt/c/projects/SV_2/rtl_vlog/top/top.sv:20:1: Top level module "work@top".
[NTE:EL0508] Nb Top level modules: 1.
[NTE:EL0509] Max instance depth: 8.
[NTE:EL0510] Nb instances: 1170.
[NTE:EL0511] Nb leaf instances: 297.
[INF:UH0706] Creating UHDM Model...
[ FATAL] : 0
[ SYNTAX] : 0
[ ERROR] : 0
[WARNING] : 0
[ NOTE] : 5
ERROR: Assert `inst' failed in /mnt/c/projects/github/synlig-main/frontends/systemverilog/uhdm_ast.cc:2739.
I am using the following commands to load the files:
plugin -i systemverilog
... (Use same include files and package file in all the file calls)
read_systemverilog -defer ../rtl_vlog/defs/register_defs.sv ../rtl_vlog/defs/defs.sv ../rtl_vlog/defs/RTL_asic_synth_pkg.sv ../rtl_vlog/top/top.sv
read_systemverilog -link
Apologies if I have not included all the information you require as I am a new user to synlig.
Thanks
The text was updated successfully, but these errors were encountered:
Hello again. I tried creating the uhdm file first with Surelog and then read it into Yosys and I get the same error listed above. So Surelog outputs:
[NTE:EL0503] /mnt/c/projects/SV_2/rtl_vlog/top/top.sv:20:1: Top level module "work@top".
[NTE:EL0508] Nb Top level modules: 1.
[NTE:EL0509] Max instance depth: 8.
[NTE:EL0510] Nb instances: 1170.
[NTE:EL0511] Nb leaf instances: 297.
[INF:UH0706] Creating UHDM Model...
[INF:UH0708] Writing UHDM DB: /mnt/c/projects/SV_2/synthesis/slpp_all/surelog.uhdm ...
[ FATAL] : 0
[ SYNTAX] : 0
[ ERROR] : 0
[WARNING] : 15
[ NOTE] : 9
Hello,
I am building my SystemVerilog code with synlig and when yosys goes to create the UHDM model and I get an error. I am getting the following output before the ERROR:
[NTE:EL0503] /mnt/c/projects/SV_2/rtl_vlog/top/top.sv:20:1: Top level module "work@top".
[NTE:EL0508] Nb Top level modules: 1.
[NTE:EL0509] Max instance depth: 8.
[NTE:EL0510] Nb instances: 1170.
[NTE:EL0511] Nb leaf instances: 297.
[INF:UH0706] Creating UHDM Model...
[ FATAL] : 0
[ SYNTAX] : 0
[ ERROR] : 0
[WARNING] : 0
[ NOTE] : 5
ERROR: Assert `inst' failed in /mnt/c/projects/github/synlig-main/frontends/systemverilog/uhdm_ast.cc:2739.
I am using the following commands to load the files:
plugin -i systemverilog
... (Use same include files and package file in all the file calls)
read_systemverilog -defer ../rtl_vlog/defs/register_defs.sv ../rtl_vlog/defs/defs.sv ../rtl_vlog/defs/RTL_asic_synth_pkg.sv ../rtl_vlog/top/top.sv
read_systemverilog -link
Apologies if I have not included all the information you require as I am a new user to synlig.
Thanks
The text was updated successfully, but these errors were encountered: