diff --git a/src/frontends/systemverilog/uhdm_ast.cc b/src/frontends/systemverilog/uhdm_ast.cc
index e19fce4b3..ed04cb736 100644
--- a/src/frontends/systemverilog/uhdm_ast.cc
+++ b/src/frontends/systemverilog/uhdm_ast.cc
@@ -2380,6 +2380,19 @@ void UhdmAst::simplify_parameter(AST::AstNode *parameter, const std::vector<::Yo
             }
         });
     }
+    auto ancestor_node = this;
+    while (ancestor_node) {
+        if (ancestor_node->current_node) {
+            visitEachDescendant(ancestor_node->current_node, [&](AST::AstNode *current_scope_node) {
+                if (current_scope_node->type == AST::AST_TYPEDEF || current_scope_node->type == AST::AST_PARAMETER ||
+                    current_scope_node->type == AST::AST_LOCALPARAM || current_scope_node->type == AST::AST_FUNCTION) {
+                    AST_INTERNAL::current_scope[current_scope_node->str] = current_scope_node;
+                }
+            });
+        }
+        ancestor_node = ancestor_node->parent;
+    }
+
     // first apply custom simplification step if needed
     simplify_sv(parameter, nullptr);
     // workaround for yosys sometimes not simplifying parameters children
diff --git a/tests/opentitan/opentitan_parsing_test/ot_cores_passlist.txt b/tests/opentitan/opentitan_parsing_test/ot_cores_passlist.txt
index f91516f45..0b715e12b 100644
--- a/tests/opentitan/opentitan_parsing_test/ot_cores_passlist.txt
+++ b/tests/opentitan/opentitan_parsing_test/ot_cores_passlist.txt
@@ -46,6 +46,7 @@ lowrisc:ip:rom_ctrl:0.1
 lowrisc:ip:rom_ctrl_pkg:0.1
 lowrisc:ip:rstmgr_cnsty_chk:0
 lowrisc:ip:rstmgr_reg:0.1
+lowrisc:ip:rv_core_ibex:0.1
 lowrisc:ip:rv_core_ibex_pkg:0.1
 lowrisc:ip:rv_dm:0.1
 lowrisc:ip:rv_plic_component:0.1