From 4018ab35e45b5566a3bec2f99ab48685b4a43000 Mon Sep 17 00:00:00 2001
From: Tomasz Gorochowik <tgorochowik@antmicro.com>
Date: Fri, 29 Sep 2023 15:04:17 +0200
Subject: [PATCH] Fork edif pass

This allows us to use latest yosys. The upstream edif pass introduced
changes which are incompatible with SystemVerilog.

Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
---
 .../systemverilog/uhdm_common_frontend.cc     |  3 ++
 third_party/yosys_mod/edif.cc                 | 30 ++++++++++++++-----
 third_party/yosys_mod/edif.h                  |  4 +++
 3 files changed, 30 insertions(+), 7 deletions(-)
 create mode 100644 third_party/yosys_mod/edif.h

diff --git a/frontends/systemverilog/uhdm_common_frontend.cc b/frontends/systemverilog/uhdm_common_frontend.cc
index 8970eabad..203e867ad 100644
--- a/frontends/systemverilog/uhdm_common_frontend.cc
+++ b/frontends/systemverilog/uhdm_common_frontend.cc
@@ -18,6 +18,7 @@
  */
 
 #include "uhdm_common_frontend.h"
+#include "edif.h"
 
 namespace systemverilog_plugin
 {
@@ -30,6 +31,8 @@ static void set_line_num(int) {}
 /* Stub for AST::process */
 static int get_line_num(void) { return 1; }
 
+UhdmCommonFrontend::UhdmCommonFrontend(std::string name, std::string short_help) : Frontend(name, short_help) { register_synlig_edif_backend(); }
+
 void UhdmCommonFrontend::print_read_options()
 {
     log("    -noassert\n");
diff --git a/third_party/yosys_mod/edif.cc b/third_party/yosys_mod/edif.cc
index 60d15a675..8abe883fc 100644
--- a/third_party/yosys_mod/edif.cc
+++ b/third_party/yosys_mod/edif.cc
@@ -27,8 +27,10 @@
 #include "kernel/sigtools.h"
 #include <string>
 
-USING_YOSYS_NAMESPACE
-PRIVATE_NAMESPACE_BEGIN
+namespace systemverilog_plugin
+{
+
+using namespace ::Yosys;
 
 #define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str()
 #define EDIF_DEFR(_id, _ren, _bl, _br) edif_names(RTLIL::unescape_id(_id), true, _ren, _bl, _br).c_str()
@@ -86,8 +88,8 @@ struct EdifNames {
     }
 };
 
-struct EdifBackend : public Backend {
-    EdifBackend() : Backend("edif", "write design to EDIF netlist file") {}
+struct SynligEdifBackend : public Backend {
+    SynligEdifBackend() : Backend("edif", "write design to EDIF netlist file") {}
     void help() override
     {
         //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@@ -129,7 +131,7 @@ struct EdifBackend : public Backend {
     }
     void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
     {
-        log_header(design, "Executing EDIF backend.\n");
+        log_header(design, "Executing Synlig EDIF backend.\n");
         std::string top_module_name;
         bool port_rename = false;
         bool attr_properties = false;
@@ -598,6 +600,20 @@ struct EdifBackend : public Backend {
 
         *f << stringf(")\n");
     }
-} EdifBackend;
+};
+
+SynligEdifBackend *seb = NULL;
+;
+
+void register_synlig_edif_backend()
+{
+    if (seb == NULL) {
+        backend_register.erase("edif");
+        pass_register.erase("edif");
+        pass_register.erase("write_edif");
+        seb = new SynligEdifBackend;
+        seb->init_register();
+    }
+}
 
-PRIVATE_NAMESPACE_END
+} // namespace systemverilog_plugin
diff --git a/third_party/yosys_mod/edif.h b/third_party/yosys_mod/edif.h
new file mode 100644
index 000000000..e877bbc41
--- /dev/null
+++ b/third_party/yosys_mod/edif.h
@@ -0,0 +1,4 @@
+namespace systemverilog_plugin
+{
+void register_synlig_edif_backend();
+}